Foundry 3D Chiplets

TSMC ,SAMSUNG, INTEL foundry's with 3-D dimensions and technology nodes
By
N.Sai Lokesh Kumar
Introduction
The three leading-edge foundries — Intel, Samsung, and TSMC have started filling in some key pieces
in their roadmaps, adding for future generations of chip technology and setting the stage for significant
improvements in performance with faster time for custom designs.
Roadmaps for all three show that transistor scaling will continue at least into the 18/16/14
angstrom range, with a possible move from nanosheets and forksheet FETs, followed by
complementary FETs (CFETs) at some point in the future
All three foundries are working on full 3D-ICs, as well. And there will be hybrid options
available, where logic is stacked on logic and mounted on a substrate, but separated from other features
in order to minimize physical effects such as heat a heterogeneous configuration that has been called
both 3.5D and 5.5D.
TSMC’s 3D approach. Source: TSMC
TSMC has experimented with a number of different options, including both RDL and non-RDL
bridges, 2.5D chip-on-wafer-on-substrate (CoWoS), and System On Integrated Chips (SoIC), a 3D-IC
concept in which chiplets are packed and stacked inside a substrate using very short interconnects.
This approach allows any of its packaging approaches InFO, CoWoS, and SoIC. It’s also essential to
TSMC’s business model, because the company is the only pure-play foundry of the three.
TSMC’s scaling roadmap into the angstrom era. Source: TSMC
Intel’s Foveros Direct 3D. Source: Intel
Intel, its Foveros Direct 3D to stack logic on logic, either face-to-face or face-to-back. The approach
allows chips or wafers from different foundries, with the connection bandwidth determined by the copper
via pitch, according to a new Intel paper. The paper noted that the first version would use a copper pitch
of 9µm, while the second generation would use a 3µm pitch.
Foveros allows an active logic die to be stacked on either another active or passive die, with the
base die used to connect all the die in a package at a 36 micron pitch. Intel claims it can guarantee 99%
known good die, and 97% yield at post-assembly test.
Intel’s process roadmap. Source: Intel Foundry
Samsung’s 3D-IC architecture for AI. Source: Samsung
Samsung followed with its own system description language, 3DCODE,The focus increasingly is about
latency and performance per watt in a specific domain, and this is where stacking logic-on-logic in a true 3D-
IC configuration, using hybrid bonds to connect chiplets to a substrate and each other. Moving electrons
through a wire on a planar die is still the fastest (assuming a signal doesn’t have to travel from one end of the
die to another), but stacking transistors on top of other transistors is the next best thing, and in some cases
even better than a planar SoC because some vertical signal paths may be shorter.
Samsung’s process scaling roadmap. Source: Samsung Foundry
Combining a 2nm (SF2) die on top of a 4nm (SF4X) die, both mounted on top of another substrate. This
is basically a 3D-IC on a 2.5D package, which is the 3.5D or 5.5D concept. The foundry will begin
stacking an SF1.4 on top of SF2P, starting in 2027. What’s particularly attractive about this approach are
the thermal dissipation possibilities. With the logic separated from other functions, heat can be channeled
away from the stacked dies through the substrate.
Samsung roadmap and innovations. Source: Semiconductor Engineering/MemCon 2024
Samsung has started detailing plans which includes 3D DRAM stacks with a configurable logic layer
underneath. This is the second time around for this approach, Samsung and Micron co-developed the
Hybrid Memory Cube, packaging a DRAM stack on a layer of logic. Memory is one of the key elements
that determine performance, and the ability to read/write and move data back and forth more quickly
between memory and processors can have a big impact on performance and power.
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TSMC ,SAMSUNG, INTEL foundry's with 3-D dimensions and technology nodes

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