Asynchronous Inputs to Synchronous Systems

• Many synchronous systems need to interface to asynchronous input signals:

– Consider a computer system running at some clock frequency, say 1GHz with:
• Interrupts from I/O devices, keystrokes, etc.
• Data transfers from devices with their own clocks
– Ethernet has its own 100MHz clock
– PCI bus transfers, 66MHz standard clock.
– These signals could have no known timing relationship with the system clock of the CPU.

“Synchronizer” Circuit
• For a single asynchronous input, we use a simple flip-flop to bring the external input signal into the
timing domain of the system clock:

• The D flip-flop samples the asynchronous input at each cycle and produces a synchronous
output that meets the setup time of the next stage.
• It is essential for asynchronous inputs to be synchronized at only one place.
Only ONE synchronizer per input
Two flip-flops may not receive the clock and input signals at precisely the same time (clock and data
skew). When the asynchronous input changes near the clock edge, one flip-flop may sample input as 1
and the other as 0.
Metastability Resolution Time
• It denotes the maximum time that the output can remain metastable without causing
synchronizer (and system) failure.

tr= tclock - tcomb - tsetup

Recommended synchronizer design

Hope that FF1 settles down before “META” is sampled.

– In this case, “SYNCIN” is valid for almost a full clock period.
– Can calculate the probability of “synchronizer failure”
(FF1 still metastable when META sampled)
• As long as the clock period is greater than tr plus the FF2’s setup time, SYNCIN becomes a
synchronized copy of the asynchronous input on the next clock tick.
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• As long as the clock period is greater than tr
plus the FF2’s setup time, SYNCIN
becomes a synchronized copy of the
asynchronous input on the next clock tick.
Synchronizer Failure
• Synchronizer failure is said to occur if a system uses a synchronizer output while the output
is still in the metastable state.
• The way to avoid synchronizer failure is to ensure that the system waits “long enough”
before using a synchronizer’s output.
There are two ways to get a flip-flop out of the metastable state:
1.Force the flip-flop into a valid logic state using input signals that meet the published
specifications for minimum pulse width, setup time, and so on.
2.Wait “long enough,” so the flip-flop comes out of metastability on its own.
Solutions to Synchronizer Failure
• the probability of failure can never be reduced to 0, but it can be reduced
• slow down the system clock
-this gives the synchronizer more time to decay into a steady state synchronizer
failure becomes a big problem for very high speed systems
• use the fastest possible logic in the synchronizer
-this makes for a very sharp "peak" upon which to balance S or AS TTL D-FFs are
recommended
• cascade two synchronizers

Metastability and MTBF

• A synchronizer design is characterised by it’s Mean Time Between Failure (MTBF)
– A failure is declared when the first sync. FF goes metastable and the output is not resolved
before the 2nd. FF is clocked
– Depends on FF setup/hold and prop. times, clock rate and average rate of input change
– Different flip-flops can have greatly different MTBFs
– Even a “small” change of the clock can be significant
• The MTBF equation is:
For example, using a 74LS74 FF (T0 = 0.4s, τ= 1.5ns) at a clock rate of 10 MHz and in
input av. rate of change = 100 KHz
– tr = 80 ns (100 ns clock period - 20 ns tsu)
– MTBF = 3.6 ·1011 sec.
• If we just change the clock to 16 MHz, things get really strange
– tr = 42.5 ns (62.5 ns clock period - 20 ns tsu)
– MTBF = 3.1 sec.
Reliable synchronizers
• Reliable synchronizers can be built in two ways
– Use faster flip flops.
– Increase the value of tr in MTBF equation.
Multiple-cycle synchronizer

Best value that can be obtained for tr is tclk if tsetup is zero.

• In Multiple-cycle synchronizer tr can be in the order of n.tclk

tr=n.tclk-tsetup
De-skewed multiple-cycle synchronizer
Programmable Large-Scale Integration (LSI) techniques:
Programmable Large-Scale Integration (LSI) techniques involve designing and implementing
digital circuits using programmable devices that can be configured or programmed to perform
specific functions. These techniques offer flexibility, reusability, and the ability to create
complex digital systems without the need for custom chip designs. Some commonly used
programmable LSI techniques include:

1.Programmable Logic Arrays: PLAs, or Programmable Logic Arrays, are digital devices
used in digital circuit design to implement combinational logic functions. They provide a
flexible way to create custom logic functions without the need for custom chip designs. PLAs
are composed of an array of programmable AND gates and OR gates, allowing designers to
create complex logic functions by configuring the connections between these gates.

Here's how a typical PLA works:

1. AND Array: The AND array consists of multiple programmable AND gates, each
with multiple inputs. These inputs are connected to the inputs of the PLA (external
signals or inputs from previous logic gates). The AND gates generate intermediate
product terms based on the inputs.
2. OR Array: The OR array consists of programmable OR gates that take the outputs of
the AND gates as inputs. These OR gates combine the product terms generated by the
AND gates to create the desired logic functions.
3. Programming: The key feature of PLAs is their programmability. Users can program
the connections between the inputs, AND gates, and OR gates to define the logic
functions they want to implement. This is typically done using a hardware description
language (HDL) such as Verilog or VHDL.
4. Outputs: The outputs of the OR gates represent the outputs of the PLA, which can be
used as inputs to other logic gates, registers, or other components in a digital circuit.

PLAs offer several advantages:

• Custom Logic Functions: PLAs allow designers to implement custom logic

functions tailored to specific requirements, without the need for custom chip
fabrication.
• Flexibility: Changes to the logic functions can be made by reprogramming the PLA,
eliminating the need to design and fabricate new chips.
• Area Efficiency: PLAs can be more area-efficient than implementing the same logic
functions using discrete gates, especially for complex functions.
• Reduced Design Time: PLAs can speed up the design process by offering a
convenient way to prototype and iterate logic functions.

However, PLAs also have limitations:

• Limited Speed: The propagation delay through the programmable gates can limit the
speed of operation compared to custom-designed logic.
• Limited Complex Logic: While PLAs are good for implementing combinational
logic, they might not be as suitable for more complex sequential logic.
• Resource Constraints: The number of inputs, AND gates, and OR gates is limited in
a PLA, which can constrain the complexity of logic functions.
2.Programmable Array Logic:PAL, or Programmable Array Logic, is a type of digital
device used in digital circuit design to implement combinational logic functions. Similar to
PLAs (Programmable Logic Arrays), PALs offer flexibility in creating custom logic
functions without the need for custom chip designs. PALs consist of an array of
programmable AND gates followed by a fixed OR gate structure.

Here's how a typical PAL works:

1. AND Array: The AND array in a PAL consists of multiple programmable AND
gates. Each AND gate has multiple inputs, which can be connected to the device's
input pins, external signals, or outputs of other logic gates.
2. OR Gate Structure: Unlike PLAs, where the OR gates are programmable, PALs
have a fixed OR gate structure. The outputs of the AND gates are directly connected
to specific inputs of the OR gates. The OR gates combine the outputs of the AND
gates to generate the final logic outputs.
3. Programming: Programming a PAL involves configuring the connections between
the inputs, AND gates, and OR gates to define the desired logic functions. This
programming is typically done using a hardware description language (HDL) such as
Verilog or VHDL.
4. Outputs: The outputs of the OR gates represent the outputs of the PAL, which can be
used as inputs to other logic gates, registers, or other components in a digital circuit.

The main difference between PLAs and PALs is the fixed OR gate structure in PALs. While
this limits the flexibility compared to PLAs, it also simplifies the programming process and
can lead to faster propagation delays in the circuit.

Advantages of PALs include:

• Custom Logic Functions: PALs allow designers to implement custom logic

functions to meet specific requirements.
• Simplicity: The fixed OR gate structure simplifies the programming process
compared to PLAs.
• Faster Propagation Delays: The fixed OR gate structure can lead to shorter
propagation delays compared to some PLAs.

Disadvantages include:

• Limited Flexibility: The fixed OR gate structure limits the complexity of logic
functions that can be implemented.
• Less Suitable for Complex Logic: Like PLAs, PALs might not be as suitable for
implementing complex sequential logic.

PLD stands for Programmable Logic Device, which is a broad category of digital devices
used in digital circuit design to implement custom logic functions. PLDs include various
types of devices that can be programmed to perform specific logic operations, ranging from
simple combinational logic to more complex sequential logic. PLDs offer a flexible and
efficient way to create custom digital circuits without the need for custom chip designs.

There are three main types of PLDs:

1. Programmable Logic Arrays (PLAs): As mentioned earlier, PLAs consist of an

array of programmable AND gates followed by programmable OR gates. The
connections between the inputs, AND gates, and OR gates can be programmed to
create custom logic functions.
2. Programmable Array Logic (PAL): PALs have a similar structure to PLAs, but
they have a fixed OR gate structure. The AND gates are programmable, but the OR
gate connections are fixed. This simplifies the programming process compared to
PLAs.
3. Complex Programmable Logic Devices (CPLDs): CPLDs are a more advanced
form of PLDs that combine multiple logic elements, including flip-flops and
programmable logic blocks, to implement both combinational and sequential logic.
CPLDs are particularly suited for small to medium-scale designs.
4. Field-Programmable Gate Arrays (FPGAs): FPGAs are highly versatile PLDs that
contain an array of configurable logic blocks, interconnects, and I/O blocks. They can
be programmed to perform a wide range of logic functions, including complex
algorithms and specialized tasks.

PLDs are programmed using hardware description languages (HDLs) such as Verilog or
VHDL. Designers describe the desired logic functions in the HDL, and then the programming
tools compile the design into a format that can be loaded onto the PLD.

Advantages of PLDs include:

• Flexibility: PLDs offer the ability to create custom logic functions without custom
chip fabrication.
• Rapid Prototyping: PLDs are useful for rapidly prototyping and testing digital
designs.
• Iterative Design: Designers can easily modify and iterate their designs without the
need for new chip fabrication.

However, PLDs also have limitations:

• Speed and Delay: The propagation delay through programmable gates can limit the
speed of operation compared to custom-designed logic.
• Resource Constraints: PLDs have limitations on the number of inputs, gates, and
flip-flops available, which can restrict the complexity of logic functions.

Complex Programmable Logic Devices (CPLDs) are a type of programmable logic device
used in digital circuit design to implement both combinational and sequential logic functions.
CPLDs offer a higher level of integration and complexity compared to simpler programmable
logic devices like PALs (Programmable Array Logic) and GALs (Generic Array Logic).
CPLDs are designed to accommodate medium-scale digital designs, offering a balance
between the flexibility of programmable logic and the efficiency of custom-designed logic.
They consist of multiple logic blocks, interconnect resources, and input/output pins, all of
which can be configured to perform specific logic functions.

Key features of CPLDs include:

1. Logic Blocks: CPLDs contain a number of logic blocks, which typically consist of
combinational logic elements (AND gates) and sequential logic elements (flip-flops or
registers). These logic blocks can be programmed to perform specific functions.
2. Programmable Interconnect: The logic blocks in a CPLD are connected through
programmable interconnect resources. Designers can configure the interconnect to
create desired logic paths between different blocks.
3. I/O Pins: CPLDs have input and output pins that connect the device to external
signals and other components. These pins can be configured to serve as inputs,
outputs, or bidirectional signals.
4. Clock Distribution: CPLDs often include features for distributing clock signals
efficiently to the internal logic blocks. This is crucial for implementing sequential
logic.
5. Programmability: CPLDs are programmed using hardware description languages
(HDLs) like Verilog or VHDL. Designers write code that describes the desired logic
behavior, and software tools compile and program the CPLD accordingly.
6. Complex Logic Functions: CPLDs are capable of implementing both combinational
and sequential logic, making them suitable for designs that involve memory elements,
state machines, counters, and more.

Advantages of CPLDs include:

• Flexibility: CPLDs offer the flexibility of programmable logic, allowing designers to

create custom logic functions without custom chip fabrication.
• Integration: CPLDs integrate multiple logic blocks, interconnect resources, and I/O
pins on a single chip.
• Medium-Scale Designs: CPLDs are well-suited for medium-scale digital designs that
are more complex than what PALs or GALs can handle.

Disadvantages include:

• Limited Resources: CPLDs have limitations on the number of logic blocks, flip-
flops, and interconnect resources available, which can restrict the complexity of
designs.
• Propagation Delays: Like other programmable logic devices, CPLDs have inherent
propagation delays that can affect their speed.

Field-Programmable Gate Arrays (FPGAs) are semiconductor devices that offer a high
degree of flexibility in digital circuit design. FPGAs consist of an array of programmable
logic blocks, configurable interconnects, and input/output blocks. They can be configured by
the user to perform custom digital logic functions, making them a versatile platform for
implementing a wide range of applications.
Key characteristics and features of FPGAs include:

1. Configurable Logic Blocks (CLBs): CLBs are the fundamental building blocks of
FPGAs. They consist of Look-Up Tables (LUTs), flip-flops or registers, and other
logic elements. LUTs can be programmed to implement specific logic functions.
2. Configurable Interconnects: The interconnects within an FPGA can be programmed
to connect various logic blocks and input/output pins. This flexibility allows designers
to create custom signal paths.
3. Input/Output Blocks (IOBs): IOBs provide the interface between the FPGA and
external signals. They can be configured to accommodate different voltage levels and
signal standards.
4. Reconfigurability: One of the defining features of FPGAs is their ability to be
reconfigured multiple times. Designers can change the logic configuration to
implement different functions or adapt to changing requirements.
5. Hardware Description Languages (HDLs): FPGAs are programmed using
hardware description languages (HDLs) like Verilog or VHDL. Designers describe
the desired logic behavior in HDL, and software tools convert these descriptions into
a configuration bitstream that programs the FPGA.
6. Parallelism: FPGAs can perform multiple operations in parallel due to their array-
based architecture, making them suitable for tasks that require high-speed
computation.
7. Applications: FPGAs are used in various industries, including telecommunications,
aerospace, automotive, industrial automation, medical devices, signal processing,
cryptography, artificial intelligence, and more.
8. Prototyping and Development: FPGAs are commonly used for rapid prototyping
and development of digital systems. They allow designers to test and validate their
designs in a real hardware environment before producing custom ASICs (Application-
Specific Integrated Circuits).
9. Trade-offs: While FPGAs offer flexibility and rapid design iterations, they might
have slightly longer propagation delays and consume more power compared to
custom-designed ASICs optimized for specific tasks.
10. Complex Designs: Advanced FPGAs can include specialized hardware blocks such
as digital signal processors (DSPs), embedded memory blocks, and high-speed
transceivers, enabling the implementation of complex designs.
11. Ecosystem: The FPGA ecosystem includes design tools, libraries, IP cores (pre-
designed functional blocks), and development boards to facilitate the design and
implementation process.
12. Integration: Some FPGAs can integrate microprocessors or microcontrollers
alongside programmable logic, creating a System-on-Chip (SoC) that combines
hardware and software components.

Design Procedure for a sequential circuit:

The design procedure for sequential circuits involves a systematic process to create digital
circuits that utilize memory elements (like flip-flops) to store and manipulate information
over time.

Specification and Requirements:

 o Define the requirements and functionality of the sequential circuit. Determine
the inputs, outputs, and desired behavior.
2. State Diagram or State Table:
o Create a state diagram or state table that represents the different states the
circuit can be in and the transitions between them.
o Identify the inputs and outputs associated with each state transition.
3. State Encoding:
o Assign binary codes (state codes) to each state to uniquely identify them. The
choice of state encoding can affect the complexity of the circuit.
4. Next State Logic:
o Design the logic that determines the next state based on the current state and
input conditions. This logic usually involves a combination of logic gates,
truth tables, and Karnaugh maps.
5. Output Logic:
o Define the logic that generates the desired outputs based on the current state
and input conditions. This logic can also involve logic gates, truth tables, and
Karnaugh maps.
6. Flip-Flop Selection:
o Choose the appropriate type of flip-flops (e.g., D flip-flops, JK flip-flops)
based on the design requirements and the characteristics of the states.
7. State Transition Table:
o Create a state transition table that shows the current state, inputs, next state,
and outputs for each state transition.
8. Timing Considerations:
o Analyze timing requirements, including clock frequency and setup/hold times
for flip-flops, to ensure reliable operation.
9. Circuit Implementation:
o Implement the next state logic and output logic using combinational logic
gates (AND, OR, NOT gates).
o Connect the flip-flops according to the state encoding and state transition
table.
10. Testing and Simulation:
o Use simulation tools to test the sequential circuit's behavior under different
input sequences and conditions.
o Verify that the circuit meets the specified requirements and produces the
expected outputs.
11. Verification and Debugging:
o Analyze simulation results to identify and resolve any issues, such as
unintended state transitions or incorrect outputs.
12. Synthesis and Implementation:
o Convert the design into a hardware description language (HDL) code like
Verilog or VHDL.
o Use synthesis tools to map the HDL code to actual flip-flops and logic
elements available on the target hardware (e.g., FPGA or ASIC).
13. Physical Design:
o For ASICs, perform physical design tasks like placement and routing to create
the layout of the circuit on the silicon die.
14. Testing on Hardware:
o Program the design onto the target hardware (FPGA or ASIC) and perform
functional testing to validate the circuit's behavior.
15. Iterative Refinement:
o If necessary, iterate through the design process to refine the circuit based on
testing and feedback.