THE FIELD EFFECT TRANSISTOR (FET) – INTRODUCTION

FETs are a class of semiconductors that operate on an entirely different principle than
BJTs. As the name field-effect implies, conduction is controlled by an electric field
established by a voltage applied to the control terminal (the gate). However, unlike the
BJTs, with the FET, current is conducted by only one type of carrier ( electrons or holes)
depending on the type of FET (n channel or p channel) hence, the FET is also referred to
as the unipolar transistor. Both BJTs and FETs, are equally important and each offers distinct
advantages and has unique areas of application.]

FETs are used in most computer circuits (ICs) because of several important advantages
they have over BJTs. Compared to BJTs, FET transistors can be made quite small hence,
occupying a small silicon area on an IC chip. Their manufacturing process is also
relatively simple. Digital logic and memory functions can be implemented with circuits
that exclusively use MOSFETs. For these reasons, most very-large-scale integrated
(VLSI) circuits are made at present using MOS technology. examples include
microprocessor and memory chips. MOS technology has also been applied extensively in
the design of analog integrated circuits.
A particular kind of FET, the enhancement-type MOSFET is the most widely used field-
effect transistor.

STRUCTURE AND PHYSICAL OPERATION OF THE ENHANCEMENT-TYPE

METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
(MOSFET)

Fig.1 physical structure of enhancement type n-MOSFET. Physical structure of the

enhancement-type NMOS transistor: (a) perspective view; (b) cross section.
Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the oxide layer is in
the range of 0.02 to 0.1 m.

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Fig.1 shows the physical structure of the n-channel enhancement-type MOSFET. The
transistor is fabricated on a p-type substrate (which is a single-crystal silicon wafer) that
provides physical support for the device. Two heavily doped n-type regions, indicated by
n+ source and n+ drain regions, are created in the substrate. A thin layer of silicon
dioxide (SiO2), is grown on the surface of the substrate, covering the area between the
source and drain regions. Metal is deposited on top of the oxide layer to form the gate
electrode of the device. Metal contacts are also made to the source region, the drain
region and the substrate, also known as the body. The substrate forms pn junctions with
the source and drain regions. In normal operation, these pn junctions are kept reverse-
biased at all times. The two pn junctions (source-body and drain-body) are cut-off by
connecting the body to the source. Thus the substrate (body) will be considered as
having no effect on device operation and the Mosfet will be treated as a three-terminal
device. The gate (G), the Source (S) and the drain (D).

OPERATION WITH NO GATE VOLTAGE:

With no bias voltage applied to the gate, two back-to-back diodes exist in series between
drain and source. These diodes prevent current conduction from drain to source when a
voltage VDS is applied. The path between drain and source has a very high resistance of
the order of 1012

Figure 2: Mosfet operation with no gate voltage

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CREATING A CHANNEL FOR CURRENT FLOW:

Fig. 3 Creating an n-channel

Consider the next situation depicted in fig. 3. We have grounded the source and drain and
applied a positive voltage to the gate. (Since the source is grounded the gate voltage
appears in effect between gate and source and thus is denoted VGS). The positive gate
voltage causes in the first instance the free holes to be repelled from the region of the
substrate under the gate (the channel region). These holes are pushed downward into the
substrate, leaving behind a carrier-depletion region. The positive gate voltage also
attracts electrons from the n+ source and drain into the channel region.

Now if, a voltage is applied between drain and source, current flows through this induced
n-region, carried by the mobile electrons. The induced n region forms a channel for
current flow from source to drain. Thus, the MOSFET of figure 3 is called an n-channel
MOSFET or an NMOS transistor. [Note that an n channel MOSFET is created in a p type
substrate. The induced channel is also called an inversion layer]. The value of VGS at
which a sufficient number of mobile electrons accumulate in the channel region to form a
conducting channel is called the threshold voltage (Vt). In NMOS Vt is positive and lies
between 1 and 3 V.

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The positive gate voltage cause positive charges to accumulate on the top plate of the
capacitor (the gate electrode) and the corresponding negative charge of the bottom plate
is formed by the electrons in the induced channel. The charges which accumulate on the
gate cannot cross into the channel region because of the insulating effect of the oxide
layer. An electric field thus develops in the vertical direction. It is this field that controls
the amount of charge in the channel, and thus it determines the channel conductivity and,
in turn, the current that will flow through the channel when a voltage VDS is applied.

The PMOS transistor

A p-channel enhancement-type MOSFET (PMOS transistor) is fabricated on an n-type

substrate with p+ regions for the drain and source, and holes as charge carriers. The
device operates just like the n-channel device except that VDS and VGS are negative and
Vt is also negative. The current iD enters the source terminal and leaves through the drain.

PMOS versus NMOS

 NMOS devices can be made smaller

 They operate faster
 NMOS requires lower supply voltages
 Both NMOS and PMOS are utilized in the design of CMOS

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Complementary MOS technology (CMOS) employs transistors of both polarities.

Fig. 4. Cross section of a CMOS integrated circuit. Note that the NMOS is formed in a
separate p-type region, known as a p well. Another arrangement is also possible in which
a p-type body is used and the p device is formed in an n well.

APPLYING A SMALL VDS

Figure 5: An NMOS transistor with vGS > Vt and with a small vDS applied

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Consider the NMOS shown in figure 5, applying a positive voltage VDS between drain
and source, causes a current iD to flow through the induced n-channel. (Current is carried
by free electrons flowing from source to drain). The magnitude of iD depends on the
density of electrons in the channel, which in turn depends on the magnitude of VGS.

Figure 5.4. Shows a graph of iD against VDS for various values of VGS. We observe that
the MOSFET is operating as a linear resistance whose value is controlled by VGS. The
resistance is infinite for VGS  Vt and its value decreases as VGS exceeds Vt.

For VGS = Vt, the channel is just induced, and the current conducted iD is negligibly
small. As VGS exceeds Vt more electrons are attracted into the channel and the result is a
channel of increased conductance. The conductance of the channel is proportional to the
excess gate voltage (VGS - Vt). It follows that iD will be proportional to VGS - Vt and, of
course, the voltage VDS that causes iD to flow.

From the description above, one can say that for the MOSFET to conduct, a channel must
be induced. Then increasing VGS above the threshold voltage Vt enhances the channel,
hence the names enhancement-mode operation and enhancement-type MOSFET. Finally,
we note that the current that leaves the source terminal (iS) is equal to the current that
enters the drain terminal iD, and the gate current iG = 0

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OPERATION AS VDS IS INCREASED:

Fig. 6a Operation as VDS is Increased

let VGS be held constant and greater than Vt and therefore a channel is formed, as in
figure 6. VDS appears as a voltage drop across the length of the channel. That is as we
travel along the channel from source to drain, the voltage (measured relative to the
source) increases from 0 to VDS. The voltage between the gate and points along the
channel decreases from VGS (at the source end) to VGS - VDS at the drain end. Since the
channel depth depends on this voltage, we find that the channel is no longer of uniform
depth; rather, the channel takes the tapered form. For example, let’s take VGS to be 10 V
and VDS to be 5 V. at the source end of the mosfet, the channel depth would be equivalent
to 10 – 0 = 10, whilst at the drain end the channel depth would be equivalent to 10 – 5 =
5. As VDS is increased, the channel becomes more tapered and its resistance increases
correspondingly.

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Figure 6b: Pinched-off channel

Eventually at VGS - VDS = Vt (or VDS = VGS - Vt) the channel depth at the drain end
decreases to almost zero and the channel is said to be pinched-off. Increasing VDS
beyond this value has little effect (theoretically, no effect) on the channel shape, and the
current through the channel remains constant at the value reached for VDS (at which, VGS
- VDS = Vt). The drain current thus saturates at this value, and the MOSFET is said to
have entered the saturation region of operation.

The voltage VDS at which saturation occurs is denoted VDS sat

VDS sat = VGS - Vt

Obviously for every value of VGS  Vt, there is a corresponding value of VDS sat. The
device operates in the saturation region if VDS  VDS sat.
The region of the iD - VDS characteristic obtained for VDS  VDS sat , sat is called the
triode region.

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Figure 7

To help further in visualizing the effect of VDS, we show in fig. 8 sketches of the channel
as VDS is increased as UGS remains constant.

VDS ≥ VGS - Vt

VDS
Source Channel Drain

VDS = 0

Increasing VDS causes the channel to acquire a tapered shape. Eventually, as VDS reaches
VGS – Vt, the channel is pinched off at the drain end. Increasing VDS above VGS – Vt has
little effect (theoretically no effect) on the channel’s shape.

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EQUATIONS FOR DEVICE OPERATION

The iD - VDS characteristics, shown in fig.5.10b. are a family of curves, each measured at
a constant VGS. There are 3 distinct regions of operation: the cut off, the triode region and
the saturation region.

Saturation region - amplifier operation

Cut off
Triode - switch operations

The device is cut off when UGS Vt.

TRIODE REGION OF OPERATION (NMOS)

To operate the MOSFET in the triode region we must first induce a channel

VGS  Vt (Induced channel)

and keep VDS small enough so that the channel remain continuous. This is achieved by
ensuring that the gate-to-drain voltage is

VGD  Vt (continuous channel). ………*

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This condition can be stated explicitly in terms of VDS by writing:

VDS < VGS - Vt (continuous channel )………**

Either equation * or ** Can be used to ascertain triode - region operation. In words, the
n-channel enhancement-type MOSFET operates in the triode region when UGS is greater
than Vt and the drain voltage is lower than the gate voltage by at least Vt volts. Or put
simply; When the potential difference between gate and drain is greater than Vt, the
MOSFET is in triode region

In the triode region, the iD-VDS characteristics can be approximately described by the
relationship:

iD = K[2(VGS - Vt) VDS - VDS2] ………(1)

in which K is a device parameter given by;

K = ½ nCox(W/L) (Units A/V2).

n - physical constant known as the Electron Mobility. Its value in this case applies for
the electrons in the induced n-channel

Cox - Oxide capacitance; is the capacitance per unit area of the gate-to-body capacitor for
which oxide layer serves as dielectric.

L - length of channel
W - width

(Since for a given fabrication process the quantity ½ nCox is a constant (

approximately 10A/V2 for the standard NMOS process with a 0.1 -m oxide thickness),
the aspect ratio of the device (W/L) determines the conductivity parameter K).

If VDS is sufficiently small so that we can neglect V2DS term in equation 1. We obtain for
the iD - VDS characteristic near the origin the following relationship;

iD = 2K (VGS - Vt) VDS

this linear relation represents the operation of the MOS transistor as a linear resistance rDS

rDS = VDS = [2K (VGS - Vt)]-1

iD
Whose value is controlled by VGS.

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SATURATION REGION OF OPERATION (NMOS)

To operate the MOSFET in the saturation region, a channel has to be induced;

VGS Vt (induced channel)

And pinched of at the drain end by raising VDS to a value that results in the gate to drain
voltage falling below Vt,

VGD ≤ Vt (pinched of channel)

This condition can be expressed explicitly in terms of VDS as;

VDS  VGS - Vt (pinched of channel)

Thus, the n-channel enhancement type MOSFET operates in the saturation region when
UGS is greater than Vt. and the drain voltage does not fall below the gate voltage by more
than Vt. Volts. Or when the potential difference between gate and drain becomes equal to
or less than Vt, the MOSFET enters saturation region.
The boundary between the triode region and the saturation region is characterized by;

VDS = VGS - Vt.

Substituting this into equation (1), gives the saturation value of the current i D as;

iD = K(VGS - Vt)2……………………3
thus, in saturation, the MOSFET provides a drain current whose value is independent of
the voltage VDS and is determined by the gate voltage VGS according to the square law
relationship shown in the equation (3) above.

EQUATIONS FOR A P-CHANNEL MOSFET

For a p-channel device the threshold voltage Vt. Is negative. To induce a channel we
apply a gate voltage that is more negative than Vt.

VGS = ≤ Vt. (induced channel)

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And apply a drain voltage that is more negative than the source voltage (i.e. VDS is
negative or equivalently VSD is positive). The current iD flows out of the drain terminal.
To operate in the triode region VDS must satisfy;

VDS VGS - Vt. ( continuous channel )

That is the drain voltage must be higher than the gate voltage by at least |Vt.|. The current
iD is given by the same equation as for NMOS,

iD = K[2(VGS - Vt) VDS - VDS2]

where VGS, Vt. And VDS are negative and K is given by;

K = ½ pCox(W/L)

Where p is the mobility of holes in the induced p-channel. Typically,

p = ½n
with the result that for the same W/L ratio, a PMOS transistor has half the value of K as
the NMOS.

To operate in saturation VDS must satisfy;

VDS ≤ VGS - Vt. (pinched of channel)

The current iD is given by the same equation used for NMOS;

iD = K(VGS - Vt)2
Where VGS and Vt. Are negative.

Channel length modulation

When we say iD is independent of VDS in saturation and therefore the output resistance at
the drain is infinite, we are talking about an ideal case. In practice, increasing VDS above
VDSsat moves the channel pinch-off point slightly away from the drain toward the source.
Thus the effective channel length is reduced. The slight linear dependence of iD on VDS in
the saturation region can be analytically accounted for by incorporating the function 1 +
VDS in the iD equation as follows:

iD = K(VGS - Vt.)2(1 + VDS)

where VA = 1/

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the channel length modulation makes the output resistance in saturation finite. Thus
incremental output resistance in saturation, ro is;

ro = [K(VGS - Vt.)2]-1

ro = [ID]-1

Where ID is the current corresponding to the particular value of UGS for which ro is being
evaluated. Sometimes ro = VA/ID.

NB. rDS is the drain-to-source resistance in the triode region for small VDS.

THE DEPLETION TYPE MOSFET

The depletion mode MOSFET shown as an N channel device (P channel is also available)
in Fig is more usually made as a discrete component, i.e. a single transistor rather than
IC form. In this device a thin layer of N type silicon is deposited just below the
gate−insulating layer, and forms a conducting channel between source and drain.

In other words, there is no need to induce a channel, unlike the case of the enhancement
MOSFET. Therefore when the gate source voltage VGS is zero, current (in the form of
free electrons) can flow between source and drain. The channel depth and hence its
conductivity can be controlled by VGS as in the enhancement type device. Applying a
positive VGS, enhances the channel by attracting the electrons into it, while a negative
VGS repels the electrons from the channel; and thus the channel becomes shallower and
its conductivity decreases.

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The negative VGS is said to deplete the channel of its charge carriers and this mode of
operation is called depletion mode. As the magnitude of VGS is increased in the negative
direction, a value is reached at which the channel is completely depleted of charge
carriers and iD is reduced to zero even though VDS may still be applied. This negative
value of VGS is the threshold voltage of the n-channel depletion type MOSFET.
The current-voltage characteristics of the depletion-type MOSFET are described by the
equations given in the previous section for the enhancement device except that, for an n-
channel depletion device, Vt. Is negative. Another parameter for the depletion MOSFET
is the value of drain current obtained in saturation with VGS=0. It is denoted, IDSS. It can
be shown that

IDSS = KVt2

MOS transistor types and symbols

D D

G G

S S
NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

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THE JUNCTION FIELD EFFECT TRANSISTOR (JFET)

(a) basic structure of n-channel JFET (b) Circuit symbol for the n-channel JFET (c) Circuit symbol for the
p-channel JFET

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PHYSICAL OPERATION:

In a junction field-effect transistor, or JFET, the controlled current passes from source to
drain, or from drain to source as the case may be. The controlling voltage is applied
between the gate and source. Note how the current does not have to cross through a PN
junction on its way between source and drain: the path (called a channel) is an
uninterrupted block of semiconductor material. In the image just shown, this channel is
an N-type semiconductor. P-type channel JFETs are also manufactured:

Lets consider an n-channel JFET with VGS=0, the application of a voltage VDS causes
current to flow from the drain to the source. When a negative VGS is applied the depletion
region of the gate-channel junction widens and the channel becomes correspondingly
narrower. Thus the channel resistance increases and the current iD ( for a given VDS)
decreases. Because VDS is small, the channel is almost of uniform width. The JFET is
simply operating as a resistance whose value is controlled by VGS. If we keep increasing
VGS in the negative direction, a value is reached at which the depletion region occupies
the entire channel. At this value of VGS the channel is completely depleted of charge
carriers (electrons); the channel has in effect disappeared. This value of VGS is therefore
the threshold voltage of the device Vt., which is obviously negative for an n-channel
JFET.

Current-Voltage Characteristics

For a JFET the saturation region is usually called the pinch-off region, and the threshold
voltage is usually called the pinch-off voltage and is denoted by, Vp, thus Vp=Vt.
Manufacturers usually specify the value of drain current at the onset of saturation for
UGS=0, denoted IDSS instead of the conductance parameter K. It can be easily shown that;

IDSS = KVt2 = KVp2

The JFET characteristics can be described by the same equations used for MOSFETs.
Specifically, re labeling Vt. As Vp, we can write;

The n-channel JFET will be cut off for; VGS <_ Vp where Vp is negative.

To turn the device on, we apply a gate-to-source voltage UGS.

Vp < VGS <_ 0

And a positive drain-to source voltage VDS. The JFET operates in the triode region for;

VDS <_ VGS - Vp

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In which case the drain current is given by;

iD = K[2(VGS - Vp)VDS - VDS2]

this can also be expressed below if Vp2 is extracted from the square brackets and we
replace KVp2 by IDSS.

iD = IDSS[2(1 - VGS/Vp)(VDS/-Vp) - (VDS/Vp)2]

The JFET operates in saturation (pinch-off) for; VDS  VGS - Vp

In words, for the JFET to operate in pinch-off, the drain voltage must be greater than the
gate voltage by at least |Vp|. In pinch-off, the drain current is given by

iD = IDSS(1 - VGS/Vp)2(1 + VDS)

Where   1/VA is a positive constant included to account for the dependence of iD on

VDS in a pinch-off.

The P-channel JFET

The equations are the same, however, Vp is positive, (0 <_ UGS <_ Vp). VDS is negative 
and VA are negative and the current iD flows out of the drain terminal. To operate the p-
channel JFET in pinch-off, VDS <_ UGS - Vp, which in words means that the drain voltage
must be lower than the gate voltage by at least |Vp|. Otherwise with UDS  UGS -Vp, the
p-channel JFET operates in the triode region.

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