Field Effect Transistor
2. MOSFET
MOSFET stands for metal – oxide – emiconductor field – effect transistor. MOSFETs are
further broken down into depletion type and enhancement type. The terms depletion and
enhancement define their basic mode of operation.
2.1 DEPLETION-TYPE MOSFET (D-MOSFET)
Basic Construction
The basic construction of the n -channel depletion-type MOSFET is provided in Fig. 10. A slab
of p -type material is formed from a silicon base and is referred to as the substrate. It is the
foundation on which the device is constructed. In some cases the substrate is internally
connected to the source terminal. However, many discrete devices provide an additional
terminal labeled SS , resulting in a four-terminal device. The source and drain terminals are
connected through metallic contacts to n -doped regions linked by an n -channel as shown in
the figure. The gate is also connected to a metal contact surface but remains insulated from the
n -channel by a very thin silicon dioxide (SiO2 ) layer. SiO2 is a type of insulator referred to as
a dielectric , which sets up opposing (as indicated by the prefix di -) electric fields within the
dielectric when exposed to an externally applied field. The fact that the SiO2 layer is an
insulating layer means that:
There is no direct electrical connection between the gate terminal and the channel of a
MOSFET.
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Field Effect Transistor
Fig.10. n-Channel depletion type MOSFET.
In addition:
It is the insulating layer of SiO 2 in the MOSFET construction that accounts for the very
desirable high input impedance of the device.
The reason for the label metal–oxide–semiconductor FET is now fairly obvious: metal for the
drain, source, and gate connections; oxide for the silicon dioxide insulating layer; and
semiconductor for the basic structure on which the n - and p -type regions are diffused.
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Field Effect Transistor
Basic Operation and Characteristics
In Fig. 11, the gate-to-source voltage is set to 0 V by the direct connection from one terminal
to the other, and a voltage VDD is applied across the drain-to-source terminals. The result is an
attraction of the free electrons of the n-channel for the positive voltage at the drain. The result
is a current similar to that flowing in the channel of the JFET. In fact, the resulting current with
VGS =0 V continues to be labeled IDSS , as shown in Fig. 12 .
Fig. 11. N-channel depletion type MOSFET with VGS=0V and applied voltage VDD.
In Fig. 12 , VGS is set at a negative voltage such as –1 V. The negative potential at the gate will
tend to pressure electrons toward the p -type substrate (like charges repel) and attract holes
from the p -type substrate (opposite charges attract) as shown in Fig. 12 . Depending on the
magnitude of the negative bias established by VGS , a level of recombination between electrons
and holes will occur that will reduce the number of free electrons in the n -channel available
forconduction. The more negative the bias, the higher is the rate of recombination.
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Field Effect Transistor
Fig. 12. Reduction in free carriers in a channel due to a negative potential
at the gate terminal.
The resulting level of drain current is therefore reduced with increasing negative bias for VGS ,
as shown in Fig. 13 for VGS = -1 V, -2 V, and so on, to the pinch-off level of -6 V. The resulting
levels of drain current and the plotting of the transfer curve proceed exactly as described for
the JFET.
Fig. 13. Drain and transfer characteristics for an n-channel depletion type MOSFET.
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Field Effect Transistor
For positive values of VGS , the positive gate will draw additional electrons (free carriers) from
the p -type substrate due to the reverse leakage current and establish new carriers through the
collisions resulting between accelerating particles. As the gate-to-source voltage continues to
increase in the positive direction, Fig.13 reveals that the drain current will increase at a rapid
rate for the reasons listed above. The vertical spacing between the VGS =0 V and VGS = +1 V
curves of Fig. 13 is a clear indication of how much the current has increased for the 1-V change
in VGS . Due to the rapid rise, the user must be aware of the maximum drain current rating since
it could be exceeded with a positive gate voltage. That is, for the device of Fig. 13, the
application of a voltage VGS = +4 V would result in a drain current of 22.2 mA, which could
possibly exceed the maximum rating (current or power) for the device. As revealed above, the
application of a positive gate-to-source voltage has “enhanced” the level of free carriers in the
channel compared to that encountered with VGS = 0 V. For this reason the region of positive
gate voltages on the drain or transfer characteristics is often referred to as the enhancement
region , with the region between cutoff and the saturation level of IDSS referred to as the
depletion region.
2.2 ENHANCEMENT-TYPE MOSFET
Basic Construction
The basic construction of the n -channel enhancement-type MOSFET is provided in Fig. 14 .
A slab of p -type material is formed from a silicon base and is again referred to as the substrate.
As with the depletion-type MOSFET, the substrate is sometimes internally connected to the
source terminal, whereas in other cases a fourth lead (labeled SS) is made available for external
control of its potential level. The source and drain terminals are again connected through
metallic contacts to n -doped regions, but in Fig. 6.32 the absence of a channel between the two
n -doped regions. This is the primary difference between the construction of depletion-type and
enhancement-type MOSFETs—the absence of a channel as a constructed component of the
device. The SiO2 layer is still present to isolate the gate metallic platform from the region
between the drain and source, but now it is simply separated from a section of the p-type
material. Therefore, we can say that the construction of an enhancement-type MOSFET is quite
similar to that of the depletion-type MOSFET, except for the absence of a channel between the
drain and source terminals.
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Field Effect Transistor
Fig. 14. n-Channel enhancement-type MOSFET.
Basic Operation and Characteristics
If VGS is set at 0 V and a voltage applied between the drain and the source of the device of Fig.
14 , the absence of an n -channel (with its generous number of free carriers) will result in a
current of effectively 0 A, wheras in case of JFET and MOSFET ID = IDSS. It is not sufficient
to have a large accumulation of carriers (electrons) at the drain and the source (due to the n
doped regions) if a path fails to exist between the two. With VDS some positive voltage, VGS at
0 V, and terminal SS directly connected to the source, there are in fact two reverse-biased p –
n junctions between the n -doped regions and the p -substrate to oppose any significant flow
between drain and source.
In Fig. 15, both VDS and VGS have been set at some positive voltage greater than 0 V,
establishing the drain and the gate at a positive potential with respect to the source.
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Field Effect Transistor
Fig. 15. Channel formation in the n-channel enhancement-type MOSFET.
The positive potential at the gate will pressure the holes (since like charges repel) in the p -
substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p -
substrate, as shown in the figure. The result is a depletion region near the SiO2 insulating layer
void of holes. However, the electrons in the p-substrate (the minority carriers of the material)
will be attracted to the positive gate and accumulate in the region near the surface of the SiO2
layer. The SiO2 layer and its insulating qualities will prevent the negative carriers from being
absorbed at the gate terminal. As VGS increases in magnitude, the concentration of electrons
near the SiO2 surface increases until eventually the induced n-type region can support a
measurable flow between drain and source. The level of VGS that results in the significant
increase in drain current is called the threshold voltage and is given the symbol VT . On
specification sheets it is referred to as VGS(Th), although VT is less unwieldy and will be used in
the analysis to follow. Since the channel is nonexistent with VGS =0 V and “enhanced” by the
application of a positive gate-to-source voltage, this type of MOSFET is called an
enhancement-type MOSFET. Both depletion- and enhancement-type MOSFETs have
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Field Effect Transistor
enhancement-type regions, but the label was applied to the latter since it is its only mode of
operation.
As VGS is increased beyond the threshold level, the density of free carriers in the induced
channel will increase, resulting in an increased level of drain current. However, if we hold VGS
constant and increase the level of VDS , the drain current will eventually reach a saturation level
as occurred for the JFET and depletion-type MOSFET. The leveling off of ID is due to a
pinching-off process depicted by the narrower channel at the drain end of the induced channel
as shown in Fig. 16.
Fig.16. Change in channel and depletion region with increasing level of VDS for a fixed value
of VGS.
Applying Kirchhoff’s voltage law to the terminal voltages of the MOSFET of Fig. 16., we find
that
VDG VDS VGS (1)
If VGS is held fixed at some value such as 8 V and VDS is increased from 2 V to 5 V, the voltage
VDG (by Eq.(1)) will increase from –6 V to –3 V and the gate will become less and less positive
with respect to the drain. This reduction in gate-to-drain voltage will in turn reduce the
attractive forces for free carriers (electrons) in this region of the induced channel, causing a
reduction in the effective channel width. Eventually, the channel will be reduced to the point
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Field Effect Transistor
of pinch-off and a saturation condition will be established as happen in the JFET and depletion-
type MOSFET. In other words, any further increase in VDS at the fixed value of VGS will not
affect the saturation level of ID until breakdown conditions are encountered.
The drain characteristics of Fig. 17 reveal that for the device of Fig. 14 with VGS = 8 V,
saturation occurs at a level of VDS = 6 V. In fact, the saturation level for VDS is related to the
level of applied VGS by
VDSsat VGS VT (2)
Obviously, therefore, for a fixed value of VT , the higher the level of VGS , the greater is the
saturation level for VDS , as shown in Fig. 14 by the locus of saturation levels.
Fig. 17. Drain characteristics of an n-channel enhancement-type MOSFET with VT =2V and
k 0.278 103 A V 2
For values of V GS less than the threshold level, the drain current of an enhancement-type
MOSFET is 0 mA.
Figure 17 clearly reveals that as the level of VGS increases from VT to 8 V, the resulting
saturation level for ID also increases from a level of 0 mA to 10 mA. In addition, it is quite
noticeable that the spacing between the levels of VGS increases as the magnitude of VGS
increases, resulting in ever-increasing increments in drain current. For levels of VGS >VT, the
drain current is related to the applied gate-to-source voltage by the following nonlinear
relationship:
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Field Effect Transistor
I D k VGS VT
2
(3)
The equation (3) shows a nonlinear (curved) relationship between ID and VGS . The k term is a
constant that is a function of the construction of the device. The value of k can be determined
from the equation (4),where I Don and VGS(on) are the values for each at a particular point on the
characteristics of the device.
I Don
k (4)
VGS (on) VT
2
Fig. 18. Sketching the transfer characteristics for an n- channel enhancement-type MOSFET
from the drain characteristics.
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