ever, since ID can extend beyond the IDSS level, another point is normally provided

that reflects a typical value of ID for some positive voltage (for an n-channel device).
For the unit of Fig. 5.30, ID is specified as ID(on)  9 mA dc, with VDS  10 V and
VGS  3.5 V.

5.8 ENHANCEMENT-TYPE MOSFET

Although there are some similarities in construction and mode of operation between
depletion-type and enhancement-type MOSFETs, the characteristics of the enhance-
ment-type MOSFET are quite different from anything obtained thus far. The transfer
curve is not defined by Shockley’s equation, and the drain current is now cut off un-
til the gate-to-source voltage reaches a specific magnitude. In particular, current con-
trol in an n-channel device is now effected by a positive gate-to-source voltage rather
than the range of negative voltages encountered for n-channel JFETs and n-channel
depletion-type MOSFETs.

Basic Construction
The basic construction of the n-channel enhancement-type MOSFET is provided in
Fig. 5.31. A slab of p-type material is formed from a silicon base and is again re-
ferred to as the substrate. As with the depletion-type MOSFET, the substrate is some-
times internally connected to the source terminal, while in other cases a fourth lead
is made available for external control of its potential level. The source and drain ter-
minals are again connected through metallic contacts to n-doped regions, but note in
Fig. 5.31 the absence of a channel between the two n-doped regions. This is the pri-
mary difference between the construction of depletion-type and enhancement-type
MOSFETs—the absence of a channel as a constructed component of the device. The
SiO2 layer is still present to isolate the gate metallic platform from the region be-
tween the drain and source, but now it is simply separated from a section of the
p-type material. In summary, therefore, the construction of an enhancement-type
MOSFET is quite similar to that of the depletion-type MOSFET, except for the ab-
sence of a channel between the drain and source terminals.

Figure 5.31 n-Channel enhancement-type MOSFET.

234 Chapter 5 Field-Effect Transistors

Basic Operation and Characteristics
If VGS is set at 0 V and a voltage applied between the drain and source of the device
of Fig. 5.31, the absence of an n-channel (with its generous number of free carriers)
will result in a current of effectively zero amperes—quite different from the deple-
tion-type MOSFET and JFET where ID  IDSS. It is not sufficient to have a large ac-
cumulation of carriers (electrons) at the drain and source (due to the n-doped regions)
if a path fails to exist between the two. With VDS some positive voltage, VGS at 0 V,
and terminal SS directly connected to the source, there are in fact two reverse-biased
p-n junctions between the n-doped regions and the p-substrate to oppose any signif-
icant flow between drain and source.
In Fig. 5.32 both VDS and VGS have been set at some positive voltage greater than
0 V, establishing the drain and gate at a positive potential with respect to the source.
The positive potential at the gate will pressure the holes (since like charges repel) in
the p-substrate along the edge of the SiO2 layer to leave the area and enter deeper re-
gions of the p-substrate, as shown in the figure. The result is a depletion region near
the SiO2 insulating layer void of holes. However, the electrons in the p-substrate (the
minority carriers of the material) will be attracted to the positive gate and accumu-
late in the region near the surface of the SiO2 layer. The SiO2 layer and its insulat-
ing qualities will prevent the negative carriers from being absorbed at the gate termi-
nal. As VGS increases in magnitude, the concentration of electrons near the SiO2 surface
increases until eventually the induced n-type region can support a measurable flow
between drain and source. The level of VGS that results in the significant increase in
drain current is called the threshold voltage and is given the symbol VT. On specifi-
cation sheets it is referred to as VGS(Th), although VT is less unwieldy and will be used
in the analysis to follow. Since the channel is nonexistent with VGS  0 V and “en-
hanced” by the application of a positive gate-to-source voltage, this type of MOSFET
is called an enhancement-type MOSFET. Both depletion- and enhancement-type MOS-
FETs have enhancement-type regions, but the label was applied to the latter since it
is its only mode of operation.

Electrons attracted to positive gate

(induced n-channel)
Region depleted of p-type
carriers (holes)

ID

D n
e
+ e +
+ e
+
IG = 0 A
+ + SS
+
e
G
e
+ p VDS
+ + +
+ e –
VGS + e
+
e
+
–
S n

IS = ID
Figure 5.32 Channel formation
Insulating layer Holes repelled in the n-channel enhancement-
by positive gate type MOSFET.

5.8 Enhancement-Type MOSFET 235

 As VGS is increased beyond the threshold level, the density of free carriers in the
induced channel will increase, resulting in an increased level of drain current. How-
ever, if we hold VGS constant and increase the level of VDS, the drain current will
eventually reach a saturation level as occurred for the JFET and depletion-type MOS-
FET. The leveling off of ID is due to a pinching-off process depicted by the narrower
channel at the drain end of the induced channel as shown in Fig. 5.33. Applying Kirch-
hoff’s voltage law to the terminal voltages of the MOSFET of Fig. 5.33, we find that

VDG  VDS  VGS (5.11)

Figure 5.33 Change in channel

and depletion region with increas-
ing level of VDS for a fixed value
of VGS.

If VGS is held fixed at some value such as 8 V and VDS is increased from 2 to 5
V, the voltage VDG [by Eq. (5.11)] will drop from 6 to 3 V and the gate will be-
come less and less positive with respect to the drain. This reduction in gate-to-drain
voltage will in turn reduce the attractive forces for free carriers (electrons) in this re-
gion of the induced channel, causing a reduction in the effective channel width. Even-
tually, the channel will be reduced to the point of pinch-off and a saturation condi-
tion will be established as described earlier for the JFET and depletion-type MOSFET.
In other words, any further increase in VDS at the fixed value of VGS will not affect
the saturation level of ID until breakdown conditions are encountered.
The drain characteristics of Fig. 5.34 reveal that for the device of Fig. 5.33 with
VGS  8 V, saturation occurred at a level of VDS  6 V. In fact, the saturation level
for VDS is related to the level of applied VGS by

VDSsat  VGS  VT (5.12)

Obviously, therefore, for a fixed value of VT, then the higher the level of VGS, the more
the saturation level for VDS, as shown in Fig. 5.33 by the locus of saturation levels.

236 Chapter 5 Field-Effect Transistors

 ID (mA)
Locus of VDSsat

11
10 VGS = +8 V

9
8
7 VGS = +7 V

6
5
VGS = +6 V
4
3
VGS = +5 V
2
1 VGS = +4 V
VGS = +3 V
0 5V 10 V 15 V 20 V 25 V VDS
6V VGS = V T = 2 V

Figure 5.34 Drain characteristics of an n-channel enhancement-type

MOSFET with VT  2 V and k  0.278 103 A/V2.

For the characteristics of Fig. 5.33 the level of VT is 2 V, as revealed by the fact
that the drain current has dropped to 0 mA. In general, therefore:
For values of VGS less than the threshold level, the drain current of an en-
hancement-type MOSFET is 0 mA.
Figure 5.34 clearly reveals that as the level of VGS increased from VT to 8 V, the
resulting saturation level for ID also increased from a level of 0 to 10 mA. In addi-
tion, it is quite noticeable that the spacing between the levels of VGS increased as the
magnitude of VGS increased, resulting in ever-increasing increments in drain current.
For levels of VGS  VT, the drain current is related to the applied gate-to-source
voltage by the following nonlinear relationship:
ID  k(VGS  VT)2 (5.13)

Again, it is the squared term that results in the nonlinear (curved) relationship be-
tween ID and VGS. The k term is a constant that is a function of the construction of
the device. The value of k can be determined from the following equation [derived
from Eq. (5.13)] where ID(on) and VGS(on) are the values for each at a particular point
on the characteristics of the device.

ID(on)
k  2 (5.14)
(VGS(on)  VT)
Substituting ID(on)  10 mA when VGS(on)  8 V from the characteristics of Fig.
5.34 yields
10 mA 10 mA 10 mA
k  2    
(8 V  2 V) (6 V)2 36 V2
 0.278  103 A/V2
and a general equation for ID for the characteristics of Fig. 5.34 results in:
ID  0.278 103(VGS  2 V)2

5.8 Enhancement-Type MOSFET 237

 Substituting VGS  4 V, we find that
ID  0.278 103(4 V  2 V)2  0.278 103(2)2
 0.278 103(4)  1.11 mA
as verified by Fig. 5.34. At VGS  VT , the squared term is 0 and ID  0 mA.
For the dc analysis of enhancement-type MOSFETs to appear in Chapter 6, the
transfer characteristics will again be the characteristics to be employed in the graph-
ical solution. In Fig. 5.35 the drain and transfer characteristics have been set side by
side to describe the transfer process from one to the other. Essentially, it proceeds as
introduced earlier for the JFET and depletion-type MOSFETs. In this case, however,
it must be remembered that the drain current is 0 mA for VGS VT. At this point a
measurable current will result for ID and will increase as defined by Eq. (5.13). Note
that in defining the points on the transfer characteristics from the drain characteris-
tics, only the saturation levels are employed, thereby limiting the region of operation
to levels of VDS greater than the saturation levels as defined by Eq. (5.12).

ID (mA) ID (mA)

10 10 VGS = +8 V

9 9
8 8
7 7 VGS = +7 V

6 6
5 5
VGS = +6 V
4 4
3 3
VGS = +5 V
2 2
1 1 VGS = +4 V
VGS = +3 V
0 1 2 3 4 5 6 7 8 VGS 0 5 10 15 20 25 VDS
VT
VGS = V T = 2 V

Figure 5.35 Sketching the transfer characteristics for an n-channel enhancement-

type MOSFET from the drain characteristics.

The transfer curve of Fig. 5.35 is certainly quite different from those obtained ear-
lier. For an n-channel (induced) device, it is now totally in the positive VGS region
and does not rise until VGS  VT. The question now surfaces as to how to plot the
transfer characteristics given the levels of k and VT as included below for a particu-
lar MOSFET:
ID  0.5 103(VGS  4 V)2
First, a horizontal line is drawn at ID  0 mA from VGS  0 V to VGS  4 V as
shown in Fig. 5.36a. Next, a level of VGS greater than VT such as 5 V is chosen and
substituted into Eq. (5.13) to determine the resulting level of ID as follows:
ID  0.5 103(VGS  4 V)2
 0.5 103(5 V  4 V)2  0.5 103(1)2
 0.5 mA

238 Chapter 5 Field-Effect Transistors

Figure 5.36 Plotting the transfer characteristics of an n-channel enhancement-
type MOSFET with k  0.5 103 A/V2 and VT  4 V.

and a point on the plot is obtained as shown in Fig. 5.36b. Finally, additional levels
of VGS are chosen and the resulting levels of ID obtained. In particular, at VGS  6,
7, and 8 V, the level of ID is 2, 4.5, and 8 mA, respectively, as shown on the result-
ing plot of Fig. 5.36c.

p-Channel Enhancement-Type MOSFETs

The construction of a p-channel enhancement-type MOSFET is exactly the reverse of
that appearing in Fig. 5.31, as shown in Fig. 5.37a. That is, there is now an n-type
substrate and p-doped regions under the drain and source connections. The terminals
remain as identified, but all the voltage polarities and the current directions are re-
versed. The drain characteristics will appear as shown in Fig. 5.37c, with increasing
levels of current resulting from increasingly negative values of VGS. The transfer char-
acteristics will be the mirror image (about the ID axis) of the transfer curve of Fig.
5.35, with ID increasing with increasingly negative values of VGS beyond VT, as shown
in Fig. 5.37b. Equations (5.11) through (5.14) are equally applicable to p-channel de-
vices.

5.8 Enhancement-Type MOSFET 239

 ID (mA) ID (mA)

8 8 VGS = –6 V

D 7 7
ID 6 6

p 5 5
VGS = –5 V
4 4

G n SS 3 3
– VGS = –4 V
2 2
p 1 1 VGS = –3 V

+ –6 –5 –4 –3 –2 –1 0 VGS 0 VDS
D VGS = VT = –2 V
VT

(a) (b) (c)

Figure 5.37 p-Channel enhancement-type MOSFET with VT  2 V and k  0.5 103 A/V2.

Symbols, Specification Sheets, and Case

Construction
The graphic symbols for the n- and p-channel enhancement-type MOSFETs are pro-
vided as Fig. 5.38. Again note how the symbols try to reflect the actual construction
of the device. The dashed line between drain and source was chosen to reflect the fact
that a channel does not exist between the two under no-bias conditions. It is, in fact,
the only difference between the symbols for the depletion-type and enhancement-type
MOSFETs.

Figure 5.38 Symbols for (a)

n-channel enhancement-type
MOSFETs and (b) p-channel
enhancement-type MOSFETs.

The specification sheet for a Motorola n-channel enhancement-type MOSFET is

provided as Fig. 5.39. The case construction and terminal identification are provided
next to the maximum ratings, which now include a maximum drain current of 30 mA
dc. The specification sheet provides the level of IDSS under “off” conditions, which is
now simply 10 nA dc (at VDS  10 V and VGS  0 V) compared to the milliampere
range for the JFET and depletion-type MOSFET. The threshold voltage is specified

240 Chapter 5 Field-Effect Transistors