Pdp

Contemporaneously it is observed the rise of new project practices that utilize the possibilities of the internet in the communication process between the various stakeholders. One of these approaches is Crowd-design, emerging mode of design and production system that uses the knowledge and resources available in the crowd, usually via the internet, in order to solve problems and/or create content. This dissertation aims to propose steps and procedures for the adaptation of Crowd- design to the NPD process inside Brazilian companies. The theoretical basis was based on a review of the literature on Crowd-design and product development via crowdsourcing and was able to raise definitions, principles, actors, competitive implications, implications for sustainability, and the role of the designer in this process. Based on the unified model of product development proposed by Rozenfeld et al. (2006) and what the crowdsourcing literature addressed at each stage of the NPD, a proposal for a new product development model via Crowd-design was elaborated. The research method involved a study of multiple cases with one in ex- post-facto format and the other as participant observation, both developed at the Design and Sustainability Laboratory of the Federal University of Paraná (NDS/ UFPR). The two cases have applied Crowd-design as a complementary process in the development of new products using the crowd, the first being in partnership with a micro-enterprise and open to anyone solve and second only to the internal employees of a large company. The case study was given in the form of project documents (reports, minutes, audio/visual) and through interviews with the researchers who took part in the project teams. The external validation was done through pattern matching comparing both cases with the theoretical model. At the end of the process, it was concluded that the proposed Crowd-design model was adapted based on Rozenfeld et al. (2006) in the PDP of the companies, as well as the implications of this process for the sustainability and skills of the designer throughout the process.

Generally, Nigerian political parties in the present republic have been hampered by crisis of internal democracy thus undermining their political leadership recruitment function. Also, this has negative implications for party discipline and unity. The resultant effects are party factionalization, defection and carpet-crossing. The Peoples Democratic Party (PDP) is a good example of one of these Nigerian political parties that lacks internal democracy. In fact, PDP was a leviathan. The 2015 Election symbolized a contest between David and Goliath. The electoral outcome is that PDP has transformed from a ruling party to an opposition party. The study, by relying on the theory of relative autonomy of the state and secondary sources, concludes that the PDP authoritarianism deepened crisis of internal democracy in Nigeria and that this authoritarian character of the former ruling PDP was a reflection of the authoritarian character of the Nigerian state which is currently shaping the ruling APC. The implication being that this lack of internal party democracy in Nigerian political parties generally undermines the credibility of the entire electoral process thereby rendering the entire process undemocratic. The study is essentially qualitative, historical and inductive.

Mungkin peristiwa ‘virus korona’ ini mengambarkan ‘Teori Angsa Hitam ‘(peristiwa terjadi diluar dugaan dan menimbulkan kegemparan) namun kita harus lebih positif dan menganggapnya sebagai pemangkin untuk pendidikan diatas talian dan alat berteknologi  lain hasil daripada  penganjuran dan nasihat korporat yang bersungguh-sungguh sekian lamanya.

In this paper an ultra-low power NAND based multiplexer and flip flop is proposed. The modified design is compared to conventional 4*1 multiplexer and shows dynamic and static power reduction up to 32.077% and 45.055% respectively while for JK flip flop, dynamic and static power reduction up to 84.25% and 92.47%respectively. Simulations have been done on 270C temperature and 50MHz frequency. With every selection line input dynamic power consumption is calculated, static power consumption, delay and power delay product. The simulations have been carried out on Tanner EDA.

Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.

This paper uses Stanford model for MOS-like CNTFET in order to find optimum values of its parameters. The purpose is to test well-designed NAND and D-Latch ICs based on this optimized CNTFET at VDD = 0.9 V in 32-nm technology by HSPICE, in order to observed PDP-based error (power–delay product-based error). This error causes a growth in power consumption of logic gates and circuits. Importance of using “trade-off factor” instead of “PDP factor” in some specific cases is clearly illustrated in this paper. The optimum values of MOS-like CNTFET parameters which are obtained in by Stanford model this paper, are the same as the optimum ones in previous works. This research displays a useful insight about MOS-like CNTFET and PDP-based error and presents trade-off factor to making well-designed gates and circuits.

{{{{{ Keywords: MOS-like CNTFET, Stanford model, HSPICE, NAND, D-Latch, Power–Delay Product (PDP), Trade-Off, Nanoscience, Nanotechnology, SN Applied Sciences, Springer, Salimeh Shahrabadi }}}}}

See:
https://doi.org/10.1007/s42452-019

High computer performance depends only partially on using fmter and more reliable hardware, but to a large extent it depends on the architecture and on the processing techniques. An effective platform that matches general planning strategies is given by the ...

PDP is a technique designed for CSP to show that complete file of the client is in secured state without downloading the whole file. PDP scheme of multi cloud includes multiple csp’s to mutually store and maintain the client’s data. Later CPDP was proposed which also has the Homorphic verifiable response and Hash index hierarchy properties, but there is a security flaws. The problem is, when a malicious csp or organizer generates a valid response which also clears the verification process in case of deletion of the stored data. This means, simply, an attacker gets the information without storing the client’s data. In this paper, we discuss about the security flaws in CPDP (Cooperative Provable Data Possession) scheme.

... Mariam Kamkar, Patrik Krajina, Peter Fritzson ... In the following set of statements, s2 is communication dependent on its communicating partner ~1; the statement s 2 is receiving a message in bx from the process with ProcId 1, sent by statement sl through the message denoted ...

Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.

This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesser energy required. The circuit is designed using total number of 9 transistors. The proposed circuit performance better in terms of power, delay, power delay product which is very easily shown by the simulation results. There is comparison of performance among proposed circuit with other pre-exist circuits in various literatures and this comparison shows higher reduction in Power-Delay-Product (pJ) of our proposed design. It has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM standard models are used for simulations. The proposed design gives faster response for the carry output and can be used to reduce more at higher temperature.

The growth of Foundation Degree qualifications in the UK (HEFCE, 2007) has lead to a more active view of employer engagement with Higher Education. Many full time Foundation Degree students are now taking up work placements with employers as part of their study. As a result, a three-way conversation between learners, employers and tutors needs to take place on an ongoing basis throughout placements. An online environment utilising blogs, e-portfolio and online work-based contracts can facilitate this ‘conversation’. Employers can be further supported through provision of online materials to support the process of mentor training. This paper reports on an HE Academy, ICS funded mini-project to create such an environment at Hull College for students on the Foundation Degree course in Software Design and Development. The project is still underway, and is in the middle of its year-long span. The environment has been chosen, developed and tested. The next phase will be to use the system ...

A FPGA Implementation of a bilateral filter for image processing is given which does spatial
averaging without smoothing edges. Kernel based processing is possible, which means that processing of the
entire filter window at one pixel clock cycle. It is also supported by the arrangement of the input data into
groups and applied a single clock cycle for a group of pixels. Based on these features, a technique called
Spurious Power Suppression Technique (SPST) is implemented in Bilateral Filter to minimize Power Delay
Product (PDP). SPST can also dramatically reduce the power by turn off its MSP (Most significant bit) without
compromising the computational results to achieve the target parameters. Furthermore, an Original Glitch
Diminishing technique is proposed to filter out useless switching power by asserting signals after the data
transient period. The SPST can be expanded to a Fine-grain scheme in which the combinational circuits are
divided into more than two parts. In Bilateral Filter a kernel of different size can be implemented using SPST
which achieve good performance.