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WO2023206986A1 - 碳化硅半导体器件及其制作方法 - Google Patents

碳化硅半导体器件及其制作方法 Download PDF

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Publication number
WO2023206986A1
WO2023206986A1 PCT/CN2022/125790 CN2022125790W WO2023206986A1 WO 2023206986 A1 WO2023206986 A1 WO 2023206986A1 CN 2022125790 W CN2022125790 W CN 2022125790W WO 2023206986 A1 WO2023206986 A1 WO 2023206986A1
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Prior art keywords
trench
level
silicon carbide
double
region
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PCT/CN2022/125790
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English (en)
French (fr)
Inventor
袁俊
Original Assignee
湖北九峰山实验室
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Priority claimed from CN202220975064.3U external-priority patent/CN217468441U/zh
Priority claimed from CN202210433930.0A external-priority patent/CN114678425A/zh
Application filed by 湖北九峰山实验室 filed Critical 湖北九峰山实验室
Priority to EP22939806.0A priority Critical patent/EP4456144A1/en
Priority to US18/839,675 priority patent/US20250169126A1/en
Priority to JP2024548417A priority patent/JP2025505292A/ja
Publication of WO2023206986A1 publication Critical patent/WO2023206986A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions

Definitions

  • the present application relates to the technical field of semiconductor devices, and more specifically, to a silicon carbide (SiC) semiconductor device and a manufacturing method thereof.
  • SiC silicon carbide
  • the main structure of electronic equipment to achieve various functions is integrated circuits, and semiconductor devices are important electronic components of integrated circuits.
  • Silicon carbide semiconductor devices have become a major development direction in the semiconductor field due to their excellent characteristics in high-power applications.
  • silicon carbide semiconductor devices are prone to breakdown problems in areas where the electric field is concentrated due to the existence of higher electric fields.
  • this application provides a silicon carbide semiconductor device and a manufacturing method thereof.
  • the scheme is as follows:
  • a silicon carbide semiconductor device, the silicon carbide semiconductor device includes:
  • a silicon carbide epitaxial layer having opposite first and second surfaces, the first surface including a gate region and source regions located on both sides of the gate region;
  • a first voltage-resistant shielding structure formed in the silicon carbide epitaxial layer based on the first trench
  • the gate structure has a metal gate on its surface
  • the source region has a metal source on its surface
  • a well region is provided in the first surface, and the well region is located between the first trench and the second voltage-withstanding shielding structure.
  • the first voltage-withstanding shielding structure in the depth direction of the first trench, is located on a side of the well region facing the second surface and is connected to the well region. Zone no contact.
  • the first trench is a first double-step trench
  • the gate structure includes polysilicon filling the first trench, and there is a first insulating dielectric layer between the first trench and the filled polysilicon;
  • the first voltage-withstanding shielding structure includes a doped region located in the sidewalls and the bottom surface of the first-level trench of the first double-level step trench facing the second surface.
  • the depth of the well region relative to the first surface is less than the depth of the step between two levels of the first two-level step trench, and the first withstand voltage
  • the shielding structure is located on a side of the first double-stepped trench where the step between the two-stepped trenches faces the second surface.
  • the first trench is a first double-step trench; the first double-step trench is filled with polysilicon, and the first double-step trench is connected to the first double-step trench.
  • the thickness of the insulating dielectric layer at the bottom of the first two-stage stepped trench is greater than the thickness of the insulating dielectric layer on the side walls of each stage of the first two-stage stepped trench, and is greater than that of the adjacent two stages.
  • the silicon carbide semiconductor device there is a multi-level step trench in the surface of the source region; the multi-level step trench is filled with polysilicon, and the relationship between the multi-level step trench and the filled polysilicon is There is a second insulating dielectric layer between;
  • the second voltage-withstanding shielding structure includes a doped region formed in the silicon carbide epitaxial layer based on the multi-level step trench.
  • the first trench is a first two-level step trench; the multi-level step trench is a second two-level step trench, and the first two-level step trench is The depth is the same as the second double step trench.
  • the first trench is a first double-step trench
  • the multi-level step trench is a three-level step trench, and the depth of the three-level step trench is greater than the depth of the first two-level step trench.
  • the second voltage-resistant shielding structure includes a doping region located in the silicon carbide epitaxial layer around sidewalls, steps, bottoms and openings of the multi-level step trench.
  • the thickness of the second insulating dielectric layer at the bottom of the multi-level stepped trench is greater than the thickness of the second insulating layer on the side walls of each level of the multi-level stepped trench.
  • the thickness of the dielectric layer is greater than the thickness of the second insulating dielectric layer on the step between two adjacent trenches.
  • the second voltage-withstanding shielding structure is an ion implantation region formed in the source region.
  • the implantation depth of the ion implantation region is not less than the depth of the first trench.
  • This application also provides a method for manufacturing the silicon carbide semiconductor device described in any one of the above, the manufacturing method includes:
  • An epitaxial wafer includes a silicon carbide epitaxial layer, the silicon carbide epitaxial layer has an opposite first surface and a second surface, the first surface includes a gate region and is located on both sides of the gate region The source region;
  • a first voltage-withstanding shielding structure is formed in the silicon carbide epitaxial layer
  • the first trench is a first double-step trench
  • a multi-level step trench is formed in the surface of the source region
  • the method of preparing the first voltage-resistant shielding structure and the second voltage-resistant shielding structure includes:
  • the first double-level step trench is close to the first-level trench sidewall of the dielectric layer on the second surface. Ions are implanted into the sidewalls and bottom of the first-level trench to form the first voltage-withstanding shielding structure in the silicon carbide epitaxial layer at the sidewalls and bottom of the first-level trench near the second surface of the first double-step trench;
  • ions are implanted at the bottom of the multi-level stepped trench, the steps of the trenches at each level, and the side walls.
  • the second voltage-withstanding shielding structure is formed in the silicon carbide epitaxial layer of the sidewall.
  • the first trench is a first two-level step trench; a multi-level step trench is formed in the surface of the source region; the first two-level step trench and the The multi-level step trenches are filled with polysilicon; the gate structure includes polysilicon filled in the first double-level step trench;
  • the gate structure includes the first two-level step polysilicon filled in the trench;
  • the metal gate is located on the surface of the polysilicon filled in the first double-level step trench; and the metal source is located on the surface of the polysilicon filled in the multi-level step trench.
  • the thickness of the insulating dielectric layer at the bottom of the first double-step stepped trench is greater than the thickness of the insulating dielectric layer on the side walls of each level of the first double-step stepped trench.
  • the thickness is greater than the thickness of the insulating dielectric layer on the step between two adjacent trenches;
  • the thickness of the insulating dielectric layer at the bottom of the multi-level stepped trench is greater than the thickness of the insulating dielectric layer on the side walls of each level of the multi-level stepped trench, and is greater than the thickness between two adjacent levels of trenches.
  • the thickness of the insulating dielectric layer on the step is greater than the thickness of the insulating dielectric layer on the side walls of each level of the multi-level stepped trench, and is greater than the thickness between two adjacent levels of trenches.
  • the multi-level stepped trench is a second double-level stepped trench, and the second double-level stepped trench has the same depth as the first double-level stepped trench; or, the second double-level stepped trench has the same depth as the first double-level stepped trench.
  • the multi-level step trench is a three-level step trench, and the depth of the three-level step trench is greater than the depth of the first two-level step trench.
  • the method of forming the second voltage-resistant shielding structure includes:
  • an ion implantation region is formed in the source region as the second withstand voltage shielding structure
  • the implantation depth of the ion implantation region is not less than the depth of the first trench.
  • the silicon carbide semiconductor device includes: a silicon carbide epitaxial layer, and the silicon carbide epitaxial layer has opposite first and second surfaces.
  • the first surface includes a gate region and source regions located on both sides of the gate region; there is a first trench in the surface of the gate region; based on the first trench formed on the carbonization a first voltage-resistant shielding structure in the silicon epitaxial layer; a gate structure located in the first trench; a metal gate on the surface of the gate structure; and a second voltage-resistant shielding structure on the surface of the source region.
  • the silicon carbide semiconductor device has a first voltage-resistant shielding structure formed in the silicon carbide epitaxial layer based on the first trench, and a second voltage-resistant shielding structure formed in the surface of the source region, which improves the first voltage-resistant shielding structure.
  • the voltage resistance performance of the corner area at the bottom of the trench solves the problem of breakdown that is prone to occur in areas where the electric field is concentrated.
  • Figure 1 is a schematic structural diagram of a DMOSFET
  • Figure 2 is a schematic structural diagram of a UMOSFET
  • Figure 3 is a schematic structural diagram of a silicon carbide semiconductor device provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of another silicon carbide semiconductor device provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of another silicon carbide semiconductor device provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of another silicon carbide semiconductor device provided by an embodiment of the present application.
  • FIGS. 7-29 are schematic flow charts of a method for manufacturing a silicon carbide semiconductor device provided by embodiments of the present application.
  • SiC vertical power MOSFET devices mainly include lateral double-diffusion DMOSFET and vertical gate trench structure UMOSFET.
  • Figure 1 is a schematic structural diagram of a DMOSFET, including: an n+ (n-type heavily doped) substrate 2; an n- (n-type lightly doped) drift region 3 provided on the surface of the substrate 2 ; The p-type well region 4 located in the drift region 3; and the source region 5 located within the p-type well region.
  • the source region 5 includes an n+ doped region 51 and a p+ (p-type heavily doped) doped region 52.
  • a gate dielectric layer 7 is provided on the surface of the drift region 3
  • a gate electrode 8 is provided on the surface of the gate dielectric layer 7 .
  • the side surface of the substrate 2 facing away from the drift region 3 has a drain electrode 1 .
  • the DMOSFET structure adopts planar diffusion technology, using refractory materials such as polysilicon gates as masks, and uses the edges of the polysilicon gates to define the p base region and n+ source region.
  • refractory materials such as polysilicon gates as masks
  • the name DMOS comes from this double diffusion process.
  • the surface channel region is formed by utilizing the side diffusion difference between the p-type base region and the n+ source region.
  • Figure 2 is a schematic structural diagram of a UMOSFET.
  • the difference from the structure shown in Figure 1 is that a U-shaped groove is provided in the UMOSFET.
  • the surface of the U-shaped groove is covered with a gate dielectric layer 7, and the gate 8 is filled with in the U-shaped groove.
  • the vertical gate trench structure UMOSFET is named after the U-shaped trench structure.
  • the U-shaped trench structure is formed in the gate region using reactive ion etching.
  • the U-shaped trench structure has a high channel density (channel density is defined as the channel width of the active area), which significantly reduces the on-state characteristic resistance of the device.
  • SiC UMOSFET still has several problems in actual process manufacturing and application:
  • the thickness of the silicon dioxide layer at the bottom of the trench is often thin during the high-temperature furnace tube oxidation process of a single rectangular or U-shaped gate trench, which reduces the voltage withstand capability of the trench bottom and the device. reliability.
  • the technical solution of the present application provides a silicon carbide semiconductor device with a first voltage-withstanding shielding structure formed in the silicon carbide epitaxial layer based on the first trench, and in the surface of the source region A second withstand voltage shielding structure is formed, which improves the withstand voltage performance of the corner area at the bottom of the first trench, solves the problem of breakdown that is prone to occur in areas where electric fields are concentrated, and improves the device's ability to withstand static electricity in harsh environments and to withstand high voltages in the circuit. Spike tolerance.
  • the first voltage-withstanding shielding structure can be formed based on the first trench, which can increase the ion implantation depth when forming the first voltage-withstanding shielding structure, and facilitate the implementation of various trench gate protection structures and anti-surge designs in terms of technology.
  • a thicker insulating dielectric layer can be formed at the bottom of the trench, which solves the problem that the conventional high-temperature furnace tube oxidation process cannot form a thicker silicon dioxide layer in the trench, further improving the resistance of the trench bottom. pressure capability and device reliability.
  • Figure 3 is a schematic structural diagram of a silicon carbide semiconductor device provided by an embodiment of the present application.
  • the silicon carbide semiconductor device includes:
  • Silicon carbide epitaxial layer 11 the silicon carbide epitaxial layer 11 has opposite first surfaces and second surfaces, the first surface includes a gate region and source regions located on both sides of the gate region;
  • the first voltage-withstanding shielding structure 13 formed in the silicon carbide epitaxial layer 11 based on the first trench 12;
  • the gate structure g located in the first trench 12;
  • the gate structure has a metal gate G on its surface
  • the well region W is located between the first trench 12 and the second voltage-withstanding shielding structure 14 .
  • the silicon carbide semiconductor device has a first voltage-resistant shielding structure 13 formed in the silicon carbide epitaxial layer 11 based on the first trench 12, and a second voltage-resistant shielding structure 14 formed in the surface of the source region,
  • the voltage resistance performance of the corner area at the bottom of the first trench 12 is improved, the problem of breakdown that is prone to occur in areas where the electric field is concentrated is solved, and the device's ability to withstand static electricity in harsh environments and to withstand high-voltage spikes in the circuit is improved.
  • the first voltage-withstanding shielding structure 13 can be formed based on the first trench 12, which can increase the ion implantation depth when forming the first voltage-withstanding shielding structure 13, and facilitate the realization of a variety of trench gate protection structures and wave resistance in the process. Yong design.
  • a thicker insulating dielectric layer can be formed at the bottom of the trench, which solves the problem that the conventional high-temperature furnace tube oxidation process cannot form a thicker silicon dioxide layer in the trench, further improving the resistance of the trench bottom. pressure capability and device reliability.
  • the silicon carbide epitaxial layer 11 is prepared on the surface of the semiconductor substrate 10 , and the second surface faces the semiconductor substrate 10 .
  • a metal drain D is provided on the surface of the semiconductor substrate 10 away from the silicon carbide epitaxial layer 11 .
  • the metal source S and the metal drain D can be Ti or Al, etc., and the metal drain D can be one or a composite metal layer of Ni, Ti, Al or Ag.
  • the silicon carbide epitaxial layer 11 and the semiconductor substrate 10 have the same doping type
  • the well region W, the first voltage-withstanding shielding structure 13 and the second voltage-withstanding shielding structure 14 have the same doping type, and are opposite to the doping type of the epitaxial layer 11 .
  • P-type doping and N-type doping are opposite types of doping.
  • the silicon carbide epitaxial layer 11 close to the first surface of the well region W has an ion implantation region 17 with a doping type opposite to that of the well region W.
  • the ion implantation region 17 can be N+ ion implantation. area.
  • the semiconductor substrate 10 can be an N+ (N-type heavily doped) silicon carbide substrate; the epitaxial layer 11 is an N- (N-type lightly doped) silicon carbide epitaxial layer, serving as a drift region of the semiconductor device; the well region W is P Well area.
  • the first voltage-withstanding shielding structure 13 and the second voltage-withstanding shielding structure 14 include P+ (P-type heavily doped) ion implantation regions. It should be noted that in the embodiments of the present application, the doping types of each region of the device are not limited to those described in the embodiments. The doping types can be set based on requirements to form a PMOS or NMOS structure.
  • the first voltage-withstanding shielding structure 13 is located on the side of the well region W facing the second surface, and has no contact with the well region W. That is to say In the vertical direction of FIG. 3 , the first voltage-withstanding shielding structure 13 is located below the well region W and has no contact with the well region W.
  • the first trench 12 is a first double-step trench;
  • the gate structure g includes polysilicon filling the first trench 12 , and the first trench 12 and
  • the first voltage-withstanding shielding structure 13 includes a sidewall surface of a first-level trench located in the first double-level step trench facing the second surface. and doped regions within the bottom surface.
  • the first insulating dielectric layer 151 is a gate oxide layer, which may be silicon dioxide.
  • the first two-level stepped trench has two-level trenches and a step structure located between the two-level trenches.
  • One level of the first two-level stepped trench is close to the first surface and the other level is close to the second surface.
  • the opening of the primary trench close to the first surface is larger than the opening of the primary trench close to the second surface.
  • ion implantation is performed into the first double-level step trench to form the first voltage-resistant shielding structure 13, thereby avoiding ion implantation
  • ions are implanted into the first-level trench sidewall of the first double-level step trench close to the first surface, so that the first voltage-withstanding shielding structure 13 is located below the well region W to avoid contact between the two, thereby avoiding
  • the resulting abnormal channel opening problem of semiconductor devices ensures the normal operation of the device.
  • the first insulating dielectric layer 151 extends to the outside of the first trench 12 and covers the first surface.
  • the first insulating dielectric layer 151 has an opening on the first surface for disposing the metal ohmic contact layer 18 .
  • the source metal S is connected to the silicon carbide epitaxial layer 11 at the opening through the metal ohmic contact layer 18 .
  • the depth of the well region W relative to the first surface is less than the depth of the step between the two-level trenches in the first double-level step trench, and the first voltage-withstanding shielding structure 13 is located on the first double-level step trench.
  • the step between two stepped grooves faces the side of the second surface.
  • the multi-level stepped trench 16 in the surface of the source region; the multi-level stepped trench 16 is filled with polysilicon, and the multi-level stepped trench 16 is in contact with the filled polysilicon.
  • the second insulating dielectric layer 152 in between; the second withstand voltage shielding structure 14 includes a doped region formed in the silicon carbide epitaxial layer 11 based on the multi-level step trench.
  • the first insulating dielectric layer 151 on the surface of the first trench 12 and the second insulating dielectric layer 152 on the surface of the multi-step trench 16 are made of the same material and are formed at the same time.
  • the polysilicon filled in the first trench 12 and the polysilicon filled in the multi-level stepped trench 16 are formed simultaneously.
  • the second voltage-withstanding shielding structure 14 includes a doped region in the silicon carbide epitaxial layer 11 located around the sidewalls, steps, bottoms and openings of the multi-level step trench 16. That is to say, the multi-level steps
  • the second voltage-withstanding shielding structure 14 is disposed in the sidewalls, steps, and bottom of the trench 16 and in the silicon carbide epitaxial layer around the opening.
  • the first trench 12 is a first double-step trench; the multi-step trench 16 is a second double-step trench.
  • the first double-step trench The depth of the second double step trench is the same, and both can be prepared in the same process flow.
  • the multi-level step trench 16 is not limited to a double-level step trench, but may also be a step trench with more than 2 levels.
  • the number of trench steps of the multi-step trench 16 can be set based on device thickness parameters and ion implantation depth requirements.
  • the silicon carbide semiconductor device may be a silicon carbide MOSFET device.
  • a trench gate is formed in the gate region based on the first trench 12
  • a trench source is formed in the source regions on both sides of the gate region based on the multi-step trench 16 .
  • Both the first trench 12 and the multi-level stepped trench 16 may be double-level stepped trenches.
  • a silicon carbide MOSFET device with a double-level stepped trench structure is formed.
  • Figure 4 is a schematic structural diagram of another silicon carbide semiconductor device provided by an embodiment of the present application.
  • the first trench 12 is a first Double-level step trench
  • the multi-level step trench 16 is a three-level step trench, and the depth of the three-level step trench is greater than the depth of the first two-level step trench.
  • FIG. 5 is a schematic structural diagram of another silicon carbide semiconductor device provided by an embodiment of the present application.
  • the first trench 12 is a first two-level step trench. groove; the first double-level step trench is filled with polysilicon, the gate structure g includes polysilicon filling the first double-level step trench, the first double-level step trench and the filled polysilicon
  • the thickness of the first insulating dielectric layer 151 at the bottom of the first double-step trench is greater than that of the first double-step trench.
  • the thickness of the first insulating dielectric layer 151 on the sidewalls of the trenches at each level is greater than the thickness of the first insulating dielectric layer 151 on the steps between the adjacent two levels of trenches.
  • the thickness of the second insulating dielectric layer 152 at the bottom 16 of the multi-level stepped trench is greater than the thickness of the second insulating dielectric layer 152 on the sidewalls of each level of the multi-level stepped trench 16 .
  • the thickness of the insulating dielectric layer 152 is greater than the thickness of the second insulating dielectric layer 152 on the step between two adjacent trenches.
  • the second insulating dielectric layer 152 and the first insulating dielectric layer 151 are the same insulating dielectric layer 15 .
  • the thickness of the first insulating dielectric layer 151 and the second insulating dielectric layer 152 at the bottom of the trench can be greater than the thickness of other areas of the trench.
  • the silicon carbide semiconductor device described in the embodiment of the present application can form a trench gate based on the first trench 12 in the gate region, and form a trench source based on the multi-step trenches 16 in the source region on both sides of the gate region. , and form a first voltage-resistant shielding structure 13 at the bottom of the first trench 12 through ion implantation, passing through the bottom and side walls of the multi-level stepped trench 16 and the silicon carbide epitaxial layer 11 of the steps between the two-level trenches. Ion implantation forms the second voltage-resistant shielding structure 14 .
  • both the first voltage-withstanding shielding structure 13 and the second voltage-withstanding shielding structure 14 may be P+ (P-type heavily doped) regions.
  • the first voltage-withstanding shielding structure 13 and the second voltage-withstanding shielding structure 14 are formed by ion implantation in the silicon carbide epitaxial layer 11 respectively, thereby solving the problem of carbonization. It is difficult to form a deep P+ masking layer in silicon material and the damage problem of high-dose and high-energy P+ ion implantation improves the reliability of the device and can better shield and protect the gate trench.
  • a silicon dioxide layer is grown on the surface of the first trench 12 and the multi-level step trench 16 as the first insulating dielectric layer 151 and the second insulating layer 151.
  • the dielectric layer 152 is then filled with polysilicon in the first trench 12 and the multi-level step trench 16, and then a metal electrode is formed to complete a silicon carbide MOSFET device with a double-level step trench structure.
  • the second voltage-withstanding shielding structure 14 is an ion implantation region formed in the source region.
  • the implantation depth of the ion implantation region is not less than the depth of the first trench 12 .
  • another embodiment of the present application also provides a method for manufacturing a silicon carbide semiconductor device, which is used to manufacture the silicon carbide semiconductor device described in the above embodiment.
  • the manufacturing method can be as shown in Figures 7 to 29 Show.
  • Figures 7 to 29 are schematic flow diagrams of a method for manufacturing a silicon carbide semiconductor device provided by an embodiment of the present application.
  • the manufacturing method includes:
  • Step S11 As shown in FIG. 7, an epitaxial wafer is provided.
  • the epitaxial wafer includes a silicon carbide epitaxial layer 11.
  • the silicon carbide epitaxial layer 11 has an opposite first surface and a second surface.
  • the first surface includes a gate. electrode region and source regions located on both sides of the gate region.
  • the silicon carbide semiconductor device may be prepared using an N+ silicon carbide semiconductor substrate 10 having an N-silicon carbide epitaxial layer 11 . Wherein, the second surface of the silicon carbide epitaxial layer 11 faces the semiconductor substrate 10 .
  • Step S12 As shown in Figures 8 to 16, form a first trench 12 in the gate region.
  • the well region W, the ion implantation region 17 and the electric field buffer region 19 are formed in the silicon carbide epitaxial layer 11 by performing ion implantation on the first surface.
  • the ion implantation region 17 and the electric field buffer region 19 are located within the surface of the source region and within the well region W.
  • the manufacturing method is described by taking the source region having multi-level step trenches 16 as an example.
  • the subsequent process forms the second voltage-withstanding shielding structure 14 based on the multi-level step trenches 16 .
  • the electric field buffer 19 can solve the leakage and breakdown problems caused by the thin thickness of the second voltage-withstanding shielding structure 14 at the opening position of the multi-level stepped trench 16, thereby enhancing the manufacturability and reliability of the device.
  • the doping type of the electric field buffer region 19 and the second withstand voltage shielding structure 14 is the same, for example, both can be N+ doped.
  • the doping types of the ion implantation region 17 and the second withstand voltage shielding structure 14 are opposite, and the ion implantation region 17 may be an N+ doped region.
  • the second double-step trench can be formed while forming the first double-step trench.
  • the specific process of forming the first double-step trench and the second double-step trench is as follows:
  • Step S121 As shown in FIG. 8 , a well region W, an ion implantation region 17 and an electric field buffer region 19 located in the well region are formed on the first surface through ion implantation.
  • ion implantation is generally carried out through high-temperature ion implantation equipment at 500-600°C to reduce damage to the crystal lattice of the silicon carbide material.
  • Step S122 As shown in Figure 12, perform first-level trench etching on the first surface.
  • a plasma dry etching process such as RIE or ICP etching process, can be used to etch to form the first-level trench.
  • the etching principle of silicon carbide materials is shown in Figures 9-11.
  • SiO 2 is deposited on the silicon carbide material as a mask layer through a deposition process such as CVD, and the photoresist PR is spin-coated on the surface of the mask layer.
  • the photoresist PR with the required pattern is formed through exposure and development, and then as shown in the figure As shown in Figure 10, based on the patterned photoresist PR, the mask layer is etched to form a patterned mask layer.
  • the silicon carbide material is etched. Grooves form on its surface. Common semiconductor processes such as photolithography and etching will not be described in detail in subsequent processes.
  • a layer of SiO 2 can be deposited by CVD as the mask layer 21, using gases containing F groups such as CF 4 and SF 6 , or gases containing Cl groups such as chlorine.
  • Gas, and a mixed gas of Ar and oxygen use plasma etching equipment ICP or RIE to etch the silicon carbide epitaxial layer 11 in the gate region and the source regions on both sides, so that in the gate region and The source regions respectively form first-level trenches.
  • the depth of the first-level trench is 10nm-3 ⁇ m. Further, the depth of the first-level trench can be set to 800nm-1um, so that the device has better performance.
  • Step S123 As shown in Figure 13, fill the first-level trench with SiO2 dielectric layer 22.
  • the SiO 2 dielectric layer 22 may be deposited using a CVD process.
  • the SiO 2 dielectric layer 22 fills the first level trench and covers the mask layer 21 .
  • Step S124 As shown in Figure 14, the mask 23 of the second-level trench is aligned.
  • a photoresist is spin-coated on the surface of the SiO 2 dielectric layer 22 , and the photoresist is exposed and developed based on the mask 23 to pattern the photoresist.
  • the photoresist is not shown in FIG. 14 .
  • the mask 23 has a first hollow region and a second hollow region, the first hollow region is used to form a second-level trench of the trench gate in the gate region, and the second hollow region is used to form a second-level trench in the source region.
  • the opening of the first hollow region is smaller than the opening of the first-level trench in the gate region, and the opening of the second hollow region is larger than the opening of the first-level trench in the source region.
  • Step S125 As shown in Figure 15, etching is performed based on the photoresist on the surface of the SiO2 dielectric layer 22, and second-level trenches are formed based on the first-level trenches in the gate region and the source region.
  • F-based gases such as CF 4 and SF 6 , or Cl-based gases such as chlorine, and a mixed gas of Ar and oxygen, through plasma etching equipment ICP or RIE, in the gate area and on both sides.
  • the silicon carbide epitaxial layer 11 is etched to form second-level trenches in the gate region and the source region respectively.
  • the etching depth of the second-level trench is 100nm-3um; further, the etching depth of the second-level trench can be set to 300-500nm, so that the device has better performance.
  • a second-level trench with a greater depth can be etched at the bottom of the first-level trench in the gate region, thereby forming a second-level trench.
  • a double step trench Based on this method, while forming the first double-level step trench in the gate region, it is also possible to form the first double-level step trench close to the first-level trench on the first surface.
  • the SiO 2 dielectric layer 22 is retained on the sidewall as a sacrificial layer to avoid scattering of ions on the first-level trench sidewall of the first double-level step trench close to the first surface when the first voltage-withstanding shielding structure 13 is formed in the subsequent process. problem, solve the abnormal channel opening problem caused by this, ensure the normal operation of the device, and improve the reliability of the device.
  • the opening of the second hollow region is larger than the opening of the first-level trench in the source region, when etching downward, the size of the upper part of the first-level trench increases and the depth of the lower part increases, thereby forming a second-level trench.
  • Double step trench Based on this method, the SiO 2 dielectric layer 22 on the sidewalls, steps and bottom surface of the second double-level step trench can be removed.
  • ions are implanted to facilitate the formation of the second double-level step trench in the source region. Ions are implanted into the sidewalls, steps and bottom of the silicon carbide epitaxial layer 11 of the two-step trench to form a second voltage-withstanding shielding structure 14 .
  • Figure 16 is an SEM image of a double step trench formed in the source region and the gate region based on the manufacturing method described in the embodiment of the present application. Based on the SEM image, it can be seen that using the method described in the embodiment of the present application The manufacturing method can form double-step trenches with good morphology in the gate region and the source region respectively.
  • Step S13 As shown in FIGS. 17 to 20 , based on the first trench, form a first voltage-withstanding shielding structure 13 in the silicon carbide epitaxial layer.
  • second voltage-withstanding shielding structure 14 in the surface of the source region; there is a well region W in the first surface, and the well region W is located between the first trench 12 and the second voltage-withstanding shielding structure. between 14.
  • the first trench 12 is a first two-level stepped trench; a multi-level stepped trench 16 is formed in the surface of the source region; the first voltage-resistant shielding structure 13 and the second voltage-resistant shielding structure 13 are prepared.
  • the method of masking the structure 14 includes: based on the first double-level step trench and the dielectric layer 22 of the first double-level step trench close to the sidewall of the first-level trench on the first surface, Ion implantation is performed on the sidewalls and bottom of the first-level trench close to the second surface, and the silicon carbide epitaxial layer is formed in the sidewalls and bottom of the first-level trench of the first double-step trench close to the second surface.
  • the first voltage-resistant shielding structure 13 based on the multi-level step trench 16, ions are implanted at the bottom of the multi-level step trench 16, the steps and side walls of each level trench, and in the multi-level step trench 16
  • the second voltage-withstanding shielding structure 14 is formed in the silicon carbide epitaxial layer at the bottom of the trench, the steps of the trench at each level, and the sidewalls.
  • the multi-level step trench 16 can be set as a second double-level step trench, and the second double-level step trench has the same depth as the first double-level step trench; in other ways, all the steps can be set.
  • the multi-step trench 16 is a three-step trench, and the depth of the three-step trench is greater than the depth of the first two-step trench.
  • step S13 first, as shown in FIG. 17 , ion implantation is performed based on the patterned mask layer 21 and dielectric layer 22 to form the first voltage-resistant shielding structure 13 and the second voltage-resistant shielding structure 14 .
  • High-temperature ion implantation equipment can be used to perform P+ ion implantation on the sidewalls and bottom of the trench at 500-600°C to form the first voltage-resistant shielding structure 13 and the second voltage-resistant shielding structure 14, and then remove them as shown in Figure 18
  • the buffered HF wet method can be used to remove the silicon dioxide mask, thereby removing the mask layer 21 and the dielectric layer 22.
  • the typical implanted ions are Al ions; the ion implantation energy can be from a few hundred KeV to several MeV, the dose is 1E12cm -2 -1E16cm -2 ; the implantation depth is a few hundred nm to a few microns .
  • the first double-level step trench serves as the well region W of the channel region and will not be affected by P+ ion implantation.
  • Figure 19 is an SEM image after forming the first voltage-resistant shielding structure 13 and the second voltage-resistant shielding structure 14 using the manufacturing method of the embodiment of the present application. Based on Figure 19, it can be seen that after the P+ ion implantation is completed, as a trench The well region W in the channel region will not be affected by P+ ion implantation, which improves the reliability and stability of the device.
  • Figure 20 is an SEM image of the source region before and after P+ ion implantation using the manufacturing method of the embodiment of the present application.
  • the picture on the left is an SEM image of the area corresponding to the second double-step trench before P+ ion implantation.
  • the picture on the right is an SEM image of the area corresponding to the second double-step trench after P+ ion implantation.
  • the smaller gray area in the picture on the right is an SEM slice image formed after Al ion implantation.
  • the trench gate adopts a first two-level step trench.
  • the first two-level step trench can be formed while retaining the dielectric on the side wall of the first-level trench close to the first surface.
  • Layer 22 therefore, when performing ion implantation on the first two-level step trench, P+ ions can be implanted at the bottom and sidewalls of the first-level trench close to the second surface, while avoiding ion implantation at the first-level trench close to the first surface.
  • the sidewalls of the first-level trench are doped by P+ ion scattering, which solves the problem of abnormal channel opening of subsequent trench MOSFETs.
  • Step S14 As shown in Figures 21 to 23, form a gate structure g in the first trench;
  • the first trench 12 is a first double-step trench; a multi-step trench 16 is formed in the surface of the source region; the first double-step trench and the multi-step trench are filled with polysilicon; the gate structure g includes polysilicon filled in the first double-level step trench; between the first double-level step trench and the filled polysilicon, the multi-level step There is an insulating dielectric layer 15 between the trench 16 and the filled polysilicon; the gate structure g includes the polysilicon filled in the first double-step trench.
  • the part of the insulating dielectric layer 15 located in the first trench 12 is the first insulating dielectric layer 151 , which serves as the gate dielectric layer of the trench gate.
  • the part located in the multi-step trench 16 is the second insulating dielectric layer 152 .
  • an insulating dielectric layer 15 is formed covering the first surface and the surface of the first trench 12 and the multi-level stepped trench 16.
  • the insulating dielectric layer in the first trench 12 serves as a trench.
  • the insulating dielectric layer 15 is a SiO2 layer.
  • the insulating dielectric layer 15 can be grown in a high-temperature furnace tube. Oxygen can be introduced into the high-temperature furnace tube at 1100°C-1350°C.
  • the first trench 12 and the multi-step trench 16 SiO2 is oxidized and grown to form an insulating dielectric layer 15.
  • the thickness of the insulating dielectric layer 15 may be 40-70 nm.
  • the first trench 12 and the multi-level stepped trench 16 are filled with polysilicon.
  • silane or DCS gas and Ar, and doping gases containing phosphorus or B, phosphane, borane, etc. are passed into the LPCVD furnace tube; polysilicon is generated after the chemical cracking reaction, and the thickness of the polysilicon can be 400nm. to several um thickness.
  • a mixed gas of HBr, chlorine and oxygen is used to etch the polysilicon to remove the polysilicon on the first surface.
  • Step S15 As shown in Figures 24 and 25, form a metal gate on the surface of the gate structure g, form a metal source on the surface of the source region, and form silicon carbide as shown in Figure 3 Semiconductor device.
  • the metal gate G is located on the surface of the polysilicon filled in the first two-level step trench; the metal source S is located on the surface of the polysilicon filled in the multi-level step trench 16 .
  • step S15 first, as shown in FIG. 24, the insulating dielectric layer 15 on the first surface is etched to form an opening exposing the first surface.
  • F-based gases such as CHF 3 and CF 4 or chlorine-based gases containing Cl can be used to etch the first insulating dielectric layer 15 in the preset area on the surface of the source region to form the required openings.
  • a metal ohmic contact layer 18 is formed in the opening area of the first insulating dielectric layer 15 to reduce the contact resistance between the metal source S and the first surface.
  • PVD deposition of a single layer of Ni or multi-layer metal PVD deposition of Ti/Ni/Al can be carried out in the source area, and the metal except the source area can be stripped or etched away, and then carried out at 900°C-1100°C Rapid thermal annealing, the annealing time can be 30 seconds to 5 minutes, to form the metal ohmic contact layer 18 .
  • a metal gate G is formed on the surface of the trench gate, a metal source S is formed on the surface of the trench source, and a metal drain D is formed on the surface of the semiconductor substrate 10 away from the silicon carbide epitaxial layer 11, as shown in Figure 3 Silicon carbide semiconductor device shown.
  • the subsequent metal processes such as gate and source electrodes, the metal processes of the passivation layer and polyimide PI glue, and the back drain electrode are all conventional process methods and will not be described again.
  • the first trench 12 is a first double-step trench, and the source region has a second double-step trench.
  • the carbonization shown in FIG. 3 can be produced. Silicon semiconductor devices.
  • P+ ions are implanted into the bottom of the first double-stage step trench, it is avoided that the conventional single-stage trench design is used to implant P+ ions due to the scattering of the mask and the trench sidewalls, causing the upper sidewalls of the trench to be implanted.
  • a silicon carbide MOSFTE device with a double-step trench structure can be formed, and a double-step trench can be formed in the gate region and the source regions on both sides.
  • the gate region has a first two-level step trench for forming a trench gate
  • the source region has a second two-level step trench for forming a trench source.
  • a first voltage-resistant shielding structure 13 is formed at the bottom of the first-level trench near the second surface of the first double-level step trench and in the silicon carbide epitaxial layer 11 in the sidewall.
  • the sidewalls of the trenches at each level, and the second voltage-resistant shielding structure 14 is formed in the silicon carbide epitaxial layer 11 of each step.
  • the shielding layer problem solves the damage caused by high-dose and high-energy P+ ion implantation and the resulting reliability problems, and can achieve better shielding and protection of the trench gate.
  • a trench source structure is formed based on the double-step trench in the source area, which can easily realize the injection of a P+ electric field shielding structure with a depth of 1-2um or more in the source area, which can provide good shielding and Protect the sidewalls and bottom of the trench gate and enhance the gate reliability of silicon carbide MOSFET devices.
  • the silicon carbide semiconductor device and the manufacturing process of the double-level step trench structure can also be extended to the solution of the multi-level step trench structure to achieve a deeper P+ ion implantation distribution depth and better control of the gate area.
  • electric field shielding protection and can form a semi-superjunction structure. Therefore, in order to form newer P+ ion implantation in the source region and form a deeper second withstand voltage shielding structure 14 in the source region, a three-level step trench can be formed in the source region to form a deeper P+ shield in the source region.
  • the method of forming the second voltage-resistant shielding structure 14 includes: using an ion implantation method to form an ion implantation region in the source region as the second voltage-resistant shielding structure 14; the ion implantation region The implantation depth is not less than the depth of the first trench.
  • This method can form a silicon carbide semiconductor device as shown in Figure 6.
  • a double-step trench structure is formed only in the gate region, and high-energy and high-dose P+ ion implantation is directly used in the source region to form the second voltage-withstanding shielding structure 14, which forms the electric field shielding and shielding of the trench gate.
  • protection and process methods please refer to the process flow of the device structure shown in Figure 3, which will not be described again in the embodiments of this application.
  • the thickness of the insulating dielectric layer 15 at the bottom of the first double-step trench can be set to be greater than the thickness of the insulating dielectric layer 15 on the side walls of each level of the first double-step trench.
  • the thickness is greater than the thickness of the insulating dielectric layer 15 on the step between adjacent two-level trenches; the thickness of the insulating dielectric layer 15 at the bottom of the multi-level stepped trench 16 is greater than the thickness of the multi-level stepped trench.
  • the thickness of the insulating dielectric layer 15 on the sidewalls of the trenches at each level in 16 is greater than the thickness of the insulating dielectric layer 15 on the steps between the adjacent two levels of trenches, thereby forming silicon carbide as shown in Figure 5 Semiconductor device.
  • the process and structure can be further selectively optimized.
  • first use The CVD process of forming SiO 2 fills the trenches in the gate region and the source region, and then uses a gas ICP or RIE plasma etching process with a high selectivity for SiO 2 :SiC to etch back the trenches and the SiO 2 on the first surface.
  • the SiO 2 layer 31 is filled in both the gate region and the double step trench in the source region.
  • a relatively dense furnace tube thermal oxidation layer process can be used, such as TEOS or HTO thermal oxidation silicon dioxide process.
  • SiH 4 or DCS gas reacts with NO or O2 to deposit a relatively dense layer on the surface of the double-step trench.
  • SiO 2 layer 31 is filled in both the gate region and the double step trench in the source region.
  • the SiO 2 layer 31 on the first surface and the SiO 2 layer 31 in the double-step trench are etched away, leaving the preset thickness of SiO 2 in the first-level trench close to the second surface side.
  • Plasma etching process can be used to select a gas with a high etching selectivity ratio for SiO 2 : SiC, such as C 4 F 8 , etc., to etch back, retaining the preset thickness at the bottom of the first-level trench close to the second surface side SiO 2 layer 31.
  • a SiO2 layer is grown on the first surface and the surface of the two double-step trenches.
  • oxygen is introduced into the high-temperature furnace tube to grow SiO2 with a thickness of 40-70nm. .
  • This SiO 2 layer forms the insulating dielectric layer 15 together with the SiO 2 layer 31 remaining at the bottom of the previous trench.
  • a thicker insulating dielectric layer 15 can be formed at the bottom of the trench, which can further increase the voltage resistance of the bottom of the trench gate of the device and further improve the reliability of the device.

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Abstract

本申请公开了一种碳化硅半导体器件及其制作方法，所述碳化硅半导体器件包括：碳化硅外延层，具有相对的第一表面和第二表面，第一表面包括栅极区域以及位于栅极区域两侧的源极区域；栅极区域的表面内具有第一沟槽；基于第一沟槽形成在碳化硅外延层内的第一耐压掩蔽结构；位于第一沟槽内的栅极结构，表面上具有金属栅极；源极区域的表面内具有第二耐压掩蔽结构；源极区域的表面上具有金属源极；第一表面内具有阱区，位于第一沟槽与第二耐压掩蔽结构之间。碳化硅半导体器件基于第一沟槽在碳化硅外延层内形成有第一耐压掩蔽结构，在源极区域的表面内形成有第二耐压掩蔽结构，提高了第一沟槽底部拐角区域的耐压性，解决了在电场集中区域容易出现击穿问题。

Description

碳化硅半导体器件及其制作方法
本申请要求于2022年4月24日提交中国专利局、申请号为202210433930.0、发明名称为“碳化硅半导体器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请要求于2022年4月24日提交中国专利局、申请号为202220975064.3、发明名称为“碳化硅半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件技术领域，更具体的说，涉及一种碳化硅(SiC)半导体器件及其制作方法。
背景技术
随着科学技术的不断发展，越来越多的电子设备被广泛的应用于人们的日常生活以及工作当中，为人们的日常生活以及工作带来了巨大的便利，成为当今人们不可或缺的重要工具。
电子设备实现各种功能的主要结构是集成电路，而半导体器件是集成电路的重要组成电子元件。碳化硅半导体器件由于其在高功率应用领域的优良特性，成为半导体领域的一个主要发展方向。
然而碳化硅半导体器件在高功率器件应用领域，由于较高电场的存在，在电场集中区域容易出现击穿问题。
发明内容
有鉴于此，本申请提供了一种碳化硅半导体器件及其制作方法，方案如下：
一种碳化硅半导体器件，所述碳化硅半导体器件包括：
碳化硅外延层，所述碳化硅外延层具有相对的第一表面和第二表面，所述第一表面包括栅极区域以及位于所述栅极区域两侧的源极区域；
所述栅极区域的表面内具有第一沟槽；
基于所述第一沟槽形成在所述碳化硅外延层内的第一耐压掩蔽结构；
位于所述第一沟槽内的栅极结构；
所述栅极结构的表面上具有金属栅极；
所述源极区域的表面内具有第二耐压掩蔽结构；
所述源极区域的表面上具有金属源极；
所述第一表面内具有阱区，所述阱区位于所述第一沟槽与所述第二耐压掩蔽结构之间。
优选的，在碳化硅半导体器件中，在所述第一沟槽的深度方向上，所述第一耐压掩蔽结构位于所述阱区朝向所述第二表面的一侧，且与所述阱区无接触。
优选的，在碳化硅半导体器件中，所述第一沟槽为第一双级台阶沟槽；
所述栅极结构包括填充所述第一沟槽的多晶硅，所述第一沟槽与所填充的多晶硅之间具有第一绝缘介质层；
所述第一耐压掩蔽结构包括位于所述第一双级台阶沟槽朝向所述第二表面的一级沟槽的侧壁以及底部表面内的掺杂区域。
优选的，在碳化硅半导体器件中，所述阱区相对于所述第一表面的深度小于所述第一双级台阶沟槽中两级沟槽之间台阶的深度，所述第一耐压掩蔽结构位于所述第一双级台阶沟槽中两级沟槽之间台阶朝向所述第二表面的一侧。
优选的，在碳化硅半导体器件中，所述第一沟槽为第一双级台阶沟槽；所述第一双级台阶沟槽内填充有多晶硅，所述第一双级台阶沟槽与所填充的多晶硅之间具有第一绝缘介质层；
所述第一双级台阶沟槽底部的所述绝缘介质层的厚度大于所述第一双级台阶沟槽中各级沟槽侧壁上的所述绝缘介质层的厚度，大于相邻两级沟槽之间台阶上的所述绝缘介质层的厚度。
优选的，在碳化硅半导体器件中，所述源极区域的表面内具有多级台阶沟槽；所述多级台阶沟槽内填充有多晶硅，所述多级台阶沟槽与所填充的多晶硅之间具有第二绝缘介质层；
所述第二耐压掩蔽结构包括基于所述多级台阶沟槽形成在所述碳化硅外延层内的掺杂区域。
优选的，在碳化硅半导体器件中，所述第一沟槽为第一双级台阶沟槽；所述多级台阶沟槽为第二双级台阶沟槽，所述第一双级台阶沟槽与所述第二双级台阶沟槽的深度相同。
优选的，在碳化硅半导体器件中，所述第一沟槽为第一双级台阶沟槽；
所述多级台阶沟槽为三级台阶沟槽，所述三级台阶沟槽的深度大于所述第一双级台阶沟槽的深度。
优选的，在碳化硅半导体器件中，所述第二耐压掩蔽结构包括位于所述多级台阶沟槽的侧壁、台阶、底部以及开口四周的碳化硅外延层内的掺杂区域。
优选的，在碳化硅半导体器件中，所述多级台阶沟槽底部的所述第二绝缘介质层的厚度大于所述多级台阶沟槽中各级沟槽侧壁上的所述第二绝缘介质层的厚度，大于相邻两级沟槽之间台阶上的所述第二绝缘介质层的厚度。
优选的，在碳化硅半导体器件中，所述第二耐压掩蔽结构为形成在所述源极区域内的离子注入区域。
优选的，在碳化硅半导体器件中，所述离子注入区域的注入深度不小于所述第一沟槽的深度。
本申请还提供了一种上述任一项所述碳化硅半导体器件的制作方法，所述制作方法包括：
提供一外延片，所述外延片包括碳化硅外延层，所述碳化硅外延层具有相对的第一表面和第二表面，所述第一表面包括栅极区域以及位于所述栅极区域两侧的源极区域；
在所述栅极区域形成第一沟槽；
基于所述第一沟槽，在所述碳化硅外延层内形成第一耐压掩蔽结构；
在所述第一沟槽内形成栅极结构；
在所述栅极结构的表面上形成金属栅极，在所述源极区域的表面上形成金属源极；
其中，所述源极区域的表面内具有第二耐压掩蔽结构；所述第一表面内具有阱区，所述阱区位于所述第一沟槽与所述第二耐压掩蔽结构之间。
优选的，在制作方法中，所述第一沟槽为第一双级台阶沟槽；
在所述源极区域表面内形成有多级台阶沟槽；
制备所述第一耐压掩蔽结构和所述第二耐压掩蔽结构的方法包括：
基于所述第一双级台阶沟槽以及第一双级台阶沟槽靠近第一表面一级沟槽侧壁的介质层，对所述第一双级台阶沟槽靠近所述第二表面的一级沟槽的侧壁以及底部进行离子注入，在第一双级台阶沟槽靠近第二表面的一级沟槽侧壁和底部的碳化硅外延层内形成所述第一耐压掩蔽结构；
基于所述多级台阶沟槽，在所述多级台阶沟槽的底部、各级沟槽的台阶以及侧壁进行离子注入，在所述多级台阶沟槽的底部、各级沟槽的台阶以及侧壁的碳化硅外延层内形成所述第二耐压掩蔽结构。
优选的，在制作方法中，所述第一沟槽为第一双级台阶沟槽；所述源极区域的表面内形成有多级台阶沟槽；所述第一双级台阶沟槽以及所述多级台阶沟槽内均填充有多晶硅；所述栅极结构包括所述第一双级台沟槽内所填充的多晶硅；
所述第一双级台阶沟槽与所填充的多晶硅之间、所述多级台阶沟槽与所填充的多晶硅之间均具有绝缘介质层；所述栅极结构包括所述第一双级台阶沟槽内填充的多晶硅；
其中，所述金属栅极位于所述第一双级台阶沟槽所填充的多晶硅的表面上；所述金属源极位于所述多级台阶沟槽所填充的多晶硅的表面上。
优选的，在制作方法中，所述第一双级台阶沟槽底部的所述绝缘介质层的厚度大于所述第一双级台阶沟槽中各级沟槽侧壁上的所述绝缘介质层的厚度，大于相邻两级沟槽之间台阶上的所述绝缘介质层的厚度；
所述多级台阶沟槽底部的所述绝缘介质层的厚度大于所述多级台阶沟槽中各级沟槽侧壁上的所述绝缘介质层的厚度，大于相邻两级沟槽之间台阶上的 所述绝缘介质层的厚度。
优选的，在制作方法中，所述多级台阶沟槽为第二双级台阶沟槽，所述第二双级台阶沟槽与所述第一双级台阶沟槽的深度相同；或，所述多级台阶沟槽为三级台阶沟槽，所述三级台阶沟槽的深度大于所述第一双级台阶沟槽的深度。
优选的，在制作方法中，形成所述第二耐压掩蔽结构的方法包括：
通过离子注入方法，在所述源极区域形成离子注入区域，作为所述第二耐压掩蔽结构；
所述离子注入区域的注入深度不小于所述第一沟槽的深度。
通过上述描述可知，本申请技术方案提供的碳化硅半导体器件及其制作方法中，所述碳化硅半导体器件包括：碳化硅外延层，所述碳化硅外延层具有相对的第一表面和第二表面，所述第一表面包括栅极区域以及位于所述栅极区域两侧的源极区域；所述栅极区域的表面内具有第一沟槽；基于所述第一沟槽形成在所述碳化硅外延层内的第一耐压掩蔽结构；位于所述第一沟槽内的栅极结构；所述栅极结构的表面上具有金属栅极；所述源极区域的表面内具有第二耐压掩蔽结构；所述源极区域的表面上具有金属源极；所述第一表面内具有阱区，所述阱区位于所述第一沟槽与所述第二耐压掩蔽结构之间。所述碳化硅半导体器件基于第一沟槽在所述碳化硅外延层内形成有第一耐压掩蔽结构，在所述源极区域的表面内形成有第二耐压掩蔽结构，提高了第一沟槽底部拐角区域的耐压性能，解决了在电场集中区域容易出现击穿问题。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本申请可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本申请所能产生的功效及所能达成的目的下，均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
图1为一种DMOSFET的结构示意图；
图2为一种UMOSFET的结构示意图；
图3为本申请实施例提供的一种碳化硅半导体器件的结构示意图；
图4为本申请实施例提供的另一种碳化硅半导体器件的结构示意图；
图5为本申请实施例提供的又一种碳化硅半导体器件的结构示意图；
图6为本申请实施例提供的又一种碳化硅半导体器件的结构示意图；
图7-图29为本申请实施例提供的一种碳化硅半导体器件制作方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请中的实施例进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
SiC材料因其优良特性，在高功率方面具有强大的吸引力，成为高性能功率MOSFET的理想材料之一。SiC垂直功率MOSFET器件主要有横向型的双扩散DMOSFET以及垂直栅槽结构的UMOSFET。
如图1所示，图1为一种DMOSFET的结构示意图，包括：n+(n型重掺杂)的基底2；设置在基底2表面上的n-(n型轻掺杂)的漂移区3；位于漂移区3内的p型阱区4；以及位于p型阱区内的源区5，源区5包括n+掺杂区51和p+(p型重掺杂)掺杂区52。漂移区3表面上设置有栅极介质层7，栅极介质层7表面上具有栅极8。基底2背离漂移区3的一侧表面具有漏极1。
DMOSFET结构采用了平面扩散技术，采用难熔材料，如多晶硅栅作掩膜，用多晶硅栅的边缘定义p基区和n+源区。DMOS的名称就源于这种双扩散工艺。利用p型基区和n+源区的侧面扩散差异来形成表面沟道区域。
如图2所示，图2为一种UMOSFET的结构示意图，与图1所示结构不同在于，UMOSFET中设置有U型槽，U型槽的表面覆盖有栅极介质层7，栅极8填充在U型槽内。垂直栅槽结构的UMOSFET，其命名源于U型沟槽结构。该U型沟槽结构利用反应离子刻蚀在栅区形成。U型沟槽结构具有较高的沟道密度(沟道密度定义为有源区沟道宽度)，这使得器件的开态特征电阻显著减小。
平面型SiC MOSFET经过行业内多年的研究，已经有一些厂商率先推出了商业化产品。对于普通横向型DMOSFET结构而言，现代技术进步已经达到了缩小MOS元胞尺寸而无法降低导通电阻的程度，主要原因是由于JFET颈区电阻的限制，即使采用更小的光刻尺寸，单位面积导通电阻也难以降到2mΩ·cm 2，而沟槽结构可以有效解决这个问题。U型沟槽结构如图2所示，其采用了在存储器存储电容制各工艺中沟槽刻蚀技术，使导电沟道从横向变为纵 向，相比普通结构消除了JFET颈电阻，大大增加了元胞密度，提高了功率半导体的电流处理能力。
然而，SiC UMOSFET在实际工艺制作和应用中仍然存在几个问题：
1)SiC漂移区的高电场导致栅极介质层上的电场很高，这个问题在槽角处加剧，从而在高漏极电压下造成栅极介质层迅速击穿；对于恶劣环境的静电效应以及电路中的高压尖峰耐受能力差。
2)离子注入深度有限，导致很多针对性的沟槽栅极保护结构和抗浪涌设计从工艺上难以实现。
3)单一矩型或是U型栅极沟槽由于SiC本身材料特性，高温炉管氧化过程中，沟槽底部作为二氧化硅层厚度往往偏薄，降低了沟槽底部的耐压能力和器件的可靠性。
为了解决上述问，本申请技术方案提供了一种所述碳化硅半导体器件基于第一沟槽在所述碳化硅外延层内形成有第一耐压掩蔽结构，在所述源极区域的表面内形成有第二耐压掩蔽结构，提高了第一沟槽底部拐角区域的耐压性能，解决了在电场集中区域容易出现击穿问题，提高了器件对恶劣环境的静电承受能力以及对电路中高压尖峰的耐受能力。而且可以基于第一沟槽形成第一耐压掩蔽结构，能够增加形成第一耐压掩蔽结构时的离子注入深度，在工艺上便于实现多种针对沟槽栅极保护结构和抗浪涌设计。进一步的，还可以在沟槽底部形成厚度较大的绝缘介质层，解决了常规高温炉管氧化过程无法在沟槽形成厚度较大的二氧化硅层的问题，进一步提高了沟槽底部的耐压能力和器件的可靠性。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
如图3所示，图3为本申请实施例提供的一种碳化硅半导体器件的结构示意图，所示碳化硅半导体器件包括：
碳化硅外延层11，所述碳化硅外延层11具有相对的第一表面和第二表面，所述第一表面包括栅极区域以及位于所述栅极区域两侧的源极区域；
所述栅极区域的表面内具有第一沟槽12；
基于所述第一沟槽12形成在所述碳化硅外延层11内的第一耐压掩蔽结构13；
位于所述第一沟槽12内的栅极结构g；
所述栅极结构的表面上具有金属栅极G；
所述源极区域的表面内具有第二耐压掩蔽结构14；
所述源极区域的表面上具有金属源极S；
所述第一表面内具有阱区W，所述阱区W位于所述第一沟槽12与所述第二耐压掩蔽结构14之间。
所述碳化硅半导体器件基于第一沟槽12在所述碳化硅外延层11内形成有第一耐压掩蔽结构13，在所述源极区域的表面内形成有第二耐压掩蔽结构14，提高了在第一沟槽12底部拐角区域的耐压性能，解决了在电场集中区域容易出现击穿问题，提高了器件对恶劣环境的静电承受能力以及对电路中高压尖峰 的耐受能力。而且可以基于第一沟槽12形成第一耐压掩蔽结构13，能够增加形成第一耐压掩蔽结构13时的离子注入深度，在工艺上便于实现多种针对沟槽栅极保护结构和抗浪涌设计。
进一步的，还可以在沟槽底部形成厚度较大的绝缘介质层，解决了常规高温炉管氧化过程无法在沟槽形成厚度较大的二氧化硅层的问题，进一步提高了沟槽底部的耐压能力和器件的可靠性。
可选的，所述碳化硅外延层11制备在半导体基底10表面，第二表面朝向半导体基底10。在半导体基底10背离所述碳化硅外延层11的一侧表面设置有金属漏极D。金属源极S和金属漏极D可以Ti或是Al等，金属漏极D可以为Ni、Ti、Al或Ag中的一种或是多种的复合金属层。
碳化硅外延层11和半导体基底10的掺杂类型相同，阱区W、第一耐压掩蔽结构13和第二耐压掩蔽结构14的掺杂类型相同，且与外延层11的掺杂类型相反。P型掺杂和N型掺杂为相反类型的掺杂。阱区W靠近第一表面的碳化硅外延层11内具有与阱区W掺杂类型相反的离子注入区域17，当阱区W为P型掺杂时，该离子注入区域17可以为N+离子注入区域。
其中，半导体基底10可以为N+(N型重掺杂)碳化硅基底；外延层11为N-(N型轻掺杂)的碳化硅外延层，作为半导体器件的漂移区；阱区W为P型阱区。第一耐压掩蔽结构13和第二耐压掩蔽结构14包括P+(P型重掺杂)离子注入区域。需要说明的是，本申请实施例中，器件各个区域的掺杂类型不局限于实施例记载，可以基于需求设定其掺杂类型，以形成PMOS或是NMOS结构。
在所述第一沟槽的深度方向上，所述第一耐压掩蔽结构13位于所述阱区W朝向所述第二表面的一侧，且与所述阱区W无接触，也就说在图3竖直方向上，第一耐压掩蔽结构13位于阱区W的下方，且与阱区W无接触。
在图3所示方式中，所述第一沟槽12为第一双级台阶沟槽；所述栅极结构g包括填充所述第一沟槽12的多晶硅，所述第一沟槽12与所填充的多晶硅之间具有第一绝缘介质层151；所述第一耐压掩蔽结构13包括位于所述第一双级台阶沟槽朝向所述第二表面的一级沟槽的侧壁表面内以及底部表面内的掺杂区域。第一绝缘介质层151为栅极氧化层，可以为二氧化硅。
第一双级台阶沟槽具有两级沟槽以及位于两级沟槽之间的台阶结构，所述第一双级台阶沟槽的一级沟槽靠近第一表面，另一级靠近第二表面，靠近第一表面的一级沟槽开口大于靠近第二表面的一级沟槽的开口。基于所述第一双级台阶沟槽靠近第一表面的一级沟槽侧壁的牺牲层，对第一双级台阶沟槽进行离子注入，形成第一耐压掩蔽结构13，从而避免离子注入时由于离子散射导致所述第一双级台阶沟槽靠近第一表面的一级沟槽侧壁产生离子注入，使得第一耐压掩蔽结构13位于阱区W下方，避免二者接触，从而避免由此导致的半导体器件沟道开启异常问题，保证器件的正常工作。
第一绝缘介质层151延伸至所述第一沟槽12的外部，覆盖所述第一表面。第一绝缘介质层151在所述第一表面具有开口，用于设置金属欧姆接触层18，源极金属S通过金属欧姆接触层18和碳化硅外延层11在所述开口连接。
所述阱区W相对于所述第一表面的深度小于所述第一双级台阶沟槽中两级沟槽之间台阶的深度，所述第一耐压掩蔽结构13位于所述第一双级台阶沟槽中两级沟槽之间台阶朝向所述第二表面的一侧。
在图3所示方式中，所述源极区域的表面内具有多级台阶沟槽16；所述多级台阶沟槽16内填充有多晶硅，所述多级台阶沟槽16与所填充的多晶硅之间具有第二绝缘介质层152；所述第二耐压掩蔽结构14包括基于所述多级台阶沟槽形成在所述碳化硅外延层11内的掺杂区域。
其中，所述第一沟槽12表面的第一绝缘介质层151和所述多级台阶沟槽16表面的第二绝缘介质层152材料相同，同时形成。所述第一沟槽12内所述填充的多晶硅与所述多级台阶沟槽16中所填充的多晶硅同时形成。
所述第二耐压掩蔽结构14包括位于所述多级台阶沟槽16的侧壁、台阶、底部以及开口四周的碳化硅外延层11内的掺杂区域，也就是说，所述多级台阶沟槽16的侧壁、台阶、底部以及开口四周的碳化硅外延层内均设置有所述第二耐压掩蔽结构14。
在图3所示方式中，所述第一沟槽12为第一双级台阶沟槽；所述多级台阶沟槽16为第二双级台阶沟槽，所述第一双级台阶沟槽与所述第二双级台阶沟槽的深度相同，二者可以同工序流程制备。
本申请实施例中，所述多级台阶沟槽16不局限于为双级台阶沟槽，还可以为大于2级的台阶沟槽。可以基于器件厚度参数以及离子注入深度需求，设置所述多级台阶沟槽16的沟槽台阶级数。
本申请实施例中，所述碳化硅半导体器件可以为碳化硅MOSFET器件。在图3所示方式中，在栅极区域基于第一沟槽12形成有沟槽栅极，栅极区域两侧的源极区域，基于多级台阶沟槽16形成有沟槽源极。所述第一沟槽12和所述多级台阶沟槽16均可以双级台阶沟槽，此时，形成双级台阶沟槽结构的碳化硅MOSFET器件。
如图4所示，图4为本申请实施例提供的另一种碳化硅半导体器件的结构示意图，基于图3所示方式，图4所示方式中，所述第一沟槽12为第一双级台阶沟槽；所述多级台阶沟槽16为三级台阶沟槽，所述三级台阶沟槽的深度大于所述第一双级台阶沟槽的深度。
如图5所示，图5为本申请实施例提供的又一种碳化硅半导体器件的结构示意图，图5所示碳化硅半导体器件中，所述第一沟槽12为第一双级台阶沟槽；所述第一双级台阶沟槽内填充有多晶硅，所述栅极结构g包括填充所述第一双级台阶沟槽的多晶硅，所述第一双级台阶沟槽与所填充的多晶硅之间具有第一绝缘介质层151。在图3所示方式基础上，图5所示碳化硅半导体器件中，所述第一双级台阶沟槽底部的所述第一绝缘介质层151的厚度大于所述第一双级台阶沟槽中各级沟槽侧壁上的所述第一绝缘介质层151的厚度，大于相邻两级沟槽之间台阶上的所述第一绝缘介质层151的厚度。
在图5所示方式中，所述多级台阶沟槽底部16的所述第二绝缘介质层152的厚度大于所述多级台阶沟槽16中各级沟槽侧壁上的所述第二绝缘介质层152的厚度，大于相邻两级沟槽之间台阶上的所述第二绝缘介质层152的厚度。第二绝缘介质层152和第一绝缘介质层151为同一层绝缘介质层15。
显然，也可以在图4所示方式基础上，设置第一绝缘介质层151和第二绝缘介质层152都是位于所在沟槽底部的厚度大于所在沟槽其他区域的厚度。
本申请实施例所述碳化硅半导体器件能够基于栅极区域内的第一沟槽12形成沟槽栅极，基于栅极区域两侧源极区域内的多级台阶沟槽16形成沟槽源极，并在第一沟槽12的底部通过离子注入形成第一耐压掩蔽结构13，在多级台阶沟槽16的底部、侧壁以及两级沟槽之间台阶的碳化硅外延层11内通过离 子注入形成第二耐压掩蔽结构14。其中，第一耐压掩蔽结构13和第二耐压掩蔽结构14都可以为P+(P型重掺杂)区域。
基于所述第一沟槽12以及所述多级台阶沟槽16分别在所述碳化硅外延层11内通过离子注入形成第一耐压掩蔽结构13和第二耐压掩蔽结构14，解决了碳化硅材料里面难以形成较深的P+掩蔽层以及高剂量高能量P+离子注入的损伤问题，提高了器件的可靠性，同时可以更好的屏蔽和保护栅极沟槽。离子激活形成第一耐压掩蔽结构13和第二耐压掩蔽结构14后，在第一沟槽12和多级台阶沟槽16表面生长二氧化硅层作为第一绝缘介质层151和第二绝缘介质层152，而后在第一沟槽12和多级台阶沟槽16内填充多晶硅，之后形成金属电极后，完成双级台阶沟槽结构的碳化硅MOSFET器件。
如图6所示，图6为本申请实施例提供的又一种碳化硅半导体器件的结构示意图，所述第二耐压掩蔽结构14为形成在所述源极区域内的离子注入区域。该方式无需在源极区域形成沟槽，直接通过离子注入形成工艺形成设定深度的离子注入区域，作为所述第二耐压掩蔽结构14。在图6所示方式中，为了实现更好的耐压掩蔽效果，所述离子注入区域的注入深度不小于所述第一沟槽12的深度。
基于上述实施例，本申请另一实施例还提供了一种碳化硅半导体器件的制作方法，用于制作上述实施例所述的碳化硅半导体器件，所述制作方法可以如图7-图29所示。
参考图7-图29所示，图7-图29为本申请实施例提供的一种碳化硅半导体器件制作方法的流程示意图，该制作方法包括：
步骤S11：如图7所示，提供一外延片，所述外延片包括碳化硅外延层11，所述碳化硅外延层11具有相对的第一表面和第二表面，所述第一表面包括栅极区域以及位于所述栅极区域两侧的源极区域。
可以采用具有N-碳化硅外延层11的N+碳化硅半导体基底10，制备所述碳化硅半导体器件。其中，碳化硅外延层11的第二表面朝向半导体基底10。
步骤S12：如图8-图16所示，在所述栅极区域形成第一沟槽12。
在形成第一沟槽12前，通过在第一表面进行离子注入，在碳化硅外延层11内形成阱区W、离子注入区17和电场缓冲区19。离子注入区17和电场缓冲区19位于源极区域的表面内，且位于阱区W内。
该制作方法以源极区域具有多级台阶沟槽16为例进行说明，后续工艺基于多级台阶沟16形成第二耐压掩蔽结构14。电场缓冲区19能够解决多级台阶沟槽16在开口位置由于第二耐压掩蔽结构14厚度较薄导致的漏电和击穿问题，增强了器件的可制造性和可靠性。电场缓冲区19和第二耐压掩蔽结构14的掺杂类型相同，如都可以为N+掺杂。离子注入区17和第二耐压掩蔽结构14的掺杂类型相反，离子注入区17可以为N+掺杂区域。
以第一沟槽12为第一双级台阶沟槽，多级台阶沟槽16是第二双级台阶沟槽为例进行说明，可以在形成第一双级台阶沟槽的同时形成第二双级台阶沟槽，形成第一双级台阶沟槽和第二双级台阶沟槽的具体过程如下：
步骤S121：如图8所示，在第一表面通过离子注入，形成阱区W以及位于阱区内的离子注入区17和电场缓冲区19。
对于碳化硅材料，一般在500-600℃下，通过高温离子注入设备进行离子 注入，以降低对碳化硅材料晶格的损伤。
步骤S122：如图12所示，在第一表面进行第一级沟槽刻蚀。
可以采用等离子体干法刻蚀工艺，如RIE或是ICP刻蚀工艺，进行刻蚀形成第一级沟槽。对碳化硅材料的刻蚀原理如图9-图11所示。首先如图9所示，通过CVD等沉积工艺在碳化硅材料上沉积SiO 2作为掩膜层，在掩膜层表面旋涂光阻PR，通过曝光和显影形成所需图形的光阻PR，然后如图10所示，基于图形化的光阻PR，刻蚀掩膜层，形成图形化的掩膜层，最后如图11所示，基于图形化的掩膜层，对碳化硅材料进行刻蚀，在其表面形成沟槽。后续工艺中不再详细描述光刻及刻蚀等半导体通用的工艺过程。
如图12所示，刻蚀形成第一级沟槽时，可以通过CVD沉积一层SiO 2作为掩膜层21，采用CF 4、SF 6等含有F基的气体，或是氯气等含有Cl基的气体，以及Ar和氧气的混合气体，通过等离子体刻蚀设备ICP或是RIE，在栅极区域以及两侧的源极区域，对碳化硅外延层11进行刻蚀，以在栅极区域和源极区域分别形成第一级沟槽。第一级沟槽的深度为10nm-3μm，进一步的，可以设置第一级沟槽深度为800nm-1um，以使得器件具有更好的性能。
步骤S123：如图13所示，在第一级沟槽中填充SiO 2介质层22。可以采用CVD工艺沉积SiO 2介质层22，SiO 2介质层22填充第一级沟槽，并覆盖掩膜层21。
步骤S124：如图14所示，第二级沟槽的掩膜版23对位。
在SiO 2介质层22表面旋涂光阻，基于掩膜版23对光阻进行曝光和显影，以图形化该光阻，图14中未示出该光阻。
掩膜版23具有用于形成第一镂空区域和第二镂空区域，第一镂空区域用 于在栅极区域形成沟槽栅极的第二级沟槽，第二镂空区域用于在源极区域形成沟槽源极的第二级沟槽。掩膜版23中，第一镂空区域的开口小于栅极区域中第一级沟槽的开口，第二镂空区域的开口大于源极区域中第一级沟槽的开口。
步骤S125：如图15所示，基于SiO 2介质层22表面上的光阻，进行刻蚀，在栅极区域和源极区域的第一级沟槽基础上，分别形成第二级沟槽。
用CF 4、SF 6等含有F基的气体，或是氯气等含有Cl基的气体，以及Ar和氧气的混合气体，通过等离子体刻蚀设备ICP或是RIE，在栅极区域以及两侧的源极区域，对碳化硅外延层11进行刻蚀，以在栅极区域和源极区域分别形成第二级沟槽。第二级沟槽的刻蚀深度为100nm-3um；进一步的，可以设置第二级沟槽的刻蚀深度为300-500nm，以使得器件具有更好的性能。
由于第一镂空区域的开口小于栅极区域中第一级沟槽的开口，从而可以在栅极区域的第一级沟槽的底部刻蚀形成深度更大的第二级沟槽，从而形成第一双级台阶沟槽。基于该方式，在栅极区域形成第一双级台阶沟槽的同时，还能够在形成第一双级台阶沟槽的同时，在第一双级台阶沟槽靠近第一表面的一级沟槽侧壁保留SiO 2介质层22，作为牺牲层，以便于后续工艺形成第一耐压掩蔽结构13时，避免离子在第一双级台阶沟槽靠近第一表面的一级沟槽侧壁的散射问题，解决由此导致的沟道开启异常问题，保证器件的正常工作，提高器件可靠性。
由于第二镂空区域的开口大于源极区域中第一级沟槽的开口，故当向下刻蚀时，在第一级沟槽上部分尺寸增大，下部分深度增大，从而形成第二双级台阶沟槽。基于该方式，能够去除第二双级台阶沟槽的侧壁、台阶以及底部表面的SiO 2介质层22，在源极区域形成第二双级台阶沟槽后，经过离子注入，以 便于在第二双级台阶沟槽的侧壁、台阶以及底部的碳化硅外延层11内都进行离子注入形成第二耐压掩蔽结构14。
如图16所示，图16为基于本申请实施例所述制作方法，在源极区域和栅极区域形成双级台阶沟槽的SEM图，基于该SEM图可知，采用本申请实施例所述制作方法，能够在栅极区域和源极区域分别形成形貌良好的双级台阶沟槽。
步骤S13：如图17-图20所示，基于所述第一沟槽，在所述碳化硅外延层内形成第一耐压掩蔽结构13。
所述源极区域的表面内具有第二耐压掩蔽结构14；所述第一表面内具有阱区W，所述阱区W位于所述第一沟槽12与所述第二耐压掩蔽结构14之间。
所述第一沟槽12为第一双级台阶沟槽；在所述源极区域表面内形成有多级台阶沟槽16；制备所述第一耐压掩蔽结构13和所述第二耐压掩蔽结构14的方法包括：基于所述第一双级台阶沟槽以及第一双级台阶沟槽靠近第一表面一级沟槽侧壁的介质层22，对所述第一双级台阶沟槽靠近所述第二表面的一级沟槽的侧壁以及底部进行离子注入，在第一双级台阶沟槽靠近第二表面的一级沟槽侧壁和底部的碳化硅外延层内形成所述第一耐压掩蔽结构13；基于所述多级台阶沟槽16，在所述多级台阶沟槽16的底部、各级沟槽的台阶以及侧壁进行离子注入，在所述多级台阶沟槽的底部、各级沟槽的台阶以及侧壁的碳化硅外延层内形成所述第二耐压掩蔽结构14。
可以设置所述多级台阶沟槽16为第二双级台阶沟槽，所述第二双级台阶沟槽与所述第一双级台阶沟槽的深度相同；其他方式中，还可以设置所述多级 台阶沟槽16为三级台阶沟槽，所述三级台阶沟槽的深度大于所述第一双级台阶沟槽的深度。
在步骤S13中，首先如图17所示，基于图形化的掩膜层21和介质层22，进行离子注入，形成第一耐压掩蔽结构13和第二耐压掩蔽结构14。可以采用高温离子注入设备在500-600℃下对沟槽侧壁及底部进行P+离子注入，以形成第一耐压掩蔽结构13和第二耐压掩蔽结构14，然后如图18所示，去除掩膜层21和介质层22，可以采用缓冲HF湿法去除二氧化硅掩膜，从而去除掩膜层21和介质层22。
对于碳化硅器件的P+离子注入，一般典型的注入离子为Al离子；离子注入能量可以在几百KeV到几个MeV，剂量为1E12cm -2-1E16cm -2；注入深度几百nm到几个微米。
特别的，由于在第一双级台阶沟槽中，由于靠近第一表面的一级沟槽的侧壁有一层几十到几百纳米，甚至微米级厚度的介质层22阻挡，离子注入时，第一双级台阶沟槽作为沟道区域的阱区W不会受到P+离子注入的影响。
如图19所示，图19为采用本申请实施例制作方法形成第一耐压掩蔽结构13和第二耐压掩蔽结构14之后的SEM图，基于图19可知，完成P+离子注入后，作为沟道区域的阱区W不会受到P+离子注入的影响，提高了器件的可靠性和稳定性。
如图20所示，图20为采用本申请实施例制作方法源极区域P+离子注入前与注入后的SEM图。左图为第二双级台阶沟槽对应区域P+离子注入前的SEM图。右图为第二双级台阶沟槽对应区域P+离子注入后的SEM图，右图中灰度较小的区域是Al离子注入后形成的SEM切片影像。
通过上述描述可知，沟槽栅极采用第一双级台阶沟槽，基于本申请方法能够在形成第一双级台阶沟槽的同时，在其靠近第一表面的一级沟槽侧壁保留介质层22，因此，当对第一双级台阶沟槽进行离子注入时，可以在其靠近第二表面的一级沟槽底部和侧壁进行P+离子注入，同时避免在其靠近第一表面的一级沟槽侧壁由于P+离子散射掺杂，解决了由此导致后续沟槽MOSFET沟道开启异常的问题。
步骤S14：如图21-图23所示，在所述第一沟槽内形成栅极结构g；
所述第一沟槽12为第一双级台阶沟槽；所述源极区域的表面内形成有多级台阶沟槽16；所述第一双级台阶沟槽以及所述多级台阶沟槽内均填充有多晶硅；所述栅极结构g包括所述第一双级台沟槽内所填充的多晶硅；所述第一双级台阶沟槽与所填充的多晶硅之间、所述多级台阶沟槽16与所填充的多晶硅之间均具有绝缘介质层15；所述栅极结构g包括所述第一双级台阶沟槽内填充的多晶硅。绝缘介质层15位于第一沟槽12内的部分为第一绝缘介质层151，作为沟槽栅极的栅极介质层，位于多级台阶沟槽16内的部分为第二绝缘介质层152。
在步骤S14中，首先如图21所示，形成覆盖第一表面以及第一沟槽12以及多级台阶沟槽16表面的绝缘介质层15，第一沟槽12内的绝缘介质层作为沟槽栅极的栅极介质层。可选的，绝缘介质层15为SiO2层。可以在高温炉管生长所述绝缘介质层15，可以在1100℃-1350℃下，在高温炉管中通入氧气，在第一表面、第一沟槽12以及多级台阶沟槽16的表面氧化生长SiO2，形成绝缘介质层15，绝缘介质层15的厚度可以为40-70nm。
然后，如图22所示，形成绝缘介质层15后，在第一沟槽12以及多级台 阶沟槽16内填充多晶硅。在540℃-800℃下，在LPCVD炉管中通入硅烷或DCS气体及Ar、及含有磷或B的掺杂气体磷烷硼烷等；化学裂解反应后生成多晶硅，多晶硅的厚度可以为400nm到几个um厚度。
在如图23所示，采用HBr、氯气和氧气的混合气体，对多晶硅进行刻蚀，去除第一表面上的多晶硅。
步骤S15：如图24、图25所示，在所述栅极结构g的表面上形成金属栅极，在所述源极区域的表面上形成金属源极，形成如图3所示的碳化硅半导体器件。
其中，所述金属栅极G位于所述第一双级台阶沟槽所填充的多晶硅的表面上；所述金属源极S位于所述多级台阶沟槽16所填充的多晶硅的表面上。
在步骤S15中，首先如图24所示，刻蚀第一表面的绝缘介质层15，形成露出第一表面的开口。可以采用CHF 3、CF 4等F基气体或含Cl的氯基气体等，对源极区域表面预设区域的第一绝缘介质层15进行刻蚀，形成所需开口。
然后如图25所示，在第一绝缘介质层15的开口区域内形成金属欧姆接触层18，以降低金属源极S和第一表面的接触阻抗。可以在源极区域进行单层Ni的PVD沉积、或Ti/Ni/Al等多层金属的PVD沉积，并剥离或刻蚀掉除源极区域以外的金属，然后在900℃-1100℃下进行快速热退火，退火时间可以为30秒-5分钟，形成金属欧姆接触层18。
最后，在沟槽栅极表面形成金属栅极G，在沟槽源极表面形成金属源极S，在半导体基底10背离碳化硅外延层11的一侧表面形成金属漏极D，形成如图3所示的碳化硅半导体器件。其中，后续的栅极及源极等金属工艺，钝化层及聚酰亚胺PI胶、及背面漏极的金属工艺等均为常规工艺方法，不再赘述。
在图7-图25所示方法中，第一沟槽12为第一双级台阶沟槽，源极区域具有第二双级台阶沟槽为例进行说明，可以制作如图3所示的碳化硅半导体器件。该方式中，当对第一双级台阶沟槽的底部进行P+离子注入时，避免了常规单级沟槽设计进行P+离子时由于掩膜和沟槽侧壁的散射，导致沟槽上部侧壁也会有P+离子注入，造成耐压掩蔽结构和作为沟道区域的阱区W连接，从而导致沟道开启异常的问题。
基于图7-图25所示方法，可以形成双级台阶沟槽结构的碳化硅MOSFTE器件，可以栅极区域及其两侧的源区域均形成双级台阶沟槽。具体的，栅极区域具有第一双级台阶沟槽，用于形成沟槽栅极，源极区域具有第二双级台阶沟槽，用于形成沟槽源极。在第一双级台阶沟槽靠近第二表面的一级沟槽的底部以及侧壁内的碳化硅外延层11内形成有第一耐压掩蔽结构13，在第二双级台阶沟槽的底部、各级沟槽的侧壁、及各台阶的碳化硅外延层11内形成有第二耐压掩蔽结构14，基于两个双级台阶沟槽，解决了碳化硅材料里难以形成较深的P+掩蔽层问题，解决了高剂量高能量P+离子注入损伤及因此导致的可靠性问题，可以实现更好的屏蔽和保护沟槽栅极。
如果单纯采用高能量和高剂量离子注入1-2um以上，容易造成对碳化硅材料较严重的离子注入损伤，引起后续器件长期工作的可靠性问题。本申请实施中，基于源极区域的双级台阶沟槽形成沟槽源极结构，可以在源极区域很容易的实现1-2um以上深度的P+电场掩蔽结构的注入，可以很好的屏蔽和保护沟槽栅极侧壁及底部，增强碳化硅MOSFET器件的栅极可靠性。
同时，对于具有第一双级台阶沟槽的沟槽栅极，当对第一双级台阶沟槽的底部进行P+离子注入时，避免了业界现有的单级沟槽制备沟槽栅极的方案中 P+离子会由于掩膜和沟槽侧壁的散射，导致沟槽侧壁也会有P+离子注入，导致后续沟槽MOSFET沟道开启异常的问题。
本申请实施例中，双级台阶沟槽构造的碳化硅半导体器件及制作工艺也可以扩展到多级台阶沟槽结构的方案，以达到更深的P+离子注入分布深度和对栅极区域的更好的电场掩蔽保护，以及可以形成半超结结构。故为了在源极区域形成更新的P+离子注入，以在源极区域形成更深的第二耐压掩蔽结构14，可以在源极区域形成三级台阶沟槽，在源极区域形成更深的P+掩蔽保护结构，以制备图4所示的碳化硅半导体器件。如图26所示，图26为本申请实施例提供的一种三级台阶沟槽的SEM图。
其他方式中，形成所述第二耐压掩蔽结构14的方法包括：通过离子注入方法，在所述源极区域形成离子注入区域，作为所述第二耐压掩蔽结构14；所述离子注入区域的注入深度不小于所述第一沟槽的深度。该方式可以形成如图6所示的碳化硅半导体器件。该方式中，仅在栅极区域形成双级台阶沟槽结构，源极区域直接采用高能量和高剂量的P+离子注入形成第二耐压掩蔽结构14，构成对沟槽栅极的电场屏蔽和保护，工艺方法可以参考图3所示器件结构的工艺流程，本申请实施例中不再赘述。
其他方式中，可以设置所述第一双级台阶沟槽底部的所述绝缘介质层15的厚度大于所述第一双级台阶沟槽中各级沟槽侧壁上的所述绝缘介质层15的厚度，大于相邻两级沟槽之间台阶上的所述绝缘介质层15的厚度；所述多级台阶沟槽16底部的所述绝缘介质层15的厚度大于所述多级台阶沟槽16中各级沟槽侧壁上的所述绝缘介质层15的厚度，大于相邻两级沟槽之间台阶上的所述绝缘介质层15的厚度，从而形成如图5所示的碳化硅半导体器件。
可以在图7-图25所示方法基础上，进一步选择性优化的工艺和结构，在离子注入和高温激活完成，形成第一耐压掩蔽结构13和第二耐压掩蔽结构14后，先采用CVD形成SiO 2工艺填充栅极区域和源极区域的沟槽，然后采用对SiO 2：SiC有高选择比的气体ICP或RIE等离子刻蚀工艺回刻沟槽以及第一表面的SiO 2，刻蚀掉第一表面、第一双级台阶沟槽和第二双级台阶沟槽靠近第一表面的一级沟槽内的SiO 2，第一双级台阶沟槽和第二双级台阶沟槽底部的SiO 2；接下来进行高温炉管生长侧壁的SiO 2，以及多晶硅填充。这样能够在第一双级台阶沟槽和第二双级台阶沟槽的底部形成更厚的绝缘介质层，能进一步增加器件的沟槽栅极底部的栅极介质层的耐压性，提高器件的可靠性。该过程可以如图27-图29所示，具体方法如下：
首先，如图27所示，在图18所示结构的基础上，在栅极区域以及源极区域的双级台阶沟槽内均填充SiO 2层31。可以采用较为致密的炉管热氧化层工艺，例如TEOS，或者HTO热氧化二氧化硅工艺，通过SiH 4或者DCS气体，和NO或者O2反应，在双级台阶沟槽表面沉积一层较为致密的SiO 2层31。
然后，如图28所示，刻蚀去除第一表面的SiO 2层31以及双级台阶沟槽内的SiO 2层31，保留靠近第二表面一侧的一级沟槽内预设厚度SiO 2层31。可以采用等离子刻蚀工艺，选择对SiO 2：SiC有高刻蚀选择比的气体，如C 4F 8等，进行回刻，保留靠近第二表面一侧的一级沟槽底部的预设厚度SiO 2层31。
在如图29所示，在第一表面以及两个双级台阶沟槽的表面生长SiO 2层，在1100℃-1350℃下，高温炉管中通入氧气，生长SiO2，厚度为40-70nm。该SiO 2层与之前沟槽底部保留的SiO 2层31形成绝缘介质层15。
采用图27-图29所示方法，能够在沟槽底部形成厚度较大的绝缘介质层15，可以进一步增加器件的沟槽栅极底部的耐压性，进一步提高器件的可靠性。
本说明书中各个实施例采用递进、或并列、或递进和并列结合的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
需要说明的是，在本申请的描述中，需要理解的是，幅图和实施例的描述是说明性的而不是限制性的。贯穿说明书实施例的同样的幅图标记标识同样的结构。另外，处于理解和易于描述，幅图可能夸大了一些层、膜、面板、区域等厚度。同时可以理解的是，当诸如层、膜、区域或基板的元件被称作“在”另一元件“上”时，该元件可以直接在其他元件上或者可以存在中间元件。另外，“在…上”是指将元件定位在另一元件上或者另一元件下方，但是本质上不是指根据重力方向定位在另一元件的上侧上。
术语“上”、“下”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。当一个组件被认为是“连接”另一个组件，它可以是直接连接到另一个组件或者可能同时存在居中设置的组件。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这 些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (18)

  1. 一种碳化硅半导体器件，其特征在于，所述碳化硅半导体器件包括：
    碳化硅外延层，所述碳化硅外延层具有相对的第一表面和第二表面，所述第一表面包括栅极区域以及位于所述栅极区域两侧的源极区域；
    所述栅极区域的表面内具有第一沟槽；
    基于所述第一沟槽形成在所述碳化硅外延层内的第一耐压掩蔽结构；
    位于所述第一沟槽内的栅极结构；
    所述栅极结构的表面上具有金属栅极；
    所述源极区域的表面内具有第二耐压掩蔽结构；
    所述源极区域的表面上具有金属源极；
    所述第一表面内具有阱区，所述阱区位于所述第一沟槽与所述第二耐压掩蔽结构之间。
  2. 根据权利要求1所述的碳化硅半导体器件，其特征在于，在所述第一沟槽的深度方向上，所述第一耐压掩蔽结构位于所述阱区朝向所述第二表面的一侧，且与所述阱区无接触。
  3. 根据权利要求1所述的碳化硅半导体器件，其特征在于，所述第一沟槽为第一双级台阶沟槽；
    所述栅极结构包括填充所述第一沟槽的多晶硅，所述第一沟槽与所填充的多晶硅之间具有第一绝缘介质层；
    所述第一耐压掩蔽结构包括位于所述第一双级台阶沟槽朝向所述第二表面的一级沟槽侧壁表面内以及底部表面内的掺杂区域。
  4. 根据权利要求3所述的碳化硅半导体器件，其特征在于，所述阱区相对于所述第一表面的深度小于所述第一双级台阶沟槽中两级沟槽之间台阶的深度，所述第一耐压掩蔽结构位于所述第一双级台阶沟槽中两级沟槽之间台阶朝向所述第二表面的一侧。
  5. 根据权利要求1所述的碳化硅半导体器件，其特征在于，所述第一沟槽为第一双级台阶沟槽；所述第一双级台阶沟槽内填充有多晶硅，所述第一双级台阶沟槽与所填充的多晶硅之间具有第一绝缘介质层；
    所述第一双级台阶沟槽底部的所述绝缘介质层的厚度大于所述第一双级台阶沟槽中各级沟槽侧壁上的所述绝缘介质层的厚度，大于相邻两级沟槽之间台阶上的所述绝缘介质层的厚度。
  6. 根据权利要求1所述的碳化硅半导体器件，其特征在于，所述源极区域的表面内具有多级台阶沟槽；所述多级台阶沟槽内填充有多晶硅，所述多级台阶沟槽与所填充的多晶硅之间具有第二绝缘介质层；
    所述第二耐压掩蔽结构包括基于所述多级台阶沟槽形成在所述碳化硅外延层内的掺杂区域。
  7. 根据权利要求6所述的碳化硅半导体器件，其特征在于，所述第一沟槽为第一双级台阶沟槽；所述多级台阶沟槽为第二双级台阶沟槽，所述第一双级台阶沟槽与所述第二双级台阶沟槽的深度相同。
  8. 根据权利要求6所述的碳化硅半导体器件，其特征在于，所述第一沟槽为第一双级台阶沟槽；
    所述多级台阶沟槽为三级台阶沟槽，所述三级台阶沟槽的深度大于所述第一双级台阶沟槽的深度。
  9. 根据权利要求6所述的碳化硅半导体器件，其特征在于，所述第二耐压掩蔽结构包括位于所述多级台阶沟槽的侧壁、台阶、底部以及开口四周的碳化硅外延层内的掺杂区域。
  10. 根据权利要求6所述的碳化硅半导体器件，其特征在于，所述多级台阶沟槽底部的所述第二绝缘介质层的厚度大于所述多级台阶沟槽中各级沟槽侧壁上的所述第二绝缘介质层的厚度，大于相邻两级沟槽之间台阶上的所述第二绝缘介质层的厚度。
  11. 根据权利要求1所述的碳化硅半导体器件，其特征在于，所述第二耐压掩蔽结构为形成在所述源极区域内的离子注入区域。
  12. 根据权利要求11所述碳化硅半导体器件，其特征在于，所述离子注入区域的注入深度不小于所述第一沟槽的深度。
  13. 一种如权利要求1-12任一项所述碳化硅半导体器件的制作方法，其特征在于，所述制作方法包括：
    提供一外延片，所述外延片包括碳化硅外延层，所述碳化硅外延层具有相对的第一表面和第二表面，所述第一表面包括栅极区域以及位于所述栅极区域两侧的源极区域；
    在所述栅极区域形成第一沟槽；
    基于所述第一沟槽，在所述碳化硅外延层内形成第一耐压掩蔽结构；
    在所述第一沟槽内形成栅极结构；
    在所述栅极结构的表面上形成金属栅极，在所述源极区域的表面上形成金属源极；
    其中，所述源极区域的表面内具有第二耐压掩蔽结构；所述第一表面内具有阱区，所述阱区位于所述第一沟槽与所述第二耐压掩蔽结构之间。
  14. 根据权利要求13所述的制作方法，其特征在于，所述第一沟槽为第一双级台阶沟槽；
    在所述源极区域表面内形成有多级台阶沟槽；
    制备所述第一耐压掩蔽结构和所述第二耐压掩蔽结构的方法包括：
    基于所述第一双级台阶沟槽以及第一双级台阶沟槽靠近第一表面一级沟槽侧壁的介质层，对所述第一双级台阶沟槽靠近所述第二表面的一级沟槽的侧壁以及底部进行离子注入，在第一双级台阶沟槽靠近第二表面的一级沟槽侧壁和底部的碳化硅外延层内形成所述第一耐压掩蔽结构；
    基于所述多级台阶沟槽，在所述多级台阶沟槽的底部、各级沟槽的台阶以及侧壁进行离子注入，在所述多级台阶沟槽的底部、各级沟槽的台阶以及侧壁的碳化硅外延层内形成所述第二耐压掩蔽结构。
  15. 根据权利要求13所述的制作方法，其特征在于，所述第一沟槽为第一双级台阶沟槽；所述源极区域的表面内形成有多级台阶沟槽；所述第一双级台阶沟槽以及所述多级台阶沟槽内均填充有多晶硅；所述栅极结构包括所述第一双级台沟槽内所填充的多晶硅；
    所述第一双级台阶沟槽与所填充的多晶硅之间、所述多级台阶沟槽与所填充的多晶硅之间均具有绝缘介质层；所述栅极结构包括所述第一双级台阶沟槽 内填充的多晶硅；
    其中，所述金属栅极位于所述第一双级台阶沟槽所填充的多晶硅的表面上；所述金属源极位于所述多级台阶沟槽所填充的多晶硅的表面上。
  16. 根据权利要求15所述的制作方法，其特征在于，所述第一双级台阶沟槽底部的所述绝缘介质层的厚度大于所述第一双级台阶沟槽中各级沟槽侧壁上的所述绝缘介质层的厚度，大于相邻两级沟槽之间台阶上的所述绝缘介质层的厚度；
    所述多级台阶沟槽底部的所述绝缘介质层的厚度大于所述多级台阶沟槽中各级沟槽侧壁上的所述绝缘介质层的厚度，大于相邻两级沟槽之间台阶上的所述绝缘介质层的厚度。
  17. 根据权利要求16所述的制作方法，其特征在于，所述多级台阶沟槽为第二双级台阶沟槽，所述第二双级台阶沟槽与所述第一双级台阶沟槽的深度相同；
    或，所述多级台阶沟槽为三级台阶沟槽，所述三级台阶沟槽的深度大于所述第一双级台阶沟槽的深度。
  18. 根据权利要求13所述的制作方法，其特征在于，形成所述第二耐压掩蔽结构的方法包括：
    通过离子注入方法，在所述源极区域形成离子注入区域，作为所述第二耐压掩蔽结构；
    所述离子注入区域的注入深度不小于所述第一沟槽的深度。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117912957A (zh) * 2024-03-18 2024-04-19 泰科天润半导体科技（北京）有限公司 一种低体二极管压降的碳化硅超结沟槽栅mosfet的制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069042A (ja) * 2001-08-29 2003-03-07 Denso Corp 炭化珪素半導体装置及びその製造方法
US20170092715A1 (en) * 2013-03-13 2017-03-30 Cree, Inc. Field Effect Transistor Devices with Buried Well Protection Regions
CN109768091A (zh) * 2019-03-13 2019-05-17 中国科学院微电子研究所 一种双沟槽SS-SiC MOSFET结构
CN113488542A (zh) * 2021-06-29 2021-10-08 南瑞联研半导体有限责任公司 一种沟槽型SiC MOSFET器件及其制备方法
CN114678425A (zh) * 2022-04-24 2022-06-28 湖北九峰山实验室 碳化硅半导体器件及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069042A (ja) * 2001-08-29 2003-03-07 Denso Corp 炭化珪素半導体装置及びその製造方法
US20170092715A1 (en) * 2013-03-13 2017-03-30 Cree, Inc. Field Effect Transistor Devices with Buried Well Protection Regions
CN109768091A (zh) * 2019-03-13 2019-05-17 中国科学院微电子研究所 一种双沟槽SS-SiC MOSFET结构
CN113488542A (zh) * 2021-06-29 2021-10-08 南瑞联研半导体有限责任公司 一种沟槽型SiC MOSFET器件及其制备方法
CN114678425A (zh) * 2022-04-24 2022-06-28 湖北九峰山实验室 碳化硅半导体器件及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117912957A (zh) * 2024-03-18 2024-04-19 泰科天润半导体科技（北京）有限公司 一种低体二极管压降的碳化硅超结沟槽栅mosfet的制造方法
CN117912957B (zh) * 2024-03-18 2024-05-28 泰科天润半导体科技（北京）有限公司 一种低体二极管压降的碳化硅超结沟槽栅mosfet的制造方法

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