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WO2021012262A1 - 一种阵列基板和液晶显示器 - Google Patents

一种阵列基板和液晶显示器 Download PDF

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Publication number
WO2021012262A1
WO2021012262A1 PCT/CN2019/097702 CN2019097702W WO2021012262A1 WO 2021012262 A1 WO2021012262 A1 WO 2021012262A1 CN 2019097702 W CN2019097702 W CN 2019097702W WO 2021012262 A1 WO2021012262 A1 WO 2021012262A1
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WO
WIPO (PCT)
Prior art keywords
electrode
line
driving electrode
dummy
driving
Prior art date
Application number
PCT/CN2019/097702
Other languages
English (en)
French (fr)
Inventor
程鸿飞
李盼
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/097702 priority Critical patent/WO2021012262A1/zh
Priority to EP19930173.0A priority patent/EP4006631B1/en
Priority to US16/966,592 priority patent/US11822196B2/en
Priority to CN201990000087.9U priority patent/CN212411168U/zh
Publication of WO2021012262A1 publication Critical patent/WO2021012262A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Definitions

  • the present disclosure relates to the field of display, in particular to an array substrate and a liquid crystal display.
  • LCD displays have broad market applications. LCDs with touch function or touch function are becoming more and more popular due to easier and faster human-computer interaction. In-cell touch screen has the advantages of thinness, increased screen definition and low cost, and has been able to grow steadily and continuously in the high-end display market.
  • the present disclosure provides an array substrate including at least one driving electrode area and at least one sensing electrode area that are alternately arranged in a row direction and are not connected to each other, each of the driving electrode areas and each of the sensing electrode areas respectively includes a first A common electrode and a second common electrode, at least one driving electrode line extending in the row direction continuously passes through the driving electrode regions and the sensing electrode regions alternately arranged in the row direction, and is located at the first of the driving electrode regions
  • the common electrode is connected to the driving electrode line through at least one first via hole, and the second common electrode located in the sensing electrode area is not connected to the driving electrode line, wherein the sensing electrode area further includes at least one line parallel to For the second dummy driving electrode line of the driving electrode line, the second common electrode located in the sensing electrode area is connected to the second dummy driving electrode line through at least one fifth via.
  • the number of the fifth via and the first via are the same.
  • the driving electrode area further includes at least one first dummy driving electrode line parallel to the driving electrode line.
  • the array substrate includes a plurality of pixel units arranged along multiple rows and multiple columns, and a plurality of adjacent rows of the pixel units are provided with one drive electrode line corresponding to the drive electrode line.
  • Each pixel unit in the sensing electrode area of the line is provided with one second dummy driving electrode line.
  • one first dummy driving electrode line is provided in each pixel unit of the driving electrode region that does not include the driving electrode line, and the first dummy driving electrode line is connected to the first dummy driving electrode line.
  • the two dummy driving electrode lines are not connected.
  • the first common electrodes of the adjacent driving electrode regions are not connected along the column direction
  • the second common electrodes of the sensing electrode regions are connected in a single body along the column direction
  • the first The common electrode and the second common electrode adjacent in the row direction are not connected.
  • the first common electrode of each of the driving electrode regions is provided with at least one horizontal dummy sensing electrode line parallel to the driving electrode line in the row direction and arranged in the column direction and aligned with the At least one vertical dummy sensing electrode line connected to the at least one horizontal dummy sensing electrode line, and at least one horizontal line parallel to the driving electrode line along the row direction is provided on the second common electrode of each sensing electrode area
  • the sensing electrode lines and at least one longitudinal sensing electrode line arranged along the column direction and connected to the at least one horizontal sensing electrode line.
  • the array substrate includes a plurality of pixel units arranged along multiple rows and multiple columns, and each of the pixel units in the driving electrode area is provided with one horizontal dummy sensing electrode line, Each row of adjacent pixel units in the driving electrode area is provided with one vertical dummy sensing electrode line, and each pixel unit in the sensing electrode area is provided with one horizontal sensing electrode line, so Each row of adjacent pixel units in the sensing electrode area is correspondingly provided with one longitudinal sensing electrode line.
  • the first common electrode in each of the driving electrode regions is connected to one of the driving electrode lines through two first via holes, and the first common electrode is connected to one of the driving electrode lines in each of the sensing electrode regions.
  • the second common electrode is connected to the second dummy driving electrode line through the two fifth via holes.
  • the two fifth via holes are provided on the second dummy driving electrode lines located on both sides of the driving electrode line.
  • the two second via holes are provided on the second dummy driving electrode line on the same side of the driving electrode line.
  • the first dummy driving electrode line and the second dummy driving electrode line are discontinuous in both the first common electrode region and the second common electrode region.
  • the first dummy driving electrode line and the second dummy driving electrode line are continuous in the driving electrode area and the sensing electrode area.
  • the first dummy driving electrode line and the second dummy driving electrode line are both discontinuous or continuous in the driving electrode area and the sensing electrode area, and the sensing electrode area is larger The size of the driving electrode area in the row direction is small.
  • the horizontal dummy sensing electrode lines and the vertical dummy sensing electrode lines are located on the first common electrode of the driving electrode area and are in direct contact with the first common electrode, and the horizontal sensing The electrode line and the longitudinal sensing electrode line are located on the second common electrode of the sensing electrode area and directly contact the second common electrode.
  • the array substrate includes a plurality of gate lines and a plurality of data lines.
  • the driving electrode lines are in the same layer as the gate lines and are parallel to the gate lines
  • the orthographic projection of the driving electrode lines on the base substrate of the array substrate coincides with the orthographic projection of the horizontal dummy sensing electrode lines in the same row on the base substrate
  • the first dummy driving electrode lines coincide with the
  • the gate lines are in the same layer and parallel to the gate lines
  • the orthographic projection of the first dummy driving electrode lines on the base substrate is the orthographic projection of the horizontal dumb sensing electrode lines in the same row on the base substrate
  • the orthographic projection of the vertical dummy sensing electrode line on the base substrate coincides with the orthographic projection of the data line on the base substrate.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, and in the sensing electrode area, the driving electrode lines are in the same layer as the gate lines and are parallel to the gate lines,
  • the orthographic projection of the drive electrode line on the base substrate coincides with the orthographic projection of the horizontal sensing electrode line in the same row on the base substrate, and the second dummy drive electrode line is in the same layer as the gate line
  • the orthographic projection of the second dummy drive electrode line on the base substrate coincides with the orthographic projection of the horizontal sensing electrode line in the same row on the base substrate, so
  • the orthographic projection of the longitudinal sensing electrode line on the base substrate coincides with the orthographic projection of the data line on the base substrate.
  • the array substrate includes a plurality of pixel units arranged in multiple rows and multiple columns, and the pixel units including the drive electrode lines in the drive electrode area include:
  • An active layer located on the base substrate
  • the gate line and the driving electrode line located on the gate insulating layer;
  • the data line, the drain electrode and the first auxiliary electrode located on the interlayer insulating layer communicates with one side of the active layer through a second via hole, and the drain electrode is connected to one side of the active layer through a third via hole.
  • the other side of the active layer is in communication, and the first auxiliary electrode is in communication with the driving electrode line through a sixth via;
  • the first common electrode located on the flat layer, the horizontal dumb sensing electrode line and the vertical dumb sensing electrode line are located on the first common electrode and are in direct contact with the first common electrode, the The first common electrode communicates with the first auxiliary electrode through a first via hole;
  • the pixel electrode located on the first insulating layer the pixel electrode communicates with the drain electrode through a fourth via hole.
  • the array substrate includes a plurality of pixel units arranged in multiple rows and multiple columns, and at least one of the pixel units adjacent to the pixel unit including the drive electrode line in the sensing electrode area in the column direction
  • the pixel unit includes:
  • An active layer located on the base substrate
  • the gate line and the second dummy driving electrode line located on the gate insulating layer;
  • the other side of the active layer is connected, and the first auxiliary electrode is connected to the second dummy driving electrode line through a seventh via hole;
  • the second common electrode located on the flat layer, the horizontal sensing electrode line and the vertical sensing electrode line are located on the second common electrode and are in direct contact with the second common electrode, the second The common electrode communicates with the first auxiliary electrode through the fifth via hole;
  • the pixel electrode located on the first insulating layer the pixel electrode communicates with the drain electrode through a fourth via hole.
  • the present disclosure discloses a touch liquid crystal display including the above-mentioned array substrate.
  • FIG. 1 is a schematic plan view of a touch electrode of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of another touch electrode of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic plan view of a pixel structure of a driving electrode region of an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional view of the driving electrode area of the array substrate along the line AA' according to an embodiment of the present disclosure
  • FIG. 5 is a schematic plan view of a pixel structure of a sensing electrode area of an array substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional view of the sensing electrode area of the array substrate along line AA' according to an embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional view of the sensing electrode area of the array substrate along the line BB' according to an embodiment of the present disclosure
  • FIG. 8 is a schematic plan view of touch electrodes of an array substrate according to another embodiment of the present disclosure.
  • FIG. 9 is a schematic plan view of a pixel structure of a driving electrode region of an array substrate according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic plan view of a pixel structure of a sensing electrode area of an array substrate according to another embodiment of the present disclosure.
  • FIG. 11 is a schematic plan view of touch electrodes of an array substrate according to still another embodiment of the present disclosure.
  • the array substrate is provided with common electrodes, and at least some of the common electrodes also have the function of touch electrodes. It is used as a touch electrode during an action, but only as a common electrode when no touch action is received.
  • the common electrode area for providing the touch driving function is called the driving electrode area
  • the common electrode area that can provide the touch sensing function is called the sensing electrode area.
  • the common electrode in the driving electrode area is called the first common electrode
  • the common electrode in the sensing electrode area is called the second common electrode.
  • the first common electrode in the driving electrode area and the electrode lines on it are called driving electrodes
  • the second common electrode in the sensing electrode area and the electrode lines on it are called sensing electrodes.
  • a plurality of first common electrodes 81 and second sensing electrodes 82 that are alternately arranged in the row direction and not connected are distributed on the array substrate. Among them, the adjacent first common electrodes 81 are not connected in the column direction, and the second common electrodes 82 are not connected in the column direction. The direction is uninterrupted.
  • the array substrate is divided into a plurality of driving electrode regions 810 and sensing electrode regions 820 arranged alternately along the row direction.
  • the sensing electrode area 820 is provided with sensing electrode lines on the second common electrode 82.
  • the sensing electrode lines include a horizontal sensing electrode line 821 and a vertical sensing electrode line 822, which are connected to each other.
  • the first common electrode 81 of the driving electrode area 810 is correspondingly provided with dumb sensing electrode lines.
  • the electrode lines include a horizontal dummy sensing electrode line 811 and a vertical dummy sensing electrode line 812 connected to each other. Further, since the connection of the driving electrode line 83 and the first common electrode 81 in the driving electrode area will also affect the electric field arrangement of the array substrate, correspondingly, a first dummy is also provided in the driving electrode area 810 and the sensing electrode area 820 respectively.
  • the driving electrode lines 841 and the second dummy driving electrode lines 842, the driving electrode lines 83, the first dummy driving electrode lines 841 and the second dummy driving electrode lines 842 are arranged in the same layer as the gate lines 4.
  • the driving electrode line 83 communicates with the first common electrode 81 through the via hole, the existence of the via hole changes the electric field arrangement of the array substrate.
  • a via connection is provided in the sensing electrode area 820 accordingly.
  • the first common electrode 81 and the horizontal dummy sensing electrode lines 811 and the vertical dummy sensing electrode lines 812 located thereon are called driving electrodes
  • the second common electrode 82 and the horizontal sensing electrode lines 821 and 812 located thereon are called driving electrodes.
  • the longitudinal sensing electrode lines 822 are called sensing electrodes.
  • the vertical dummy sensing electrode lines 812 and the horizontal dummy sensing electrode lines 811 are arranged in the same layer as the vertical sensing electrode lines 822 and the horizontal sensing electrode lines 821.
  • the longitudinal dumb sensing electrode lines 812 and the transverse dumb sensing electrode lines 811 of the driving electrode area 810 are not connected to the longitudinal sensing electrode lines 822 and the transverse sensing electrode lines 821 of the sensing electrode area 820, and the longitudinal dumb sensing of the driving electrode area 810 in the column direction
  • the electrode lines 812 and the horizontal dummy sensing electrode lines 811 are not connected to the vertical dummy sensing electrode lines 812 and the horizontal dummy sensing electrode lines 811 of the adjacent driving electrode regions 810.
  • the driving electrode lines 83 of the driving electrode area 810 and the sensing electrode area 820 are connected to each other in the row direction.
  • the first dummy driving electrode line 841 of the driving electrode area 810 and the second dummy driving electrode line 842 of the sensing electrode area 820 are not connected.
  • the array substrate includes a plurality of pixel units arranged along multiple rows and multiple columns.
  • a plurality of data lines are arranged along the column direction between each column of pixel units, and a plurality of data lines are arranged along the row direction between each row of pixel units.
  • the driving electrode lines and the gate lines are located on the same layer and are parallel to each other, but their orthographic projections on the base substrate do not overlap.
  • the row direction refers to the direction in which the gate lines extend
  • the column direction refers to the direction in which the data lines extend.
  • the sensing electrode region 820 has a smaller size in the row direction than the driving electrode region 810, that is, the number of pixel units included in the sensing electrode region 820 in the row direction is greater than that of the driving electrode region 810 in the row direction.
  • the number of pixel units included is small.
  • a plurality of rows of adjacent pixel units are correspondingly provided with a driving electrode line 83, and each pixel unit in the sensing electrode area that does not include the driving electrode line is provided with a second dummy driving electrode line 842.
  • a first dummy driving electrode line 841 is provided in each pixel unit of the driving electrode area 810 that does not include the driving electrode line 83. The first dummy driving electrode line 841 and the second dummy driving electrode line 842 are not connected.
  • Each pixel unit in the driving electrode area 810 is provided with a horizontal dummy sensing electrode line 811, and every few columns of adjacent pixel units in the driving electrode area 810 are provided with a vertical dummy sensing electrode line 812 correspondingly.
  • the horizontal dummy sensing electrode lines 811 are parallel to the driving electrode lines 83, the horizontal dummy sensing electrode lines 811 of adjacent pixel units in the row direction can be connected, and the vertical dummy sensing electrode lines 812 are arranged along the column direction to sense the horizontal dummy in each row.
  • the electrode wires 811 are connected.
  • Multiple vertical dummy sensing electrode lines 812 of each driving electrode region 810 may be arranged along the column direction.
  • the interval between the adjacent vertical dummy sensing electrode lines 812 in the driving electrode area 810 is the same as the interval between the adjacent vertical sensing electrode lines 822 in the adjacent sensing electrode area 820 to obtain a balanced electric field.
  • the vertical dummy sensing electrode lines 812 in each driving electrode region 810 along each column direction may be continuous, but the vertical dummy sensing electrode lines 812 in the same column as the driving electrode regions 810 adjacent in the column direction are not connected.
  • Each pixel unit of the sensing electrode area 820 is provided with a horizontal sensing electrode line 821, the horizontal sensing electrode line 821 is parallel to the driving electrode line 83, and a plurality of longitudinal sensing electrode lines are arranged in the column direction of the sensing electrode area 820 822 is connected to the horizontal sensing electrode line 821, and each adjacent pixel unit of the sensing electrode area 820 is provided with a vertical sensing electrode line 822.
  • the longitudinal sensing electrode lines 822 in each column are continuous. In some embodiments, the interval between the longitudinal sensing electrode lines 822 adjacent to the sensing electrode region 820 is the same as the interval between the longitudinal dummy sensing electrode lines 812 adjacent to the driving electrode region 810 to obtain a balanced electric field.
  • the first common electrode 81 is connected to the driving electrode line 83 through the first via 01, and the first via 01 includes the lower half of the first via.
  • the portion 011 and the upper half portion 012 of the first via hole, the lower half portion 011 of the first via hole passes through the interlayer insulating layer 5, and the upper half portion 012 of the first via hole passes through the flat layer 7.
  • the driving electrode line 83 is located on the gate line layer of the pixel unit and is parallel to the gate line 4.
  • the orthographic projection of the driving electrode line 83 on the base substrate 1 of the array substrate is the same as the horizontal direction of the same row.
  • the orthographic projections of the dummy sensing electrode lines 811 on the base substrate 1 coincide, the first dummy driving electrode lines 841 are also located on the gate line layer of the pixel unit, and the first dummy driving electrode lines 841 are on the base substrate 1.
  • the projection coincides with the orthographic projection of the horizontal dumb sensing electrode lines 811 in the same row on the base substrate 1, and the orthographic projection of the longitudinal dumb sensing electrode lines 812 on the base substrate coincides with the orthographic projection of the data line 6 on the base substrate 1. .
  • the driving electrode line 83 is not connected to the second common electrode 82 in the sensing electrode area 820, the second dummy driving electrode line 842 is connected to the second common electrode 82 through the fifth via 05, and the fifth via 05 includes a fifth via lower half 051 and a fifth via upper half 052, the fifth via lower half 051 passes through the interlayer insulating layer 5, and the fifth via upper half 052 passes through the flat layer 7.
  • the driving electrode line 83 is located on the gate line layer of the pixel unit and parallel to the gate line 4, and the orthographic projection of the driving electrode line 83 on the base substrate 1 is the same as that of the same row.
  • the orthographic projections of the horizontal sensing electrode lines 821 on the base substrate 1 coincide, the second dummy driving electrode lines 842 are located on the gate line layer of the pixel unit, and the orthographic projections of the second dummy driving electrode lines 842 on the base substrate 1 It coincides with the orthographic projection of the horizontal sensing electrode lines 821 in the same row on the base substrate 1, and the orthographic projection of the longitudinal sensing electrode lines 822 on the base substrate 1 coincides with the orthographic projection of the data lines 6 on the base substrate 1.
  • the sensing electrode area 820 and the adjacent drive electrode area 810 have a similar circuit arrangement, so that the array substrate can be driven
  • the driving electrodes of the electrode region 810 and the sensing electrodes of the sensing electrode region 820 generate similar electric fields, so that the display of the array substrate is more uniform.
  • the common electrode in the driving electrode area is also provided with horizontal dummy sensing electrode lines 811 and Longitudinal dummy sensing electrode line 812.
  • the present disclosure can obtain a more uniform electric field in the driving electrode area and the sensing electrode area, minimize the influence of the sensing electrode on the electric field of the array substrate, and improve the display quality.
  • the first dummy driving electrode lines of the driving electrode region and the second dummy driving electrode lines of the sensing electrode region are not connected to each other, and the first dummy driving electrode lines of adjacent driving electrode regions in the column direction are not connected to each other.
  • the first dummy driving electrode lines in the driving electrode area and the second dummy driving electrode lines in the sensing electrode area are respectively in a floating state.
  • the first dummy driving electrode line in the driving electrode area and the second dummy driving electrode line in the sensing electrode area may be continuous or discontinuous. 2
  • the first dummy driving electrode line in the driving electrode area or the second dummy driving electrode line in the sensing electrode area is composed of a plurality of sub-parts.
  • the first dummy driving electrode line in the driving electrode area and the second dummy driving electrode line in the sensing electrode area are intermittent.
  • the first dummy driving electrode line in each driving electrode area and the second dummy driving electrode line in the sensing electrode area are equally divided into four parts.
  • FIG. 3 is a plan view of the pixel structure of the driving electrode region in FIG. 1 or FIG. 2
  • FIG. 4 is a cross-sectional view along AA' in FIG.
  • the driving electrode area 810 the pixel electrode 10 is located above the first common electrode 81, the pixel electrode 10 is provided with a slit, and the pixel electrode 10 is connected to the drain 60 of the TFT of the pixel unit through a fourth via hole 04. 04 passes through the first insulating layer 9 and the flat layer 7.
  • the first common electrode 81 and the horizontal dummy sensing electrode lines 811 and the vertical dummy sensing electrode lines 812 located on the driving electrode area 810 are used as driving electrodes.
  • the driving electrode lines 83 are located on the gate line layer, and the first common electrodes 81 pass through the first common electrode 81.
  • the via 01 is connected to the driving electrode line 83, the vertical dummy sensing electrode line 812 and the data line 6 overlap in a direction perpendicular to the base substrate 1, and the horizontal dummy sensing electrode line 811 and the driving electrode line 83 or the first dummy driving electrode line 841 They overlap in the direction perpendicular to the base substrate 1.
  • FIG. 5 is a diagram of the pixel structure of the sensing electrode area in FIG. 1 or FIG. 2.
  • 6 is a cross-sectional view along AA' in FIG. 5
  • FIG. 7 is a cross-sectional view along BB' in FIG.
  • the second common electrode 82 and the longitudinal sensing electrode lines 822 and the transverse sensing electrode lines 821 located thereon serve as sensing electrodes.
  • the longitudinal sensing electrode lines 822 and the data lines 6 overlap in the direction perpendicular to the base substrate 1, and the horizontal sensing electrode lines 821 and the driving electrode lines 83 or the second dummy driving electrode lines 842 in the same line are in the direction perpendicular to the base substrate 1.
  • the driving electrode line 83 is not connected to the second common electrode 82.
  • the second common electrode 82 is connected to the second dummy driving electrode line 842 through the fifth via 05.
  • the pixel unit including the driving electrode line includes: a base substrate 1; an active layer 2 located on the base substrate 1; The gate insulating layer 3 of the source layer 2; the gate line 4 and the driving electrode line 83 on the gate insulating layer 3; the interlayer covering the gate line 4, the driving electrode line 83 and the gate insulating layer 3 Insulating layer 5; the data line 6, the drain 60 and the first auxiliary electrode 61 on the interlayer insulating layer 5.
  • the data line 6 is connected to one side of the active layer 2 through the second via 02, so The drain 60 communicates with the other side of the active layer through the third via 03, the second via 02 passes through the interlayer insulating layer 5 and the gate insulating layer 3, and the third via 03 passes through the interlayer insulating layer. 5 and the gate insulating layer 3.
  • the first auxiliary electrode 61 communicates with the driving electrode line 83 through the lower part 011 of the first via 01; it covers the data line 6, the drain 60, the first auxiliary electrode 61 and The flat layer 7 of the interlayer insulating layer 5; the first common electrode 81 and the horizontal dummy sensing electrode line 811 and the vertical dummy sensing electrode line 812 on the flat layer 7, the horizontal dummy sensing electrode line 811 and the vertical
  • the dummy sensing electrode line 812 is located on the first common electrode 81, and the first common electrode 81 communicates with the first auxiliary electrode 61 through the upper part 012 of the first via 01; covering the first common electrode 81.
  • the pixel unit containing driving electrode lines in the sensing electrode area 820 is different from the pixel unit containing driving electrode lines in the driving electrode area. As shown in FIG. 6, the horizontal sensing electrode lines 821 and the vertical sensing electrodes 822 are located on the second common electrode. On 82, the second common electrode 82 does not communicate with the driving electrode line 83.
  • the pixel unit that does not contain driving electrode lines in the sensing electrode area 820 is different from the pixel unit that contains driving electrode lines in the driving electrode area.
  • the horizontal sensing electrode lines 821 and the vertical sensing electrodes 822 are located in the second common On the electrode 82, the second common electrode 82 communicates with the second auxiliary electrode 62 through the upper half 052 of the fifth via 05, and the second auxiliary electrode 62 communicates with the second dummy driving electrode line through the lower half 051 of the fifth via 051 842 connected.
  • the sensing electrode is connected to the second dummy driving electrode line through the via hole, which can make the common electrode of the driving electrode area of the array substrate and the common electrode of the sensing electrode area generate similar electric fields, and display more uniformly.
  • two vias may be provided in the driving electrode area to communicate with the driving electrode line and the first common electrode. Accordingly, two vias are also provided in the sensing electrode area to communicate with the dummy driving electrode line and the second common electrode.
  • Common electrode. 8 is a schematic plan view of the common electrode of the array substrate and the electrode lines located thereon
  • FIG. 9 is a plan view of the pixel structure of the driving electrode area of the array substrate
  • FIG. 10 is a plan view of the pixel structure of the sensing electrode area of the array substrate.
  • the driving electrode line 83 is connected to the first common electrode 81 through the two first vias 01, and in the adjacent sensing electrode area 820, at both sides of the driving electrode line 83
  • the second dummy driving electrode lines 842 are respectively provided with a fifth via 05 to communicate with the second dummy driving electrode lines 842 and the second common electrode 82.
  • two vias may be provided in the driving electrode area to communicate with the driving electrode line and the first common electrode. Accordingly, two vias are also provided in the sensing electrode area to communicate with the dummy driving electrode line and the second common electrode.
  • FIG. 11 is a plan view of touch electrodes of the array substrate.
  • the driving electrode line 83 is connected to the first common electrode 81 through two first vias 01.
  • the two fifth vias may only be provided
  • the second dummy driving electrode line 842 on one side of the driving electrode line 83 is not provided with a via hole on the second dummy driving electrode line 842 on the other side.
  • the fifth via hole communicates the second dummy driving electrode line 842 and the second common electrode 82.
  • the grid, data lines, driving electrode lines, dumb driving electrode lines, sensing electrode lines, and dumb sensing electrode lines can all be made of Cu, Al, Mo, Ti, Cr, W and other metal materials, and these
  • the alloy preparation of the material can be either a single-layer structure or a multilayer structure, such as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, MoTi ⁇ Cu.
  • the gate insulating layer, the interlayer insulating layer and the first insulating layer can all be silicon nitride or silicon oxide; the gate insulating layer can be a single-layer structure, and the gate insulating layer can also be a multi-layer structure, such as silicon oxide ⁇ nitrogen Silicon.
  • the flat layer can be made of resin material.
  • the active layer can be made of low-temperature polysilicon. ITO can be used for the pixel electrode and the common electrode.
  • the present disclosure also provides a liquid crystal display, which uses the array substrate of the above-mentioned embodiment.

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Abstract

一种阵列基板，包括沿行方向交替排列且彼此不相连的至少一个驱动电极区（810）和至少一个感应电极区（820），每个驱动电极区（810）和每个感应电极区（820）分别包含一个第一公共电极（81）和一个第二公共电极（82），至少一条驱动电极线（83）连续穿过沿行方向交替排列的驱动电极区（810）和感应电极区（820），位于驱动电极区（810）的第一公共电极（81）通过至少一个第一过孔（01）与驱动电极线（83）连接，位于感应电极区（820）的第二公共电极（82）与驱动电极线（83）不连接，其中，感应电极区（820）还包括至少一条平行于驱动电极线（83）的第二哑驱动电极线（842），位于感应电极区（820）的第二公共电极（82）通过至少一个第五过孔（05）与第二哑驱动电极线（842）连接，从而使驱动电极区（810）的第一公共电极（81）和感应电极区（820）的第二公共电极（82）产生的电场相似，显示更为均匀。

Description

一种阵列基板和液晶显示器 技术领域
本公开涉及显示领域，尤其涉及一种阵列基板和一种液晶显示器。
背景技术
LCD显示器具有广阔的市场应用。具有触控功能或者触摸功能的LCD因人机交互更为简便快捷而变得越来越普及。In-cell触摸显示屏具有轻薄、屏幕清晰度增加和成本低的优点，在高端显示器市场得以稳步持续增长。
发明内容
本公开提供一种阵列基板，包括沿行方向交替排列且彼此不相连的至少一个驱动电极区和至少一个感应电极区，每个所述驱动电极区和每个所述感应电极区分别包含一个第一公共电极和一个第二公共电极，至少一条沿行方向延伸的驱动电极线连续穿过沿行方向交替排列的所述驱动电极区和所述感应电极区，位于所述驱动电极区的第一公共电极通过至少一个第一过孔与所述驱动电极线连接，位于所述感应电极区的第二公共电极与所述驱动电极线不连接，其中，所述感应电极区还包括至少一条平行于所述驱动电极线的第二哑驱动电极线，位于所述感应电极区的所述第二公共电极通过至少一个第五过孔与所述第二哑驱动电极线连接。
在一些实施例中，所述第五过孔和所述第一过孔的数量相同。
在一些实施例中，所述驱动电极区还包括至少一条平行于所述驱动电极线的第一哑驱动电极线。
在一些实施例中，所述阵列基板包括沿多行多列排布的多个像素单元，多行相邻的所述像素单元对应设有一条所述驱动电极线，在不包含所述驱动电极线的所述感应电极区的每个所述像素单元内均设有一条所述第二哑驱动电极线。
在一些实施例中，在不包含所述驱动电极线的驱动电极区的每个所述像素单元内设有一条所述第一哑驱动电极线，所述第一哑驱动电极线与所述第二哑驱动电极线不连接。
在一些实施例中，相邻的所述驱动电极区的所述第一公共电极沿列方向不连接， 所述感应电极区的所述第二公共电极沿列方向连成一体，所述第一公共电极和行方向相邻的所述第二公共电极不连接。
在一些实施例中，在每个所述驱动电极区的所述第一公共电极上设有沿行方向平行于所述驱动电极线的至少一条横向哑感应电极线和沿列方向排列且与所述至少一条横向哑感应电极线连接的至少一条纵向哑感应电极线，在每个所述感应电极区的所述第二公共电极上设置有沿行方向平行于所述驱动电极线的至少一条横向感应电极线和沿列方向排列且与所述至少一条横向感应电极线连接的至少一条纵向感应电极线。
在一些实施例中，所述阵列基板包括沿多行多列排布的多个像素单元，在所述驱动电极区的每个所述像素单元内均设有一条所述横向哑感应电极线，所述驱动电极区的每几列相邻的像素单元对应设有一条所述纵向哑感应电极线，和在所述感应电极区的每一个像素单元内设有一条所述横向感应电极线，所述感应电极区的每几列相邻的像素单元对应设置一条所述纵向感应电极线。
在一些实施例中，在每个所述驱动电极区内所述第一公共电极通过两个所述第一过孔与一条所述驱动电极线连接，在每个所述感应电极区内所述第二公共电极通过两个所述第五过孔与所述第二哑驱动电极线连接。
在一些实施例中，所述两个第五过孔设置在位于所述驱动电极线两侧的所述第二哑驱动电极线之上。
在一些实施例中，所述两个第二过孔设置在所述驱动电极线的同一侧的第二哑驱动电极线上。
在一些实施例中，所述第一哑驱动电极线和所述第二哑驱动电极线在所述第一公共电极区和所述第二公共电极区内均是间断的。
在一些实施例中，所述第一哑驱动电极线和所述第二哑驱动电极线在所述驱动电极区和所述感应电极区内均是连续的。
在一些实施例中，所述第一哑驱动电极线和所述第二哑驱动电极线在所述驱动电极区和所述感应电极区内均是间断的或者连续的，所述感应电极区较所述驱动电极区在行方向的尺寸小。
在一些实施例中，所述横向哑感应电极线和所述纵向哑感应电极线位于所述驱动电极区的所述第一公共电极上且与所述第一公共电极直接接触，所述横向感应电极线和所述纵向感应电极线位于所述感应电极区的所述第二公共电极上且与所述第 二公共电极直接接触。
在一些实施例中，所述阵列基板包括多个栅线和多个数据线，在所述驱动电极区内，所述驱动电极线与所述栅线同层且与所述栅线相平行，所述驱动电极线在所述阵列基板的衬底基板上的正投影与同一行的所述横向哑感应电极线在衬底基板上的正投影重合，所述第一哑驱动电极线与所述栅线同层且与所述栅线相平行，所述第一哑驱动电极线在所述衬底基板上的正投影与同一行的横向哑感应电极线在所述衬底基板上的正投影重合，所述纵向哑感应电极线在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影重合。
在一些实施例中，所述阵列基板包括多个栅线和多个数据线，在所述感应电极区内，所述驱动电极线与所述栅线同层且与所述栅线相平行，所述驱动电极线在所述衬底基板上的正投影与同一行的所述横向感应电极线在衬底基板上的正投影重合，所述第二哑驱动电极线与所述栅线同层且与所述栅线相平行，所述第二哑驱动电极线在所述衬底基板上的正投影与同一行的所述横向感应电极线在所述衬底基板上的正投影重合，所述纵向感应电极线在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影重合。
在一些实施例中，所述阵列基板包括多个多行多列排布的像素单元，在所述驱动电极区包含所述驱动电极线的像素单元包括：
衬底基板；
位于所述衬底基板上的有源层；
包覆所述有源层的栅极绝缘层；
位于所述栅极绝缘层上的栅线和所述驱动电极线；
包覆所述栅线、所述驱动电极线和所述栅极绝缘层的层间绝缘层；
位于所述层间绝缘层上的数据线、漏极和第一辅助电极，所述数据线通过第二过孔与所述有源层的一侧连通，所述漏极通过第三过孔与所述有源层的另一侧连通，所述第一辅助电极通过第六过孔与所述驱动电极线连通；
包覆所述数据线、所述漏极、所述第一辅助电极和所述层间绝缘层的平坦层；
位于所述平坦层上的所述第一公共电极，所述横向哑感应电极线和所述纵向哑感应电极线位于所述第一公共电极上且与所述第一公共电极直接接触，所述第一公共电极通过第一过孔与所述第一辅助电极连通；
包覆所述第一公共电极、所述横向哑感应电极线、所述纵向哑感应电极线和所 述平坦层的第一绝缘层；
位于所述第一绝缘层上的像素电极，所述像素电极通过第四过孔与所述漏极连通。
在一些实施例中，阵列基板包括多个多行多列排布的像素单元，在所述感应电极区与包含所述驱动电极线的所述像素单元在列方向上相邻的至少一个所述像素单元包括：
衬底基板；
位于所述衬底基板上的有源层；
包覆所述有源层的栅极绝缘层；
位于所述栅极绝缘层上的栅线和所述第二哑驱动电极线；
包覆所述栅线、所述第二哑驱动电极线和所述栅极绝缘层的层间绝缘层；
位于所述层间绝缘层上的数据线、漏极和第一辅助电极，所述数据线通过第二过孔与所述有源层的一侧连通，所述漏极通过第三过孔与所述有源层的另一侧连通，所述第一辅助电极通过第七过孔与所述第二哑驱动电极线连通；
包覆所述数据线、所述漏极、所述第一辅助电极和所述层间绝缘层的平坦层；
位于所述平坦层上的所述第二公共电极，所述横向感应电极线和所述纵向感应电极线位于所述第二公共电极上且与所述第二公共电极直接接触，所述第二公共电极通过第五过孔与所述第一辅助电极连通；
包覆所述第二公共电极、所述横向感应电极线、所述纵向感应电极线和所述平坦层的第一绝缘层；
位于所述第一绝缘层上的像素电极，所述像素电极通过第四过孔与所述漏极连通。
根据本公开的另一方面，本公开披露一种触控液晶显示器，包含上述的阵列基板。
附图说明
图1为根据本公开一实施例的阵列基板的一触控电极平面示意图；
图2为根据本公开一实施例的阵列基板的又一触控电极的平面示意图；
图3为根据本公开一实施例的阵列基板的驱动电极区的像素结构平面示意图；
图4为根据本公开一实施例的阵列基板的驱动电极区沿AA’线的剖面示意图；
图5为根据本公开一实施例的阵列基板的感应电极区的像素结构平面示意图；
图6为根据本公开一实施例的阵列基板的感应电极区沿AA’线的剖面示意图；
图7为根据本公开一实施例的阵列基板的感应电极区沿BB’线的剖面示意图；
图8为根据本公开又一实施例的阵列基板的触控电极平面示意图；
图9为根据本公开又一实施例的阵列基板的驱动电极区的像素结构平面示意图；
图10为根据本公开又一实施例的阵列基板的感应电极区的像素结构平面示意图；
图11为根据本公开再一实施例的阵列基板的触控电极的平面示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施例对本公开作进一步详细描述。
下面描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。
根据本公开的一些实施例，对于具有触控功能的显示面板，其阵列基板设有公共电极，其中至少部分公共电极同时也具有触控电极的功能，也就是说，这些电极在接收到触控动作时用作触控电极，而未接收到触控动作时仅用作公共电极。为便于区分，本公开中将用于提供触控驱动功能的公共电极区域称为驱动电极区，将能够提供触控感应功能的公共电极区域称为感应电极区。将驱动电极区的公共电极称为第一公共电极，将感应电极区的公共电极称为第二公共电极。将驱动电极区的第一公共电极及位于其上的电极线称为驱动电极，将感应电极区的第二公共电极及位于其上的电极线称为感应电极。
下面，参照图1，对阵列基板的公共电极及位于其上的电极线的设置形式进行详细说明。多个沿行方向交替排列且不连接的第一公共电极81和第二感应电极82分布于阵列基板上，其中相邻的第一公共电极81沿列方向不连接，第二公共电极82沿列方向不间断。相应地，阵列基板被划分为多个沿行方向交替排列的驱动电极区810和感应电极区820。沿行方向，设有驱动电极线83，驱动电极线83 连续穿过沿行方向交替排列的驱动电极区810和感应电极区820。感应电极区820内设置有位于第二公共电极82上的感应电极线，感应电极线包括横向感应电极线821和纵向感应电极线822，两者相互连接。同时，为减少感应电极区内的感应电极对电信号的影响而能够在阵列基板中获得均衡的电场，在驱动电极区810的第一公共电极81上相应地设有哑感应电极线，哑感应电极线包括彼此连接的横向哑感应电极线线811和纵向哑感应电极线812。进一步，由于在驱动电极区驱动电极线83与第一公共电极81连接也会对阵列基板的电场排布带来影响，相应地在驱动电极区810和感应电极区820分别还设有第一哑驱动电极线841和第二哑驱动电极线842，驱动电极线83、第一哑驱动电极线841和第二哑驱动电极线842与栅线4同层设置。由于驱动电极线83通过过孔与第一公共电极81连通，过孔的存在改变了阵列基板的电场排布，为保证阵列基板的电场更为均衡，相应地在感应电极区820设置过孔连接第二哑驱动电极线842与第二公共电极82。
在本公开中，第一公共电极81和位于其上的横向哑感应电极线811以及纵向哑感应电极线812被称为驱动电极，第二公共电极82和位于其上的横向感应电极线821和纵向感应电极线822被称为感应电极。纵向哑感应电极线812和横向哑感应电极线811与纵向感应电极线822和横向感应电极线821同层设置。驱动电极区810的纵向哑感应电极线812和横向哑感应电极线811与感应电极区820的纵向感应电极线822和横向感应电极线821不连接，并且列方向上驱动电极区810的纵向哑感应电极线812和横向哑感应电极线811与相邻驱动电极区810的纵向哑感应电极线812和横向哑感应电极线811不连接。驱动电极区810和感应电极区820的驱动电极线83沿行方向彼此相连。驱动电极区810的第一哑驱动电极线841和感应电极区820的第二哑驱动电极线842不连接。
从像素结构的角度来看，阵列基板包括沿多行多列排布的多个像素单元，在各列像素单元之间沿列方向设置多条数据线，在各行像素单元之间沿行方向设置多条栅线，相邻多行像素单元对应设置一条驱动电极线，驱动电极线与栅线位于同一层且相互平行，但它们在衬底基板上的正投影不重合。
在本公开中，行方向是指栅线延伸的方向，列方向是指数据线延伸的方向。
在一些实施例中，所述感应电极区820较所述驱动电极区810在行方向的尺寸小，即感应电极区820沿行方向所包含的像素单元的数量比驱动电极区810沿行方向所包含的像素单元的数量少。
多行相邻的像素单元对应设有一条驱动电极线83，在不包含驱动电极线的感应电极区的每个像素单元内均设有一条第二哑驱动电极线842。在不包含所述驱动电极线83的驱动电极区810的每个像素单元内设有一条第一哑驱动电极线841。所述第一哑驱动电极线841与所述第二哑驱动电极线842不连接。
在驱动电极区810的每个所述像素单元内均设有一条横向哑感应电极线811，所述驱动电极区810的每几列相邻的像素单元对应设有一条纵向哑感应电极线812。其中，横向哑感应电极线811平行于驱动电极线83，沿行方向相邻的像素单元的横向哑感应电极线811可以连接，沿列方向设置纵向哑感应电极线812将每行的横向哑感应电极线811连接起来。每个驱动电极区810的纵向哑感应电极线812沿列方向可以设置多条。在一些实施例中，驱动电极区810内相邻的纵向哑感应电极线812之间的间隔与相邻感应电极区820内相邻的纵向感应电极线822间隔相同设置以获得均衡的电场。沿每一列方向在每个驱动电极区810内纵向哑感应电极线812可以是连续的，但与沿列方向相邻的驱动电极区810同一列的纵向哑感应电极线812不连接。
在所述感应电极区820的每一个像素单元内均设有一条横向感应电极线821，横向感应电极线821与驱动电极线83平行，在感应电极区820的列方向设置多条纵向感应电极线822来连接横向感应电极线821，所述感应电极区820的每几列相邻的像素单元对应设有一条纵向感应电极线822。每一列的纵向感应电极线822是连续的。在一些实施例中，感应电极区820相邻的纵向感应电极线822的间隔与驱动电极区810内相邻的纵向哑感应电极线812的间隔相同以获得均衡的电场。
根据本公开的一个实施例，参照图3和4，在驱动电极区810内第一公共电极81通过第一过孔01与驱动电极线83连接，第一过孔01包括第一过孔下半部分011和第一过孔上半部分012，第一过孔下半部分011穿过层间绝缘层5，第一过孔上半部分012穿过平坦层7。在驱动电极区810内，驱动电极线83位于像素单元的栅线层上且与栅线4相平行，所述驱动电极线83在阵列基板的衬底基板1上的正投影与同一行的横向哑感应电极线811在衬底基板1上的正投影重合，第一哑驱动电极线841也位于所述像素单元的栅线层上，第一哑驱动电极线841在衬底基板1上的正投影与同一行的横向哑感应电极线811在衬底基板1上的正投影重合，纵向哑感应电极线812在衬底基板上的正投影与数据线6在衬底基板1上的正投影重合。
参照图5-7，在感应电极区820内驱动电极线83不与第二公共电极82连接， 第二哑驱动电极线842通过第五过孔05与第二公共电极82连接，第五过孔05包括第五过孔下半部分051和第五过孔上半部分052，第五过孔下半部分051穿过层间绝缘层5，第五过孔上半部分052穿过平坦层7。在感应电极区820内，驱动电极线83位于所述像素单元的栅线层上且与所述栅线4相平行，所述驱动电极线83在衬底基板1上的正投影与同一行的横向感应电极线821在衬底基板1上的正投影重合，第二哑驱动电极线842位于所述像素单元的栅线层上，第二哑驱动电极线842在衬底基板1上的正投影与同一行的横向感应电极线821在衬底基板1上的正投影重合，纵向感应电极线822在衬底基板1上的正投影和数据线6在衬底基板1上的正投影重合。
由于在第二公共电极82与第二哑驱动电极线842之间设有第五过孔05，感应电极区820与邻接的驱动电极区810具有相近的电路排布，从而可以使阵列基板的驱动电极区810的驱动电极和感应电极区820的感应电极产生相似的电场，使阵列基板的显示更为均匀。同时，为了尽可能减小感应电极区820内的横向感应电极线821和纵向感应电极线822对电场的影响，在驱动电极区内的公共电极上也相应地设有横向哑感应电极线811和纵向哑感应电极线812。通过哑感应电极线和哑驱动电极线的设置，本公开在驱动电极区和感应电极区可以获得更加均匀的电场，最大限定地减小感应电极对阵列基板电场的影响，提高显示质量。
在一些实施例中，驱动电极区的第一哑驱动电极线和感应电极区的第二哑驱动电极线互不连接，列方向上相邻驱动电极区的第一哑驱动电极线互不连接。驱动电极区的第一哑驱动电极线和感应电极区的第二哑驱动电极线分别处于悬浮状态。驱动电极区的第一哑驱动电极线和感应电极区的第二哑驱动电极线可以是连续的，也可以是断续的。参照图2，位于驱动电极区的第一哑驱动电极线或感应电极区的第二哑驱动电极线由多个子部分组成。即，在驱动电极区的第一哑驱动电极线和感应电极区的第二哑驱动电极线是断续的。比如，将每一个驱动电极区的第一哑驱动电极线和感应电极区的第二哑驱动电极线均分为四部分。
下面结合图3-7对驱动电极区和感应电极区的像素结构做出详细说明。图3是图1或图2中驱动电极区的像素结构平面图，图4为沿图3中AA’的剖面图。在驱动电极区810，像素电极10位于第一公共电极81的上方，像素电极10上设置有狭缝，像素电极10通过第四过孔04连接像素单元的TFT的漏极60，第四过孔04穿过第一绝缘层9和平坦层7。驱动电极区810中第一公共电极81和位于其上的横向哑感应 电极线811和纵向哑感应电极线812用作驱动电极，驱动电极线83位于栅线层，第一公共电极81通过第一过孔01连接驱动电极线83，纵向哑感应电极线812与数据线6在垂直于衬底基板1的方向上重叠，横向哑感应电极线811与驱动电极线83或第一哑驱动电极线841在垂直于衬底基板1的方向上重叠。
图5为图1或图2中感应电极区的像素结构图。图6为沿图5中AA’的剖面图，图7为沿图5中BB’的剖面图。在感应电极区820中第二公共电极82和位于其上的纵向感应电极线822和横向感应电极线821用作感应电极。纵向感应电极线822与数据线6在垂直于衬底基板1的方向上重叠，同行的横向感应电极线821与驱动电极线83或第二哑驱动电极线842在垂直于衬底基板1的方向上重叠。驱动电极线83不与第二公共电极82连接。在感应电极区820第二公共电极82通过第五过孔05与第二哑驱动电极线842连接。
更为具体地，在驱动电极区810，如图4所示，包含驱动电极线的像素单元包括：衬底基板1；位于所述衬底基板1上的有源层2；包覆所述有源层2的栅极绝缘层3；位于所述栅极绝缘层3上的栅线4和驱动电极线83；包覆所述栅线4、驱动电极线83和栅极绝缘层3的层间绝缘层5；位于所述层间绝缘层5上的数据线6、漏极60和第一辅助电极61，所述数据线6通过第二过孔02与有源层2的一侧连通，所述漏极60通过第三过孔03与有源层的另一侧连通，第二过孔02穿过层间绝缘层5和栅极绝缘层3，第三过孔03穿过层间绝缘层5和栅极绝缘层3，所述第一辅助电极61通过第一过孔01下半部分011与驱动电极线83连通；包覆所述数据线6、漏极60、第一辅助电极61和所述层间绝缘层5的平坦层7；位于所述平坦层7上的第一公共电极81和横向哑感应电极线811和纵向哑感应电极线812，所述横向哑感应电极线811和纵向哑感应电极线812位于所述第一公共电极81上，所述第一公共电极81通过第一过孔01上半部分012与所述第一辅助电极61连通；包覆所述第一公共电极81、横向哑感应电极线811、纵向哑感应电极线812和所述平坦层7的第一绝缘层9；位于所述第一绝缘层9上的像素电极10，所述像素电极10通过第四过孔04与所述漏极60连通。
在感应电极区820包含驱动电极线的像素单元，与驱动电极区包含驱动电极线的像素单元不同之处为，如图6所示，横向感应电极线821和纵向感应电极822位于第二公共电极82上，第二公共电极82不与驱动电极线83连通。
在感应电极区820不包含驱动电极线的像素单元，与驱动电极区包含驱动电极 线的像素单元不同之处为，如图7所示，横向感应电极线821和纵向感应电极822位于第二公共电极82上，第二公共电极82通过第五过孔05的上半部分052与第二辅助电极62连通，第二辅助电极62通过第五过孔的下半部分051与第二哑驱动电极线842连通。
根据本公开的实施例，感应电极通过过孔连接第二哑驱动电极线，可以使阵列基板的驱动电极区的公共电极和感应电极区的公共电极产生的电场相似，显示时更为均匀。
根据本公开的又一实施例，在驱动电极区可设置两个过孔连通驱动电极线和第一公共电极，相应地，在感应电极区也设置两个过孔连通哑驱动电极线和第二公共电极。参见图8为阵列基板的公共电极和位于其上的电极线的平面示意图，图9为阵列基板的驱动电极区的像素结构的平面图，图10为阵列基板的感应电极区的像素结构平面图。在本实施例中，在驱动电极区810，驱动电极线83通过两个第一过孔01连接第一公共电极81，在相邻的感应电极区820，在位于该驱动电极线83两侧的第二哑驱动电极线842分别设置一个第五过孔05连通第二哑驱动电极线842和第二公共电极82。
根据本发明的另一些实施例，在驱动电极区可设置两个过孔连通驱动电极线和第一公共电极，相应地，在感应电极区也设置两个过孔连通哑驱动电极线和第二公共电极。图11为阵列基板的触控电极平面图。在本实施例中，在驱动电极区810，驱动电极线83通过两个第一过孔01连接第一公共电极81，在相邻的感应电极区820，两个第五过孔可以只设置在位于该驱动电极线83一侧的第二哑驱动电极线842上，另一侧的第二哑驱动电极线842上不设置过孔。第五过孔连通第二哑驱动电极线842和第二公共电极82。
本公开中，栅极、数据线、驱动电极线、哑驱动电极线、感应电极线、哑感应电极线均可以采用Cu，Al，Mo，Ti，Cr，W等金属材料制备，也可以采用这些材料的合金制备，既可以是单层结构，也可以采用多层结构，如Mo\Al\Mo，Ti\Cu\Ti，MoTi\Cu。栅极绝缘层、层间绝缘层和第一绝缘层均可采用氮化硅或氧化硅；栅极绝缘层可以是单层结构，栅极绝缘层也可以是多层结构，例如氧化硅\氮化硅。平坦层 可以采用树脂材料制备。有源层可以采用低温多晶硅制备。像素电极、公共电极可以采用ITO。
根据本公开的另一方面，本公开还提供一种液晶显示器，其采用上述实施例的阵列基板。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
可以理解的是，上述实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限与此。对于本领域的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变化、修改、替换和变型，这些变化、修改、替换和变型也视为本公开的保护范围。

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  1. 一种阵列基板，包括沿行方向交替排列且彼此不相连的至少一个驱动电极区和至少一个感应电极区，每个所述驱动电极区和每个所述感应电极区分别包含一个第一公共电极和一个第二公共电极，至少一条沿行方向延伸的驱动电极线连续穿过沿行方向交替排列的所述驱动电极区和所述感应电极区，位于所述驱动电极区的第一公共电极通过至少一个第一过孔与所述驱动电极线连接，位于所述感应电极区的第二公共电极与所述驱动电极线不连接，其中，所述感应电极区还包括至少一条平行于所述驱动电极线的第二哑驱动电极线，位于所述感应电极区的所述第二公共电极通过至少一个第五过孔与所述第二哑驱动电极线连接。
  2. 根据权利要求1的阵列基板，其中，所述第五过孔和所述第一过孔的数量相同。
  3. 根据权利要求1的阵列基板，其中，所述驱动电极区还包括至少一条平行于所述驱动电极线的第一哑驱动电极线。
  4. 根据权利要求3的阵列基板，其中，所述阵列基板包括沿多行多列排布的多个像素单元，多行相邻的所述像素单元对应设有一条所述驱动电极线，在不包含所述驱动电极线的所述感应电极区的每个所述像素单元内均设有一条所述第二哑驱动电极线。
  5. 根据权利要求4的阵列基板，其中，在不包含所述驱动电极线的驱动电极区的每个所述像素单元内设有一条所述第一哑驱动电极线，所述第一哑驱动电极线与所述第二哑驱动电极线不连接。
  6. 根据权利要求1的阵列基板，其中，相邻的所述驱动电极区的所述第一公共电极沿列方向不连接，所述感应电极区的所述第二公共电极沿列方向连成一体，所述第一公共电极和行方向相邻的所述第二公共电极不连接。
  7. 根据权利要求3所述的阵列基板，其中，在每个所述驱动电极区的所述第一公共电极上设有沿行方向平行于所述驱动电极线的至少一条横向哑感应电极线和沿列方向排列且与所述至少一条横向哑感应电极线连接的至少一条纵向哑感应电极线，在每个所述感应电极区的所述第二公共电极上设置有沿行方向平行于所述驱动电极线的至少一条横向感应电极线和沿列方向排列且与所述至少一条横向感应电极线连接的至少一条纵向感应电极线。
  8. 根据权利要求7所述的阵列基板,其中，所述阵列基板包括沿多行多列排布的多个像素单元，在所述驱动电极区的每个所述像素单元内均设有一条所述横向哑感应电极线，所述驱动电极区的每几列相邻的像素单元对应设有一条所述纵向哑感应电极线，和在所述感应电极区的每一个像素单元内均设有一条所述横向感应电极线，所述感应电极区的每几列相邻的像素单元对应设置一条所述纵向感应电极线。
  9. 根据权利要求1所述的阵列基板，其中，在每个所述驱动电极区内所述第一公共电极通过两个所述第一过孔与所述驱动电极线连接，在每个所述感应电极区内所述第二公共电极通过两个所述第五过孔与所述第二哑驱动电极线连接。
  10. 根据权利要求9所述的阵列基板，其中，所述两个第五过孔分别设置在位于所述驱动电极线两侧的所述第二哑驱动电极线之上。
  11. 根据权利要求9所述的阵列基板，其中，所述两个第五过孔均设置在位于所述驱动电极线的同一侧的所述第二哑驱动电极线之上。
  12. 根据权利要求3所述的阵列基板，其中，所述第一哑驱动电极线和所述第二哑驱动电极线在所述驱动电极区和所述感应电极区内均是间断的。
  13. 根据权利要求3所述的阵列基板，其中，所述第一哑驱动电极线和所述第二哑驱动电极线在所述驱动电极区和所述感应电极区内均是连续的。
  14. 根据权利要求3所述的阵列基板，其中，所述第一哑驱动电极线和所述第二哑驱动电极线在所述驱动电极区和所述感应电极区内均是间断的或者连续的，所述感应电极区较所述驱动电极区在行方向的尺寸小。
  15. 根据权利要求7所述的阵列基板，其中，所述横向哑感应电极线和所述纵向哑感应电极线位于所述驱动电极区的所述第一公共电极上且与所述第一公共电极直接接触，所述横向感应电极线和所述纵向感应电极线位于所述感应电极区的所述第二公共电极上且与所述第二公共电极直接接触。
  16. 根据权利要求7所述的阵列基板，其中，所述阵列基板包括多个栅线和多个数据线，在所述驱动电极区内，所述驱动电极线与所述栅线同层且与所述栅线相平行，所述驱动电极线在所述阵列基板的衬底基板上的正投影与同一行的所述横向哑感应电极线在衬底基板上的正投影重合，所述第一哑驱动电极线与所述栅线同层且与所述栅线相平行，所述第一哑驱动电极线在所述衬底基板上的正投影与同一行的所述横向 哑感应电极线在所述衬底基板上的正投影重合，所述纵向哑感应电极线在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影重合。
  17. 根据权利要求7所述的阵列基板，其中，所述阵列基板包括多个栅线和多个数据线，在所述感应电极区内，所述驱动电极线与所述栅线同层且与所述栅线相平行，所述驱动电极线在所述衬底基板上的正投影与同一行的所述横向感应电极线在衬底基板上的正投影重合，所述第二哑驱动电极线与所述栅线同层且与所述栅线相平行，所述第二哑驱动电极线在所述衬底基板上的正投影与同一行的所述横向感应电极线在所述衬底基板上的正投影重合，所述纵向感应电极线在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影重合。
  18. 根据权利要求7所述的阵列基板，其中，阵列基板包括多个多行多列排布的像素单元，在所述驱动电极区包含所述驱动电极线的像素单元包括：
    衬底基板；
    位于所述衬底基板上的有源层；
    包覆所述有源层的栅极绝缘层；
    位于所述栅极绝缘层上的栅线和所述驱动电极线；
    包覆所述栅线、所述驱动电极线和所述栅极绝缘层的层间绝缘层；
    位于所述层间绝缘层上的数据线、漏极和第一辅助电极，所述数据线通过第二过孔与所述有源层的一侧连通，所述漏极通过第三过孔与所述有源层的另一侧连通，所述第一辅助电极通过第一过孔下半部分与所述驱动电极线连通；
    包覆所述数据线、所述漏极、所述第一辅助电极和所述层间绝缘层的平坦层；
    位于所述平坦层上的所述第一公共电极，所述横向哑感应电极线和所述纵向哑感应电极线位于所述第一公共电极上且与所述第一公共电极直接接触，所述第一公共电极通过第一过孔上半部分与所述第一辅助电极连通；
    包覆所述第一公共电极、所述横向哑感应电极线、所述纵向哑感应电极线和所述平坦层的第一绝缘层；
    位于所述第一绝缘层上的像素电极，所述像素电极通过第四过孔与所述漏极连通。
  19. 根据权利要求7所述的阵列基板，其中，阵列基板包括多个多行多列排布的像素单元，在所述感应电极区与包含所述驱动电极线的所述像素单元在列方向上相邻的至少一个所述像素单元包括：
    衬底基板；
    位于所述衬底基板上的有源层；
    包覆所述有源层的栅极绝缘层；
    位于所述栅极绝缘层上的栅线和所述第二哑驱动电极线；
    包覆所述栅线、所述第二哑驱动电极线和所述栅极绝缘层的层间绝缘层；
    位于所述层间绝缘层上的数据线、漏极和第二辅助电极，所述数据线通过第二过孔与所述有源层的一侧连通，所述漏极通过第三过孔与所述有源层的另一侧连通，所述第二辅助电极通过第五过孔下半部分与所述第二哑驱动电极线连通；
    包覆所述数据线、所述漏极、所述第二辅助电极和所述层间绝缘层的平坦层；
    位于所述平坦层上的所述第二公共电极，所述横向感应电极线和所述纵向感应电极线位于所述第二公共电极上且与所述第二公共电极直接接触，所述第二公共电极通过第五过孔上班部分与所述第二辅助电极连通；
    包覆所述第二公共电极、所述横向感应电极线、所述纵向感应电极线和所述平坦层的第一绝缘层；
    位于所述第一绝缘层上的像素电极，所述像素电极通过第四过孔与所述漏极连通。
  20. 一种触控液晶显示器，包含权利要求1-19任一项所述的阵列基板。
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