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WO2018040560A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2018040560A1
WO2018040560A1 PCT/CN2017/079709 CN2017079709W WO2018040560A1 WO 2018040560 A1 WO2018040560 A1 WO 2018040560A1 CN 2017079709 W CN2017079709 W CN 2017079709W WO 2018040560 A1 WO2018040560 A1 WO 2018040560A1
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Prior art keywords
line
common electrode
array substrate
electrode
common
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PCT/CN2017/079709
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English (en)
French (fr)
Inventor
龙春平
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京东方科技集团股份有限公司
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Priority to US15/561,185 priority Critical patent/US10203570B2/en
Publication of WO2018040560A1 publication Critical patent/WO2018040560A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/124—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode interdigital
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/128—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode field shaping
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • At least one embodiment of the present disclosure is directed to an array substrate, a display panel, and a display device.
  • In-Plane Switching (IPS) liquid crystal display mode utilizes pixel electrodes and common electrodes in the same plane to form a parallel electric field parallel to the glass surface or electrode surface, so that liquid crystal molecules are deflected in a plane parallel to the glass surface, Display.
  • the IPS pixel structure is provided with a common electrode in the same layer of the pixel electrode, and can form an interdigital electrode shape.
  • At least one embodiment of the present disclosure is directed to an array substrate, a display panel, and a display device.
  • Embodiments of the present disclosure provide an array substrate of a planar conversion liquid crystal mode, which is advantageous for correcting electric field chaos in an edge portion of a sub-pixel, reducing light leakage and color mixing, increasing an aperture ratio of a sub-pixel, and thereby increasing an aperture ratio of the pixel.
  • At least one embodiment of the present disclosure provides an array substrate including a plurality of gate lines, a plurality of data lines, and a plurality of common electrodes disposed on a substrate; the plurality of gate lines extending in a first direction; The plurality of data lines extend in a second direction and are insulated and insulated from the plurality of gate lines, the second direction being different from the first direction; the plurality of common electrodes are arranged along the second direction, a gate line between adjacent two common electrodes, the plurality of common electrodes and the plurality of data lines being insulated from each other, each of the common electrodes including at least one of the data lines being perpendicular to the substrate An overlapping portion having an overlapping portion in a direction of the substrate, wherein the same of the two common electrodes in the second direction has an overlapping portion with an overlapping portion in a direction perpendicular to the substrate substrate There is a space therebetween, and the intersection of the data line and the gate line between the adjacent two common electrodes is located within the interval.
  • At least one embodiment of the present disclosure provides a display panel including any of the array substrates provided by embodiments of the present disclosure.
  • At least one embodiment of the present disclosure provides a display device including any of the display panels provided by embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • 10-substrate substrate 101-gate line; 102-data line; 103-common electrode; 1030-common electrode strip; 1031-overlap; 1032- common electrode connection; 104- common electrode line; 1041-common electrode line Via: 105-pixel electrode; 1050-pixel electrode strip; 106-source; 1061-sub-source; 1062-sub-source; 107-drain; 1071-drain via; 108-active region; - Thin film transistor; 013-spaced; 1-sub-pixel; 0106- ⁇ .
  • the IPS liquid crystal mode In the IPS mode, the IPS liquid crystal mode generally has a low aperture ratio because the thin film transistor and its gate line, the common electrode, and its common electrode line occupy a large wiring area. At the same time, the interconnection of the common electrodes of adjacent sub-pixels causes the electric field of the sub-pixel edge region to be disordered, and light leakage and color mixing are easily generated, thereby further reducing the aperture ratio.
  • Embodiments of the present disclosure provide an array substrate, a display panel, and a display device.
  • the array substrate includes a plurality of gate lines, a plurality of data lines and a plurality of common electrodes disposed on the base substrate; the plurality of gate lines extend along the first direction; the plurality of data lines extend in the second direction, and the plurality of lines
  • the gate lines are crossed and insulated, the second direction is different from the first direction; the plurality of common electrodes are arranged in the second direction, the adjacent two common electrodes have gate lines therebetween, and the plurality of common electrodes and the plurality of data lines are insulated from each other,
  • Each of the common electrodes includes an overlapping portion having an overlapping portion with respect to the at least one data line in a direction perpendicular to the substrate, wherein the same of the two common electrodes in the second direction is perpendicular to the substrate There is a space between the overlapping portions having the overlapping portions in the direction of the substrate, and the intersection of the data lines and the gate
  • the array substrate provided by the embodiment of the present disclosure will be described below with reference to the accompanying drawings.
  • the source, drain, pixel electrode and common electrode in the figure are translucent, so that the relationship of the layers can be clearly indicated.
  • the present embodiment provides an array substrate.
  • the array substrate includes a plurality of gate lines 101 , a plurality of data lines 102 , and a plurality of common electrodes 103 disposed on the substrate substrate 10 .
  • the common electrode of the upper side in Fig. 1 shows a part.
  • a plurality of gate lines 101 extend in a first direction.
  • the plurality of data lines 102 extend in the second direction and are insulated and insulated from the plurality of gate lines 101, and the second direction is different from the first direction.
  • the first direction is a horizontal direction along the paper surface
  • the second direction is a vertical direction along the paper surface
  • the first direction is perpendicular to the second direction
  • the first direction and the second direction are not limited to those shown in the drawing.
  • the plurality of gate lines 101 intersect and are insulated from the plurality of data lines 102, and the plurality of gate lines 101 intersect the plurality of data lines 102 to define the plurality of sub-pixels 1. In the dotted line frame in Fig. 1, there is one sub-pixel 1.
  • a plurality of common electrodes 103 are arranged in the second direction, and two adjacent common electrodes There is a gate line 101 between 103, and a plurality of common electrodes 103 and a plurality of data lines 102 are insulated from each other, and each common electrode 103 includes an overlap with at least one data line 102 having an overlapping portion in a direction perpendicular to the base substrate 10.
  • the two common electrodes 103 adjacent in the second direction have an interval 013 between the overlapping portions 1031 having the overlapping portions of the same data line 102 in the direction perpendicular to the base substrate 10, and the data lines
  • the intersection of 102 and the gate line 101 between the adjacent two common electrodes 103 is located in the interval 013.
  • a gate line 101 is provided between the two adjacent common electrodes 103 as an example. It should be noted that the gate lines 101 between the adjacent two common electrodes 103 may be more than one. This is not limited here.
  • the overlapping portion 1031 has an overlapping portion with a data line 102 in a direction perpendicular to the base substrate 10. For example, when there are a plurality of, for example, two data lines between adjacent two columns of sub-pixels, the overlapping is performed.
  • the portion 1031 may have an overlapping portion with a plurality of data lines 102 between adjacent two columns of sub-pixels in a direction perpendicular to the base substrate 10.
  • the data lines shown in FIG. 1 are linear, but the shape of the data lines is not limited to those shown in the drawings, and may be other shapes such as a polygonal line shape. Accordingly, the overlapping portion 1031 of the common electrode 103 is not limited to the case shown in the drawing, and the overlapping portion 1031 of the common electrode 103 may vary in accordance with the shape of the data line.
  • a common electrode 103 is included in one sub-pixel region, and the common electrode 103 includes an overlap portion 1031 and a plurality of common electrode strips 1030, and the overlap portion 1031 and the plurality of common electrode strips 1030 are electrically connected.
  • the pixel electrode 105 includes a plurality of pixel electrode strips 1050.
  • the plurality of pixel electrode strips 1050 and the plurality of common electrode strips 1030 are alternately arranged in the sub-pixels.
  • a parallel electric field can be formed between the pixel electrodes and the common electrode formed by the same layer to drive the liquid crystal rotation. .
  • the pixel electrode and the common electrode may not be in the same layer, for example, an array substrate of an Advanced-Super Dimensional Switching (ADS) mode.
  • ADS Advanced-Super Dimensional Switching
  • the pixel electrode and the common electrode may include a plurality of electrode strips.
  • the configuration of the sub-pixel 1 is not limited to that shown in FIG.
  • two gate lines may be disposed between adjacent row sub-pixels.
  • two data lines can be placed between two adjacent columns of sub-pixels.
  • the common electrode strip 1030 and the pixel electrode strip 1050 are linear as an example.
  • the shape of the common electrode strip 1030 and the pixel electrode strip 1050 is not limited in this embodiment, for example, the common electrode strip 1030 and the pixel electrode strip 1050. It can also be other shapes such as a line shape.
  • the overlapping portion 1031 of the common electrode 103 has an interval 013 therebetween, and the two common electrodes 103 adjacent to each other are disconnected, thereby being compared with the provision of the common electrode in the interval.
  • the electric field formed between the common electrode and the pixel electrode in the interval is removed, thereby weakening the electric field disorder at the edge of the sub-pixel region, which is advantageous for increasing the aperture ratio and reducing light leakage and color mixture.
  • the overlapping portion 1031 may have a portion that does not overlap, in addition to a portion overlapping the data line 102 in a direction perpendicular to the base substrate 10.
  • the length of the overlapping portion 1031 in the first direction is greater than or equal to the length of the data line 102 having an overlapping portion thereof in a direction perpendicular to the base substrate 10 in the first direction.
  • each common electrode 103 may correspond to one sub-pixel.
  • each of the common electrodes 103 may correspond to one row of sub-pixels, that is, one common electrode 103 is disposed corresponding to each row of sub-pixels.
  • each common electrode 103 corresponds to a plurality of rows, for example, two rows of sub-pixels, that is, a plurality of rows of sub-pixels are correspondingly disposed with one common electrode 103. This embodiment does not limit this.
  • adjacent common electrodes are insulated from each other.
  • the width of the gate line 101 at the intersection with the data line 102 is smaller than the width of the gate line 101 between the adjacent two data lines (within the sub-pixel).
  • the reduction in the width of the gate line 101 at the intersection with the data line 102 is advantageous for reducing parasitic capacitance.
  • the width of the gate lines 101 at the intersection of the data lines 102 is about 1/10 of the width of the portion of the gate lines 101 between the data lines 102. ⁇ 1/2 between.
  • a common electrode line 104 electrically connected to the common electrode 103 is further included, and the common electrode line 104 is parallel to the gate line 101.
  • the common electrode line 104 can be obtained by the same patterning process from the same metal film as the gate line 101.
  • the gate line 101 and the common electrode line 104 are disposed in the same layer and are disposed on both sides of the sub-pixel.
  • the width of the common electrode line 104 at the intersection with the data line 102 is smaller than the width of the common electrode line 104 between the adjacent two data lines (within the sub-pixel).
  • the reduction in the width of the common electrode line 104 at the intersection with the data line 102 is advantageous for reducing parasitic capacitance, reducing light leakage, color mixing, and increasing aperture ratio.
  • the width of the common electrode line 104 at the intersection with the data line 102 is about the portion of the common electrode line 104 between the data lines 102. Between 1/10 and 1/2 of the width.
  • the array substrate provided in the first embodiment further includes a thin film transistor 109 including a source 106 electrically connected to the data line 102, and the source 106 includes electricity.
  • At least two branches 1061, 1062 are connected, each branch being electrically connected to the data line 102, and a hollow portion 0106 between the adjacent two branches 1061, 1062 (the source 106 has a hollow portion 0106).
  • the connection of the source 106 having the hollow portion 0106 to the data line 102 is advantageous for reducing parasitic capacitance, increasing the channel width, and increasing the charging current, thereby improving the display picture quality.
  • the electrical connection between the source 106 and the data line 102 is not affected, which is advantageous for maintaining the yield.
  • the length of the portion of the active region 108 between the source 106 and the drain 107 corresponds to the channel width of the thin film transistor 109.
  • the length of the source 106 and the drain 107 is between 2 and 30 ⁇ m
  • the width of the source 106 and the drain 107 is between 2 and 10 ⁇ m
  • the source 106 is electrically connected to the data line 102.
  • the formation process of the thin film transistor 109 includes sequentially forming a gate insulating layer and an active region 108 over the gate line 101 (eg, the gate is electrically connected to the gate line 101 and formed in the same layer as the gate line 101).
  • a data line 102, a source 106, and a drain 107 may be formed in the same layer on the active region 108.
  • a portion of the corresponding gate line 101 under the active region 108 forms a gate of the thin film transistor 109.
  • Source 106 and drain 107 can be in direct contact with active region 108.
  • the passivation layer comprises one of an inorganic insulating material or an organic insulating material
  • the pixel electrode 105 and the common electrode 103 may be formed in the same layer on the passivation layer, at the drain
  • a drain via 1071 is formed in the passivation layer above 107
  • the pixel electrode 105 is electrically connected to the drain 107 through the drain via 1071
  • a common electrode line is formed in the gate insulating layer and the passivation layer above the common electrode line 104.
  • the hole 1041, the common electrode 103 is electrically connected to the common electrode line 104 through the common electrode line via 1041.
  • the common electrode is formed on the data line as an example. It should be noted that the common electrode may be formed first and then the data line may be formed. This embodiment is not limited thereto.
  • the pixel electrode 105 and the gate line 101 have overlapping portions in a direction perpendicular to the substrate 10 , and the overlapping portion may form a storage capacitor.
  • the width of the overlapping portion of the pixel electrode 105 and the gate line 101 is between 2 and 30 ⁇ m.
  • the width of the portion where the common electrode 103 overlaps with the common electrode line 104 is between 2 and 30 ⁇ m; and the width of the portion where the common electrode 103 overlaps with the data line 102 is between 2 and 30 ⁇ m.
  • the width of the pixel electrode strip 1050 is between 2 and 10 ⁇ m, and the width of the gate line 101 is between 2 and 30 ⁇ m.
  • FIG. 1 Only a partial structure of the array substrate is shown in FIG. 1, and the number of the gate lines 101, the data lines 102, the common electrode lines 104, the common electrodes 103, and the pixel electrodes 105 included in the array substrate is not limited to that shown in the drawing.
  • the embodiment provides an array substrate. As shown in FIG. 2 , the difference from the first embodiment is that the array substrate further includes a data line disposed in a direction perpendicular to the substrate 10 and spaced apart from the substrate 10 .
  • 102 has a common electrode connection portion 1032 of an overlapping portion, and the common electrode connection portion 1032 is electrically connected to the overlapping portion 1031 of the two common electrodes 103 adjacent in the second direction such that the adjacent two common electrodes 103 are electrically connected, common
  • the length of the electrode connecting portion 1032 in the first direction is smaller than the length of the overlapping portion 1031 connected thereto in the first direction, the common electrode connecting portion 1032 and the data line 102 are insulated from each other, and the common electrode connecting portion 1032 and the gate line 101 are insulated from each other.
  • the length of the common electrode connecting portion 1032 disposed in the interval 013 having an overlapping portion with the data line 102 in the direction perpendicular to the base substrate 10 in the first direction is smaller than the length in the first direction of the overlapping portion 1031 connected thereto . Therefore, compared with the length of the common electrode connecting portion 1032 in the first direction is equal to the length of the overlapping portion 1031 in the first direction, it is advantageous to weaken the electric field of the pixel region chaos, reduce light leakage and color mixing, and is advantageous for improving the sub-pixel.
  • the aperture ratio which in turn increases the aperture ratio of the pixel.
  • the embodiment provides an array substrate. As shown in FIG. 3, the array substrate is different from the first embodiment in that the gate line 101 and the common electrode line 104 are disposed on the same side of the sub-pixel 1, and the pixel electrode 105 is The gate line 101 no longer has an overlapping portion in a direction perpendicular to the base substrate 10, but the pixel electrode 105 and the common electrode line 104 have overlapping portions in a direction perpendicular to the base substrate 10, and the pixel electrode 105 and the common electrode line
  • the overlapping portion of 104 forms a storage capacitor, for example, the line width of the overlapping portion is between 2 and 30 ⁇ m.
  • the data lines in FIGS. 1 to 3 are linear, but the data lines may not be linear.
  • the data lines may also be in a zigzag shape.
  • the data lines may form a zigzag-like shape.
  • Embodiments of the present disclosure do not limit the form in which the data lines extend in the second direction. Accordingly, the shape of the overlapping portion 1031 of the common electrode may vary according to the shape of the data line having the overlapping portion thereof.
  • the drawings are only for the purpose of illustration and not limitation of the embodiments.
  • This embodiment provides a display panel including any of the array substrates described in Embodiments 1 to 3.
  • This embodiment provides a display device, including any of the display panels described in Embodiment 4.

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Abstract

提供一种阵列基板、显示面板及显示装置。该阵列基板包括设置在衬底基板(10)上的多条栅线(101)、多条数据线(102)和多个公共电极(103)；多条栅线(101)沿第一方向延伸；多条数据线(102)沿第二方向延伸，并与多条栅线(101)交叉且绝缘，第二方向与第一方向不同；多个公共电极(103)沿第二方向排列，相邻的两个公共电极(103)之间具有栅线(101)，多个公共电极(103)与多条数据线(102)彼此绝缘，每个公共电极(103)包括与至少一条数据线(102)在垂直于衬底基板(10)的方向上具有重叠部分的重叠部(1031)，在第二方向上相邻的两个公共电极(103)中，与同一条数据线(102)在垂直于衬底基板(10)的方向上具有重叠部分的重叠部(1031)之间具有间隔(013)，并且数据线(102)与位于相邻的两个公共电极(103)之间的栅线(101)的交叉处位于间隔(013)内。利用该阵列基板，可以提高像素的开口率，减少漏光和混色。

Description

阵列基板、显示面板及显示装置 技术领域
本公开至少一实施例涉及一种阵列基板、显示面板及显示装置。
背景技术
平面转换(In-Plane Switching，IPS)液晶显示模式利用在同一平面的像素电极和公共电极，形成平行于玻璃表面或电极表面的平行电场，使得液晶分子在平行于玻璃表面的平面内偏转，以进行显示。IPS像素结构在像素电极的同层设置公共电极，可形成叉指电极形状。
发明内容
本公开的至少一实施例涉及一种阵列基板、显示面板及显示装置。本公开的实施例提供一种平面转换液晶模式的阵列基板，有利于矫正子像素边缘部分的电场混乱，减少漏光和混色，提高子像素的开口率，进而提高像素的开口率。
本公开的至少一个实施例提供了一种阵列基板，包括设置在衬底基板上的多条栅线、多条数据线和多个公共电极；所述多条栅线沿第一方向延伸；所述多条数据线沿第二方向延伸，并与所述多条栅线交叉且绝缘，所述第二方向与所述第一方向不同；所述多个公共电极沿所述第二方向排列，相邻的两个公共电极之间具有栅线，所述多个公共电极与所述多条数据线彼此绝缘，每个所述公共电极包括与至少一条所述数据线在垂直于所述衬底基板的方向上具有重叠部分的重叠部，在所述第二方向上相邻的两个公共电极中，与同一条数据线在垂直于所述衬底基板的方向上具有重叠部分的重叠部之间具有间隔，并且所述数据线与位于所述相邻的两个公共电极之间的栅线的交叉处位于所述间隔内。
本公开的至少一个实施例提供了一种显示面板，包括本公开的实施例提供的任一阵列基板。
本公开的至少一个实施例提供了一种显示装置，包括本公开的实施例提供的任一显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种阵列基板的结构示意图；
图2为本公开一实施例提供的另一种阵列基板的结构示意图；
图3为本公开一实施例提供的另一种阵列基板的结构示意图。
附图标记：
10-衬底基板；101-栅线；102-数据线；103-公共电极；1030-公共电极条；1031-重叠部；1032-公共电极连接部；104-公共电极线；1041-公共电极线过孔；105-像素电极；1050-像素电极条；106-源极；1061-子源极；1062-子源极；107-漏极；1071-漏极过孔；108-有源区；109-薄膜晶体管；013-间隔；1-子像素；0106-镂空部。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地 改变。
IPS模式中，由于薄膜晶体管及其栅线、公共电极及其公共电极线占用较大的布线面积，IPS液晶模式一般具有较低的开口率。同时相邻子像素公共电极的互联导致子像素边缘区电场混乱，容易产生漏光和混色，进一步降低了开口率。
本公开的实施例提供了一种阵列基板、显示面板及显示装置。该阵列基板包括设置在衬底基板上的多条栅线、多条数据线和多个公共电极；多条栅线沿第一方向延伸；多条数据线沿第二方向延伸，并与多条栅线交叉且绝缘，第二方向与第一方向不同；多个公共电极沿第二方向排列，相邻的两个公共电极之间具有栅线，多个公共电极与多条数据线彼此绝缘，每个公共电极包括与至少一条数据线在垂直于衬底基板的方向上具有重叠部分的重叠部，在第二方向上相邻的两个公共电极中，与同一条数据线在垂直于衬底基板的方向上具有重叠部分的重叠部之间具有间隔，并且数据线与位于相邻的两个公共电极之间的栅线的交叉处位于间隔内。利用该阵列基板，有利于矫正子像素边缘部分的电场混乱，减少漏光和混色，提高子像素的开口率，进而提高像素的开口率。
下面结合附图，对本公开实施例提供的阵列基板进行说明。图中源极、漏极、像素电极和公共电极采用半透明处理，从而能够清晰地表明各层结构的关系。
实施例一
本实施例提供了一种阵列基板，如图1所示，该阵列基板包括：设置在衬底基板10上的多条栅线101、多条数据线102以及多个公共电极103。为简化附图，图1中上边的公共电极只示出了一部分。如图1所示，多条栅线101沿第一方向延伸。多条数据线102沿第二方向延伸，并与多条栅线101交叉且绝缘，第二方向与第一方向不同。图1中，第一方向为沿纸面的水平方向，第二方向为沿纸面的竖直方向，第一方向垂直于第二方向，有关第一方向和第二方向不限于图中所示。例如，多条栅线101与多条数据线102交叉且绝缘设置，且多条栅线101与多条数据线102交叉限定多个子像素1。图1中虚线框内为一个子像素1。
如图1所示，多个公共电极103沿第二方向排列，相邻的两个公共电极 103之间具有一条栅线101，多个公共电极103与多条数据线102彼此绝缘，每个公共电极103包括与至少一条数据线102在垂直于衬底基板10的方向上具有重叠部分的重叠部1031，在第二方向上相邻的两个公共电极103中，与同一条数据线102在垂直于衬底基板10的方向上具有重叠部分的重叠部1031之间具有间隔013，并且数据线102与位于相邻的两个公共电极103之间的栅线101的交叉处位于间隔013内。本实施例以上下相邻的两个公共电极103之间具有一条栅线101为例进行说明，需要说明的是，相邻的两个公共电极103之间的栅线101也可多于一条，在此不作限定。本实施例以重叠部1031在垂直于衬底基板10的方向上与一条数据线102具有重叠部分为例进行说明，相邻两列子像素之间具有多条例如两条数据线的情况下，重叠部1031可以在垂直于衬底基板10的方向上与相邻两列子像素之间的多条数据线102具有重叠部分。
需要说明的是，图1中示出的数据线为直线形，但数据线的形状不限于图中所示，例如还可以为折线形等其他形状。相应的，公共电极103的重叠部1031也不限于图中所示的情形，公共电极103的重叠部1031可依照数据线的形状变化。
如图1所示，在一个子像素区域中包括公共电极103，公共电极103包括重叠部1031和多个公共电极条1030，重叠部1031和多个公共电极条1030电连接。像素电极105包括多个像素电极条1050，多个像素电极条1050和多个公共电极条1030在子像素内交替排布，同层形成的像素电极和公共电极之间可形成平行电场驱动液晶旋转。需要说明的是，像素电极和公共电极也可不在同一层，例如形成高级超维场开关(Advanced-Super Dimensional Switching，ADS)模式的阵列基板。并且，像素电极和公共电极中的至少一个包括多个电极条即可。子像素1的构成也不限于图1所示。例如，相邻行子像素间可以设置两条栅线。例如，相邻两列子像素间可设置两条数据线。本实施例以公共电极条1030和像素电极条1050为直线形为例进行说明，但本实施例对公共电极条1030和像素电极条1050的形状不作限定，例如公共电极条1030和像素电极条1050还可以为折线形等其他形状。
本实施例提供的阵列基板中，公共电极103的重叠部1031之间具有间隔013，上下相邻的两个公共电极103断开，从而，与间隔内设置公共电极相比， 间隔内的公共电极与像素电极之间形成的电场被去除，从而，减弱了子像素区边缘的电场混乱，有利于提高开口率，并减少漏光和混色。
重叠部1031除了在垂直于衬底基板10的方向上与数据线102具有重叠部分外，还可以具有不重叠的部分。例如，如图1所示，重叠部1031在第一方向上的长度大于等于在垂直于衬底基板10的方向上与其具有重叠部分的数据线102在第一方向上的长度。从而，可以使得重叠部1031与像素电极105之间产生电场，可驱动子像素边缘的液晶旋转，可提高子像素的开口率。
例如，如图1所示，每个公共电极103可对应一个子像素。再如，每个公共电极103可对应一行子像素，即，每行子像素对应设置一个公共电极103。又例如，每个公共电极103对应多行例如两行子像素，即，多行子像素对应设置一个公共电极103。本实施例对此不作限定。例如，相邻公共电极之间彼此绝缘。
例如，如图1所示，栅线101在与数据线102的交叉处的宽度小于栅线101在相邻两条数据线之间(子像素内)的宽度。栅线101在与数据线102的交叉处的宽度的减小，有利于降低寄生电容。例如，为了使得栅线具有较好的信号传输效果并且形成较低的寄生电容，栅线101在数据线102交叉处的宽度约为栅线101位于数据线102之间的部分宽度的1/10～1/2之间。
例如，在本实施例一示例提供的阵列基板中，如图1所示，还包括与公共电极103电连接的公共电极线104，公共电极线104与栅线101平行。公共电极线104可与栅线101由同一层金属薄膜经同一构图工艺而得。例如，如图1所示，栅线101和公共电极线104同层设置，并分设于子像素的两侧。
例如，如图1所示，公共电极线104在与数据线102的交叉处的宽度小于公共电极线104在相邻两条数据线之间(子像素内)的宽度。公共电极线104在与数据线102的交叉处的宽度的减小，有利于降低寄生电容，减轻漏光、混色现象，并提高开口率。例如，为了使得公共电极线具有较好的信号传输效果并且形成较低的寄生电容，公共电极线104在与数据线102的交叉处的宽度约为公共电极线104位于数据线102之间的部分宽度的1/10～1/2之间。
例如，如图1所示，本实施例一示例提供的阵列基板还包括薄膜晶体管109，薄膜晶体管109包括与数据线102电连接的源极106,源极106包括电 连接的至少两个分支1061、1062，每个分支与数据线102电连接，相邻两个分支1061、1062之间具有镂空部0106(源极106具有镂空部0106)。具有镂空部0106的源极106与数据线102的连接方式有利于降低寄生电容，增大沟道宽度和提高充电电流，从而提高显示画面品质。同时，如果一个分支出现断路等问题，不影响源极106与数据线102之间的电连接，有利于保持良率。例如，有源区108位于源极106和漏极107之间的部分的长度对应薄膜晶体管109的沟道宽度。例如，源极106和漏极107的长度在2～30μm之间，源极106和漏极107的宽度在2～10μm之间，源极106与数据线102电连接。
一个示例中，薄膜晶体管109的形成过程包括：在栅线101(例如，栅极与栅线101电连接并与栅线101同层形成)之上依次形成栅极绝缘层和有源区108。在有源区108上可同层形成数据线102、源极106和漏极107。有源区108之下对应的栅线101部分形成薄膜晶体管109的栅极。源极106和漏极107可直接与有源区108接触。在源漏金属层上方形成钝化层，例如，钝化层包含无机绝缘材料、或有机绝缘材料中的一种，可在钝化层上同层形成像素电极105和公共电极103，在漏极107上方的钝化层中形成漏极过孔1071，像素电极105通过漏极过孔1071与漏极107电连接，公共电极线104上方的栅极绝缘层和钝化层中形成公共电极线过孔1041，公共电极103通过公共电极线过孔1041与公共电极线104电连接。
本实施例以公共电极形成在数据线上为例进行说明，需要说明的是，也可以先形成公共电极，再形成数据线，本实施例对此不作限定。
例如，如图1所示，本实施例一示例提供的阵列基板中，像素电极105与栅线101在垂直于衬底基板10的方向上具有重叠部分，重叠部分可形成存储电容。例如，像素电极105与栅线101的重叠部分的宽度在2～30μm之间。
例如，本实施例的一个示例中，公共电极103与公共电极线104重叠的部分宽度在2～30μm之间；公共电极103与数据线102重叠的部分的宽度在2～30μm之间。例如，像素电极条1050的宽度为2～10μm之间，栅线101的宽度在2～30μm之间。
图1中只示出阵列基板的部分结构，阵列基板包括的栅线101、数据线102、公共电极线104、公共电极103以及像素电极105等的个数不限于图中所示。
实施例二
本实施例提供了一种阵列基板，如图2所示，与实施例一的不同之处在于，该阵列基板还包括设置在间隔013内的在垂直于衬底基板10的方向上与数据线102具有重叠部分的公共电极连接部1032，公共电极连接部1032与在第二方向上相邻的两个公共电极103的重叠部1031电连接以使得相邻的两个公共电极103电连接，公共电极连接部1032沿第一方向上的长度小于与其连接的重叠部1031沿第一方向上的长度，公共电极连接部1032与数据线102彼此绝缘，公共电极连接部1032与栅线101彼此绝缘。设置在间隔013内的在垂直于衬底基板10的方向上与数据线102具有重叠部分的公共电极连接部1032沿第一方向上的长度小于与其连接的重叠部1031沿第一方向上的长度。从而，与公共电极连接部1032沿第一方向上的长度等于重叠部1031沿第一方向上的长度相比，有利于减弱像素区边缘混乱的电场，减少漏光和混色，有利于提高子像素的开口率，进而提高像素的开口率。
实施例三
本实施例提供了一种阵列基板，如图3所示，该阵列基板与实施例一的不同之处在于，栅线101和公共电极线104设置在子像素1的同一侧，像素电极105与栅线101在垂直于衬底基板10的方向上不再具有重叠部分，而是像素电极105与公共电极线104在垂直于衬底基板10的方向上具有重叠部分，像素电极105与公共电极线104的重叠部分形成存储电容，例如，重叠部分的线宽在2～30μm之间。
图1-图3中数据线为直线形，但数据线也可以不为直线形，例如，数据线还可为折线形，沿第二方向上，数据线可形成类似于锯齿的折线形。本公开的实施例对数据线沿第二方向延伸的形态不作限定。相应的，公共电极的重叠部1031的形状可依照与其具有重叠部分的数据线的形状变化。附图只是为了说明并非限定本公开的实施例。
实施例四
本实施例提供了一种显示面板，包括实施例一至实施例三所述的任一阵列基板。
实施例五
本实施例提供了一种显示装置，包括实施例四所述的任一显示面板。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一附图标记代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(4)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本专利申请要求于2016年8月31日递交的中国专利申请第201621033726.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种阵列基板，包括设置在衬底基板上的多条栅线、多条数据线和多个公共电极；其中，
    所述多条栅线沿第一方向延伸；
    所述多条数据线沿第二方向延伸，并与所述多条栅线交叉且绝缘，所述第二方向与所述第一方向不同；
    所述多个公共电极沿所述第二方向排列，相邻的两个公共电极之间具有栅线，所述多个公共电极与所述多条数据线彼此绝缘，每个所述公共电极包括与至少一条所述数据线在垂直于所述衬底基板的方向上具有重叠部分的重叠部，在所述第二方向上相邻的两个公共电极中，与同一条数据线在垂直于所述衬底基板的方向上具有重叠部分的重叠部之间具有间隔，并且所述数据线与位于所述相邻的两个公共电极之间的栅线的交叉处位于所述间隔内。
  2. 根据权利要求1所述的阵列基板，其中，所述重叠部在所述第一方向上的长度大于等于在垂直于所述衬底基板的方向上与其具有重叠部分的所述数据线在所述第一方向上的长度。
  3. 根据权利要求1所述的阵列基板，还包括设置在所述间隔内的在垂直于所述衬底基板的方向上与所述数据线具有重叠部分的公共电极连接部，其中，所述公共电极连接部与在所述第二方向上相邻的两个公共电极的所述重叠部电连接以使得所述相邻的两个公共电极电连接，所述公共电极连接部沿所述第一方向上的长度小于与其连接的所述重叠部沿所述第一方向上的长度，所述公共电极连接部与所述数据线绝缘，所述公共电极连接部与所述栅线绝缘。
  4. 根据权利要求1-3任一项所述的阵列基板，其中，所述数据线的形状包括直线形、折线形中的任一种。
  5. 根据权利要求1-4任一项所述的阵列基板，其中，所述多条栅线和所述多条数据线交叉限定多个子像素，每个所述公共电极对应至少一个子像素。
  6. 根据权利要求5所述的阵列基板，其中，所述栅线在与所述数据线的交叉处的宽度小于所述栅线在相邻两条数据线之间的宽度。
  7. 根据权利要求5所述的阵列基板，还包括与所述公共电极电连接的公 共电极线，其中，所述公共电极线与所述栅线平行，所述公共电极线在与所述数据线的交叉处的宽度小于所述公共电极线在相邻两条数据线之间的宽度。
  8. 根据权利要求7所述的阵列基板，其中，所述栅线和所述公共电极线同层设置，并分设于所述子像素的两侧，或所述栅线和所述公共电极线设置在所述子像素的同一侧。
  9. 根据权利要求8所述的阵列基板，还包括像素电极，其中，所述像素电极与所述栅线或所述公共电极线在垂直于所述衬底基板的方向上具有重叠部分，所述像素电极和所述公共电极被配置来形成电场以驱动液晶旋转。
  10. 根据权利要求9所述的阵列基板，其中，所述像素电极和所述公共电极中的至少一个包括多个电极条。
  11. 根据权利要求9所述的阵列基板，其中，所述像素电极和所述公共电极分别包括多个电极条，所述像素电极的多个电极条和所述公共电极的多个电极条交替排布。
  12. 根据权利要求1-11任一项所述的阵列基板，还包括薄膜晶体管，其中，所述薄膜晶体管包括与所述数据线电连接的源极，所述源极包括电连接的至少两个分支，每个分支与所述数据线电连接，相邻两个分支之间具有镂空部。
  13. 一种显示面板，包括权利要求1-12任一项所述的阵列基板。
  14. 一种显示装置，包括权利要求13所述的显示面板。
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