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WO2017063476A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2017063476A1
WO2017063476A1 PCT/CN2016/099318 CN2016099318W WO2017063476A1 WO 2017063476 A1 WO2017063476 A1 WO 2017063476A1 CN 2016099318 W CN2016099318 W CN 2016099318W WO 2017063476 A1 WO2017063476 A1 WO 2017063476A1
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WIPO (PCT)
Prior art keywords
substrate
pattern
photoresist
gate
common electrode
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Application number
PCT/CN2016/099318
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English (en)
French (fr)
Inventor
林亮
杨成绍
姜涛
邹志翔
黄寅虎
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/528,963 priority Critical patent/US20170261820A1/en
Publication of WO2017063476A1 publication Critical patent/WO2017063476A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136295—Materials; Compositions; Manufacture processes
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F2202/10—Materials and properties semiconductor

Definitions

  • the present invention relates to the field of LCD (Liquid Crystal Display), and more particularly to an array substrate and a method of fabricating the same.
  • LCD Liquid Crystal Display
  • the TFT LCD can be classified into a TN (Twisted Nematic) type, an In Plane Switching (IPS) type, and an Advanced Super Dimension Switch (ADS) type.
  • TN Transmission Nematic
  • IPS In Plane Switching
  • ADS Advanced Super Dimension Switch
  • the array substrate of the ADS type LCD includes a substrate, a common electrode sequentially formed on the substrate, a gate electrode, a semiconductor layer, a source/drain, a passivation layer, and a pixel electrode.
  • a four-mask (4MASK) fabrication process is known, as follows: First, a common electrode (1st ITO) and a gate (Gate) are formed on the substrate; Forming a semiconductor layer and a source and drain (S/D) on the substrate; in the third step, forming a passivation layer on the substrate and fabricating a via hole; and forming a pixel electrode (2nd ITO) on the substrate in the fourth step .
  • 4 MASK are: ITO Gate Mask in the first step, S D Mask in the second step, Via hole Mask in the third step and ITO Mask in the fourth step.
  • the array substrate of the ADS type LCD produced by the above process has the following problem: water vapor remains in the common electrode ITO. Part of the water vapor remains to prevent crystallization of the common electrode ITO during film formation, water added when ITO is formed (for example, by sputtering), and water which is absorbed from the air after ITO film formation. The water vapor residue forms a bulge at the interface between the ITO and other layers. These bulges are prone to cracking in the high temperature vacuum process after the common electrode and gate are completed, resulting in short circuit of the data line and the gate, which seriously affects the yield of the ADS product. .
  • an embodiment of the present invention provides an array substrate and a method of fabricating the same, in which annealing is performed after forming an ITO film, so that moisture residue in the ITO film can be released, thereby avoiding an interface between the ITO and other layers.
  • an embodiment of the present invention provides a method for fabricating an array substrate, the method comprising:
  • the ITO film and the gate metal film are processed to obtain a common electrode pattern and a gate pattern.
  • the temperature of the annealing treatment is 120 to 160 degrees Celsius.
  • the temperature of the annealing treatment is 140 degrees Celsius.
  • the annealing treatment time is 30 minutes.
  • the annealing treatment atmosphere is nitrogen.
  • the processing the ITO film and the gate metal film to obtain a common electrode pattern and a gate pattern including:
  • the ITO film and the gate metal film are etched by a gray-scale mask etching process to obtain the common electrode pattern and the gate pattern.
  • the ITO film and the gate metal film are etched by using a gray-scale mask etching process to obtain the common electrode pattern and the gate pattern.
  • the substrate on which the photoresist pattern is formed is etched to obtain the common electrode pattern and the gate pattern.
  • the substrate formed with the photoresist pattern is etched to obtain the common electrode pattern and the gate pattern, including:
  • the remaining photoresist is removed.
  • the ITO film and the gate metal film are etched by using a gray-scale mask etching process to obtain the common electrode pattern and the gate pattern. Also includes:
  • the substrate After etching the substrate on which the photoresist pattern is formed, the substrate is annealed.
  • the method further includes:
  • a pixel electrode is formed on the substrate on which the passivation layer and the via are formed.
  • an embodiment of the present invention further provides an array substrate, which is fabricated by the method described in the first aspect.
  • annealing is performed after forming the ITO film, so that the water vapor residue in the ITO film can be released, thereby avoiding the formation of a bulge at the interface between the ITO and other layers, and improving the yield of the ADS product.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 2 is a flow chart of a method for fabricating an array substrate according to another embodiment of the present invention.
  • FIG. 2a is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 2b is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • 2c is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • 2d is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • 2 e is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • 2f is a schematic structural view of a process of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 2g is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention. Referring to FIG. 1, the method includes:
  • Step 101 Forming a thin film of Indium Tin Oxide (ITO) on the substrate.
  • ITO Indium Tin Oxide
  • Step 102 Annealing the substrate.
  • Step 103 Forming a gate metal film on the ITO film.
  • Step 104 The ITO film and the gate metal film are processed to obtain a common electrode pattern and a gate pattern.
  • the common electrode pattern and the gate pattern can be obtained by processing the ITO film and the gate metal film in a single patterning process, as described in detail later.
  • the common electrode pattern and the gate pattern may also be obtained by processing the ITO film and the gate metal film without using a patterning process (instead, for example, using two patterning processes), which is not described in the present invention.
  • annealing is performed after forming the ITO film, so that the water vapor residue in the ITO film can be released, thereby avoiding the formation of a bulge at the interface between the ITO and other layers, and improving the yield of the ADS product.
  • FIG. 2 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present invention. Referring to FIG. 2, the method includes:
  • Step 201 Forming a layer of ITO film on the substrate.
  • an ITO film 210 is formed on the substrate 20.
  • Step 202 Annealing the substrate.
  • the annealing treatment temperature may be 120 to 160 degrees Celsius.
  • the annealing temperature selected in this embodiment is 120 to 160 degrees Celsius to sufficiently release water vapor.
  • the annealing treatment temperature is 140 degrees Celsius, so that the water vapor release is sufficient and the degree of crystallization is balanced.
  • the annealing treatment time can be 30 minutes.
  • the annealing temperature selected in this embodiment was 30 minutes to sufficiently release water vapor.
  • the annealing treatment atmosphere may be nitrogen.
  • other common annealing atmospheres can be selected.
  • Step 203 Forming a gate metal film on the ITO film.
  • a gate metal film can be formed on the ITO film by a sputtering process.
  • a gate metal film 220 is formed on the substrate 20 on which the ITO film 210 is formed.
  • an insulating layer can be formed on the ITO film by spraying, spin coating, sputtering or the like before forming the gate metal film.
  • Step 204 etching the ITO film and the gate metal film by using a gray-scale mask etching process to obtain a common electrode pattern and a gate pattern.
  • a gray pattern mask etching process is used to realize a patterning process to obtain a common electrode pattern and a gate pattern, thereby saving manufacturing steps.
  • the ITO film and the gate metal film are etched by a gray-scale mask etching process to obtain a common electrode pattern and a gate pattern, including:
  • step 1 a photoresist is coated on the substrate; as shown in FIG. 2c, a photoresist 230 is coated on the substrate 20 on which the ITO film 210 and the gate metal film 220 are formed.
  • Step 2 exposing the photoresist by using a gray-scale mask to obtain a photoresist pattern, the photoresist pattern comprising a first portion 231 and a second portion 232, the thickness of the first portion 231 being smaller than the thickness of the second portion 232; As shown in 2d, the photoresist pattern includes a first portion 231 and a second portion 232.
  • Step 3 etching the substrate on which the photoresist pattern is formed to obtain a common electrode pattern Case and gate pattern.
  • Step 3 can be seen in Figure 2e-2g, including:
  • the ITO film and the gate metal film are etched by a gray-scale mask etching process to obtain a common electrode pattern and a gate pattern, and further includes:
  • the substrate After etching the substrate on which the photoresist pattern is formed, the substrate is annealed.
  • Step 205 forming a semiconductor layer and a source and drain on the substrate on which the common electrode pattern and the gate pattern are formed.
  • step 205 may form a semiconductor layer and a source drain using a patterning process.
  • the semiconductor layer may be formed by a patterning process, and then the source and drain electrodes are formed by a patterning process.
  • the source drain includes a source electrode and a drain electrode.
  • Step 206 Form a passivation layer on the substrate on which the semiconductor layer and the source and drain are formed and form via holes.
  • the via is formed on the passivation layer and exposes the drain electrode in the source and drain.
  • Step 207 forming a pixel electrode on the substrate on which the passivation layer and the via are formed.
  • the pixel electrode is connected to the drain electrode.
  • the steps 205 to 207 can be implemented by using a manufacturing process in the existing ADS type TFT LCD array substrate.
  • annealing is performed after forming the ITO film, so that the water vapor residue in the ITO film can be released, thereby avoiding the formation of a bulge at the interface between the ITO and other layers, and improving the yield of the ADS product.
  • the embodiment of the invention further provides an array substrate, which is fabricated by using the method corresponding to FIG. 1 or FIG. 2 .
  • annealing after forming the ITO film can release residual moisture in the ITO film, thereby avoiding the formation of a bulge at the interface between the ITO and other layers, and improving the yield of the ADS product.

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Abstract

一种阵列基板及其制作方法。该方法包括：在基板（20）上形成一层ITO薄膜（210）；对该基板进行退火处理；在该ITO薄膜上形成一层栅极金属薄膜（220）；对该ITO薄膜和该栅极金属薄膜进行处理，得到公共电极图案（21）和栅极图案（22）。该方法在形成ITO薄膜后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和其它层之间的界面处形成鼓包，提高ADS产品的良率。

Description

阵列基板及其制作方法 技术领域
本发明涉及LCD(Liquid Crystal Display，液晶显示器)领域，特别涉及一种阵列基板及其制作方法。
背景技术
TFT(Thin Film Transistor，薄膜晶体管)LCD因其性能优良、大规模生产特性好、发展空间广阔等优点，成为目前显示器领域的主流产品。TFT LCD按照显示模式可以分为：扭曲向列(TN，Twisted Nematic)型、平面转换(IPS，In Plane Switching)型和高级超维场开关(ADS，Advanced Super Dimension Switch)型。
ADS型LCD的阵列基板包括基板、依次形成在基板上的公共电极、栅极、半导体层、源漏极、钝化层及像素电极。为了减少上述阵列基板的制作工艺，现有一种4次掩模(4MASK)制作工艺，具体如下：第一步，在基板上形成公共电极(1st ITO)和栅极(Gate)；第二步，在基板上形成半导体层和源漏极(S/D)；第三步，在基板上形成钝化层并制作过孔(Via Hole)；第四步，在基板上形成像素电极(2nd ITO)。其中，4次MASK分别为：第一步中的ITO Gate Mask，第二步中S D Mask，第三步中过Via Hole Mask和第四步中ITO Mask。
采用上述工艺制成的ADS型LCD的阵列基板，存在以下问题：公共电极ITO中会存在水汽残留。水汽残留一部分是为了防止公共电极ITO成膜时晶化，在(例如使用溅射的方式)形成ITO时加入的水；另一部分是ITO成膜后从空气中吸收的水。水汽残留使得ITO和其他层之间的界面处形成鼓包，这些鼓包在公共电极和栅极制备完成后的高温真空工艺中容易发生破裂，导致数据线和栅极短路，严重影响ADS产品的良率。
发明内容
为此，本发明实施例提供了一种阵列基板及其制作方法，其中在形成ITO薄膜后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和其他层之间的界面处形成鼓包，提高ADS产品的良 率。
第一方面，本发明实施例提供了一种阵列基板制作方法，所述方法包括：
在基板上形成一层ITO薄膜；
对所述基板进行退火处理；
在所述ITO薄膜上形成一层栅极金属薄膜；
对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案。
在本发明实施例的一种实现方式中，所述退火处理的温度为120至160摄氏度。
在本发明实施例的另一种实现方式中，所述退火处理的温度为140摄氏度。
在本发明实施例的另一种实现方式中，所述退火处理的时间为30分钟。
在本发明实施例的另一种实现方式中，所述退火处理的气氛为氮气。
在本发明实施例的另一种实现方式中，所述对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案，包括：
采用灰阶掩模刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案。
在本发明实施例的另一种实现方式中，所述采用灰阶掩模刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案，包括：
在所述基板上涂布光刻胶；
采用灰阶掩模板对所述光刻胶进行曝光，得到光刻胶图案，所述光刻胶图案包括第一部分和第二部分，所述第一部分的厚度小于所述第二部分的厚度；
对形成有所述光刻胶图案的所述基板进行刻蚀，得到所述公共电极图案和所述栅极图案。
在本发明实施例的另一种实现方式中，所述对形成有所述光刻胶图案的所述基板进行刻蚀，得到所述公共电极图案和所述栅极图案，包括：
对所述基板进行第一次刻蚀工艺，对未覆盖所述光刻胶的所述栅极金属薄膜和所述ITO薄膜进行刻蚀，得到所述公共电极图案；
采用光刻胶灰化工艺，除去所述光刻胶图案中所述第一部分的光刻胶；
对所述基板进行第二次刻蚀工艺，对未覆盖所述光刻胶的所述栅极金属薄膜进行刻蚀，得到所述栅极图案；
除去剩余光刻胶。
在本发明实施例的另一种实现方式中，所述采用灰阶掩模刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案，还包括：
对形成有所述光刻胶图案的所述基板进行刻蚀后，对所述基板进行退火。
在本发明实施例的另一种实现方式中，所述方法还包括：
在形成有所述公共电极图案和所述栅极图案的所述基板上形成半导体层和源漏极；
在形成有所述半导体层和所述源漏极的所述基板上形成钝化层并制作过孔；
在形成有所述钝化层及所述过孔的所述基板上形成像素电极。
第二方面，本发明实施例还提供了一种阵列基板，所述阵列基板利用第一方面所述的方法制作而成。
在本发明实施例中，在形成ITO薄膜后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和其他层之间的界面处形成鼓包，提高ADS产品的良率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种阵列基板制作方法的流程图；
图2是本发明另一实施例提供的一种阵列基板制作方法的流程图；
图2a是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2b是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2c是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2d是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2e是本发明实施例提供的阵列基板制作过程中的结构示意图；
图2f是本发明实施例提供的阵列基板制作过程中的结构示意图；以及
图2g是本发明实施例提供的阵列基板制作过程中的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明专利保护的范围。
图1是本发明实施例提供的一种阵列基板制作方法的流程图，参见图1，该方法包括：
步骤101：在基板上形成一层氧化铟锡(Indium Tin Oxide，ITO)薄膜。
步骤102：对基板进行退火处理。
步骤103：在ITO薄膜上形成一层栅极金属薄膜。
步骤104：对ITO薄膜和栅极金属薄膜进行处理，得到公共电极图案和栅极图案。
其中，公共电极图案和栅极图案可以采用一次构图工艺处理ITO薄膜和栅极金属薄膜得到，具体见后文详细描述。公共电极图案和栅极图案也可以不采用一次构图工艺(转而，例如采用两次构图工艺)处理ITO薄膜和栅极金属薄膜得到，本发明对此不做赘述。
在本发明实施例中，在形成ITO薄膜后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和其他层之间的界面处形成鼓包，提高ADS产品的良率。
图2是本发明实施例提供的另一种阵列基板制作方法的流程图，参见图2，该方法包括：
步骤201：在基板上形成一层ITO薄膜。
如图2a所示，在基板20上形成一层ITO薄膜210。
本领域技术人员能够理解，可以使用磁控溅射法(magnetron sputtering)、化学气相沉积法(CVD)、喷雾热分解法(spray-pyrolysis)以及溶胶-凝胶法(sol-gel)等工艺来形成所述ITO薄膜。
步骤202：对基板进行退火处理。
其中，退火处理的温度可以为120至160摄氏度。本实施例选用的退火温度为120至160摄氏度，从而充分地释放水汽。
可选地，退火处理的温度为140摄氏度，使得水汽释放充分程度和晶化程度平衡。
其中，退火处理的时间可以为30分钟。本实施例选用的退火温度为30分钟，从而充分地释放水汽。
其中，退火处理的气氛可以为氮气。当然，在本实施例中除了采用氮气作为退火气氛外，还可以选择其他常见退火气氛。
步骤203：在ITO薄膜上形成一层栅极金属薄膜。
具体地，可以采用溅射工艺在ITO薄膜上形成一层栅极金属薄膜。
如图2b所示，在形成有ITO薄膜210的基板20上形成栅极金属薄膜220。
本领域技术人员能够理解，在形成栅极金属薄膜之前，还可以使用喷涂、旋涂、溅射等方法在ITO薄膜上形成一绝缘层。
步骤204：采用灰阶掩模刻蚀工艺刻蚀ITO薄膜和栅极金属薄膜，得到公共电极图案和栅极图案。
本实施例采用灰阶掩模刻蚀工艺实现一次构图工艺得到公共电极图案和栅极图案，节省制作步骤。
具体地，采用灰阶掩模刻蚀工艺刻蚀ITO薄膜和栅极金属薄膜，得到公共电极图案和栅极图案，包括：
步骤一，在基板上涂布光刻胶；如图2c所示，在形成有ITO薄膜210及栅极金属薄膜220的基板20上涂布光刻胶230。
步骤二，采用灰阶掩模板对光刻胶进行曝光，得到光刻胶图案，光刻胶图案包括第一部分231和第二部分232，第一部分231的厚度小于第二部分232的厚度；如图2d所示，光刻胶图案包括第一部分231和第二部分232。
步骤三，对形成有光刻胶图案的基板进行刻蚀，得到公共电极图 案和栅极图案。
其中，步骤三可以参见图2e-2g，具体包括：
对基板20进行第一次刻蚀工艺，对未覆盖光刻胶的栅极金属薄膜210和ITO薄膜220进行刻蚀，得到公共电极图案21，如图2e所示；采用光刻胶灰化工艺(ashing process)，除去光刻胶图案中第一部分231的光刻胶；对基板20进行第二次刻蚀工艺，对未覆盖光刻胶的栅极金属薄膜220进行刻蚀，得到栅极图案22，如图2f所述；以及，除去剩余光刻胶(第二部分232)，如图2g所示。
进一步地，采用灰阶掩模刻蚀工艺刻蚀ITO薄膜和栅极金属薄膜，得到公共电极图案和栅极图案，还包括：
对形成有光刻胶图案的基板进行刻蚀后，对基板进行退火。
步骤205：在形成有公共电极图案和栅极图案的基板上形成半导体层和源漏极。
具体地，步骤205可以采用一次构图工艺形成半导体层和源漏极。步骤205也可以先通过构图工艺形成半导体层，再通过构图工艺形成源漏极。其中，源漏极包括源电极和漏电极。
步骤206：在形成有半导体层和源漏极的基板上形成钝化层并制作过孔。
其中，过孔形成于钝化层上并使源漏极中的漏电极暴露出来。
步骤207：在形成有钝化层及过孔的基板上形成像素电极。
其中，像素电极与漏电极相连接。
其中，步骤205至步骤207可以采用现有ADS型TFT LCD阵列基板中制作工艺实现。
在本发明实施例中，在形成ITO薄膜后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和其他层之间的界面处形成鼓包，提高ADS产品的良率。
本发明实施例还提供了一种阵列基板，该阵列基板利用图1或者图2对应的方法制作而成。
在该阵列基板制作过程中，在形成ITO薄膜后进行退火，可以使得ITO薄膜中的水汽残留释放，从而避免了在ITO和其他层之间的界面处形成鼓包，提高ADS产品的良率。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并 不局限于此。任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种阵列基板制作方法，包括：
    在基板上形成一层ITO薄膜；
    对所述基板进行退火处理；
    在所述ITO薄膜上形成一层栅极金属薄膜；
    对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案。
  2. 根据权利要求1所述的方法，其中，所述退火处理的温度为120至160摄氏度。
  3. 根据权利要求2所述的方法，其中，所述退火处理的温度为140摄氏度。
  4. 根据权利要求1所述的方法，其中，所述退火处理的时间为30分钟。
  5. 根据权利要求1所述的方法，其中，所述退火处理的气氛为氮气。
  6. 根据权利要求1所述的方法，其中，所述对所述ITO薄膜和所述栅极金属薄膜进行处理，得到公共电极图案和栅极图案，包括：
    采用灰阶掩模刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案。
  7. 根据权利要求6所述的方法，其中，所述采用灰阶掩模刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案，包括：
    在所述基板上涂布光刻胶；
    采用灰阶掩模板对所述光刻胶进行曝光，得到光刻胶图案，所述光刻胶图案包括第一部分和第二部分，所述第一部分的厚度小于所述第二部分的厚度；
    对形成有所述光刻胶图案的所述基板进行刻蚀，得到所述公共电极图案和所述栅极图案。
  8. 根据权利要求7所述的方法，其中，所述对形成有所述光刻胶图案的所述基板进行刻蚀，得到所述公共电极图案和所述栅极图案，包括：
    对所述基板进行第一次刻蚀工艺，对未覆盖所述光刻胶的所述栅极金属薄膜和所述ITO薄膜进行刻蚀，得到所述公共电极图案；
    采用光刻胶灰化工艺，除去所述光刻胶图案中所述第一部分的光刻胶；
    对所述基板进行第二次刻蚀工艺，对未覆盖所述光刻胶的所述栅极金属薄膜进行刻蚀，得到所述栅极图案；
    除去剩余光刻胶。
  9. 根据权利要求7所述的方法，其中，所述采用灰阶掩模刻蚀工艺刻蚀所述ITO薄膜和所述栅极金属薄膜，得到所述公共电极图案和所述栅极图案，还包括：
    对形成有所述光刻胶图案的所述基板进行刻蚀后，对所述基板进行退火。
  10. 根据权利要求1所述的方法，其中，所述方法还包括：
    在形成有所述公共电极图案和所述栅极图案的所述基板上形成半导体层和源漏极；
    在形成有所述半导体层和所述源漏极的所述基板上形成钝化层并制作过孔；
    在形成有所述钝化层及所述过孔的所述基板上形成像素电极。
  11. 一种阵列基板，其中，所述阵列基板利用权利要求1-10所述的方法制作而成。
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