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WO2016206239A1 - 低温多晶硅薄膜晶体管及其制备方法 - Google Patents

低温多晶硅薄膜晶体管及其制备方法 Download PDF

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WO2016206239A1
WO2016206239A1 PCT/CN2015/092001 CN2015092001W WO2016206239A1 WO 2016206239 A1 WO2016206239 A1 WO 2016206239A1 CN 2015092001 W CN2015092001 W CN 2015092001W WO 2016206239 A1 WO2016206239 A1 WO 2016206239A1
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layer
ohmic contact
ions
contact layer
active layer
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PCT/CN2015/092001
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French (fr)
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敏健
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京东方科技集团股份有限公司
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Priority to US15/322,461 priority Critical patent/US9923075B2/en
Publication of WO2016206239A1 publication Critical patent/WO2016206239A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a low temperature polysilicon thin film transistor and a method of fabricating the same.
  • low temperature poly-silicon TFT Compared with amorphous silicon (a-Si) thin film transistors (TFTs), low temperature poly-silicon TFT (LTPS TFT) technology has many advantages, such as high mobility, up to 10 -100cm 2 /Vs or so, can be prepared at lower temperature conditions (less than 600 ° C), flexible substrate selection, lower preparation costs. Due to the excellent advantages of LTPS TFTs in the preparation of flexible displays, it has become the most important material in the flexible display production in the industry.
  • a-Si amorphous silicon
  • LTPS TFT low temperature poly-silicon TFT
  • the current flexible process temperature upper limit is 400 ° C
  • the high temperature activation after the ion implantation process cannot be completed, resulting in poor device characteristics of the flexible substrate LTPS TFT formed by the above non-flexible substrate TFT fabrication process, and heavy doping cannot be avoided. A large number of defects are generated.
  • the main purpose of the present disclosure is to provide a technical solution that can form an LTPS TFT device on a flexible substrate at a temperature lower than 400 ° C, while avoiding poor performance of the LTPS TFT device caused by ion implantation process and high temperature activation. .
  • the present disclosure provides a method for preparing a low temperature polysilicon thin film transistor, The method includes: forming an active layer on the base substrate; forming an ohmic contact layer on the active layer by an atomic layer deposition process, wherein the ohmic contact layer comprises a plurality of conductive ion layers and a plurality of single crystal silicon layers/ a polysilicon layer; a source and a drain are formed on the ohmic contact layer, and the source and the drain are in contact with the active layer through the ohmic contact layer.
  • the step of forming the ohmic contact layer includes: forming a gate insulating layer, a gate electrode, and an interlayer insulating layer on the active layer, wherein the interlayer insulating layer is located at the gate and the Between the source and the drain; forming a via hole on the interlayer insulating layer, the gate insulating layer, and the active layer by a dry etching process; using the atomic layer deposition process in the via hole
  • the conductive ion layer and the single crystal silicon layer/polysilicon layer are formed in an overlapping manner.
  • the thickness of the ohmic contact layer is greater than or equal to And less than or equal to
  • the ions in the conductive ion layer comprise: boron ions or phosphorus ions.
  • the doping concentration of the ions in the conductive ion layer ranges from 10 14 to 10 18 /cm 3 .
  • the doping concentration threshold is 10 15 /cm 3 .
  • the base substrate is a flexible substrate.
  • the temperature at which the ohmic contact layer is formed using the atomic layer deposition process is less than 300 °C.
  • the present disclosure also provides a low temperature polysilicon thin film transistor comprising: a substrate; an active layer disposed on the substrate; an ohmic contact layer disposed on the active layer, the ohmic contact layer comprising a plurality of conductive ion layers and a plurality of single crystal silicon layers/polysilicon layers, wherein the ohmic contact layer is formed on the active layer by an atomic layer deposition process; a source disposed on the ohmic contact layer And a drain, the source and the drain being in contact with the active layer through the ohmic contact layer.
  • the ions in the conductive ion layer include: boron ions or phosphorus ions; and the doping concentration of ions in the conductive ion layer ranges from 10 14 to 10 18 /cm 3 .
  • the doping concentration threshold is 10 15 /cm 3 .
  • the base substrate is a flexible substrate
  • the ohmic contact layer is formed by using the atomic layer deposition process at a temperature of less than 300 ° C.
  • the low temperature polysilicon thin film transistor and the preparation method thereof Compared with the prior art, the low temperature polysilicon thin film transistor and the preparation method thereof, The defect of poor performance of the LTPS TFT device formed on the flexible substrate by the ion implantation and high temperature activation process can be overcome, and the ohmic contact with good medium surface contact can be accurately formed only under the lower temperature condition below the upper limit of the temperature of the flexible substrate.
  • the contact layer greatly improves the performance of the LTPS TFT device on the flexible substrate.
  • FIG. 1 is a schematic diagram of a method of fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of forming an SD through hole according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural view of an ohmic contact layer formed in accordance with an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of the structure of a final formed LTPS TFT in accordance with an embodiment of the present disclosure.
  • the maximum temperature that the flexible substrate can withstand is about 400 ° C, and there is almost no activation under the temperature of 400 ° C, resulting in poor activation of the current flexible display back sheet, making the blending Miscellaneous The defect cannot be repaired, resulting in an inability to meet the electrical characteristics of the LTPS TFT device.
  • the present disclosure mainly forms an ohmic contact layer with good ohmic contact at the source and the drain by applying an ALD (Atomic Layer Deposition) method. Since the temperature conditions of the ALD process are below 400 degrees Celsius, and the deposition precision of the process is high, the two steps of ion implantation and high temperature activation can be replaced.
  • ALD Atomic Layer Deposition
  • Forming an LTPS TFT device on a flexible substrate by depositing a layer of highly doped monocrystalline or polycrystalline silicon before the source and drain, and then depositing the source and drain metal with a magnetron sputtering device, Thereby, the problem of poor performance of the LTPS TFT device formed on the flexible substrate using the existing ion implantation and high temperature activation processes is solved.
  • Embodiments of the present disclosure provide a method of fabricating a low temperature polysilicon thin film transistor.
  • 1 is a schematic diagram of a method of fabricating a low temperature polysilicon thin film transistor in accordance with an embodiment of the present disclosure. As shown in FIG. 1, the flow includes the following steps (step S102 - step S106):
  • Step S102 forming an active layer on the base substrate
  • Step S104 forming an ohmic contact layer on the active layer by using an atomic layer deposition process, wherein the ohmic contact layer comprises a plurality of conductive ion layers and a plurality of single crystal silicon layers/polysilicon layers;
  • Step S106 forming a source and a drain on the ohmic contact layer, and the source and the drain are in contact with the active layer through the ohmic contact layer.
  • ion implantation is directly performed by an atomic layer deposition process without performing ion implantation and high temperature activation, thereby forming an ohmic contact layer having good ohmic contact between the source and the drain and the active layer.
  • the foregoing step S104 may be implemented by: forming a gate insulating layer, a gate electrode, and an interlayer insulating layer on the active layer, wherein the interlayer insulating layer is located in the gate a via between the source and the drain; then, a via hole is formed on the interlayer insulating layer, the gate insulating layer, and the active layer by a dry etching process; finally, an atomic layer is used And a deposition process in which the conductive ion layer and the single crystal silicon layer/polysilicon layer are formed to overlap.
  • a preferred thickness range may be selected for the thickness of the ohmic contact layer to be deposited: greater than or equal to And less than or equal to
  • the type of conductive ions usually doped in the active layer is mainly boron ions or phosphorus ions.
  • the ions in the conductive ion layer may include: boron ions or phosphorus ions.
  • the conductivity is better.
  • the remaining ions can be considered, and the two ions are not limited.
  • the doping concentration of the ions in the conductive ion layer ranges from 10 14 to 10 18 /cm 3 . It should be noted that this doping concentration conforms to the condition of heavy doping, so that the doped ohmic contact layer satisfies the requirements.
  • boron ions may be preferably used as the conductive ion layer and the single crystal silicon layer/polysilicon layer for atomic layer deposition.
  • the doping concentration threshold is 10 15 /cm 3 .
  • the base substrate may be a flexible substrate.
  • the maximum temperature it can withstand is 400 ° C, while the temperature conditions for the atomic deposition process are only 20-300 ° C. That is, the temperature at which the ohmic contact layer is formed by the atomic layer deposition process is less than 300 ° C, and thus the above method is very suitable for producing a flexible substrate-based LTPS TFT.
  • this also excludes the LTPS TFT which uses the above method to prepare a non-flexible substrate.
  • the embodiment of the present disclosure mainly forms an ohmic contact layer by atomic layer deposition at both ends of the source and the drain (since it is thin and not separately disposed with the active layer, It can be called a transition layer.
  • This method can avoid the damage of high temperature to the flexible substrate, and also avoids a large number of defects caused by ion implantation to the active layer, which is of great significance for the flexible process and mass production of flexible products.
  • the preferred embodiment describes a process for preparing an LTPS TFT on a flexible substrate. Please refer to FIG. 2 to FIG. 4 simultaneously, the process includes the following steps:
  • a flexible substrate 2 is prepared on the glass substrate 1.
  • the flexible substrate may be polyethylene terephthalate (PET) or polyethylene naphthalate (Polethylene naphthalate (PEN), after depositing a flat layer (ie, buffer layer) 3 on the flexible substrate, the flat layer may be a SiOx film layer or a SiNx film layer, or both layers may be used for stack deposition. Its thickness is To Left and right, this can play a better barrier and flattening effect.
  • the deposited a-Si is crystallized by ELA (excimer laser annealing) process.
  • the ELA process can use XeCl laser with a wavelength of 308 nm.
  • the laser overlap ratio is between 90% and 98%.
  • the a-Si is reconstituted under the action of laser energy to become a polysilicon (poly-Si) layer as the active layer 4 of the device.
  • this step is optional, that is, in the actual process, this step can be omitted.
  • the gate insulating layer 5 may be an SiOx film layer or a SiNx film layer, or may be a superposition of the two, and a thickness range thereof. Allowable To Between, of course, the thickness can be selected according to specific process conditions.
  • the gate electrode is patterned by the exposure, development, and etching processes to form the gate metal layer 6.
  • an inter-layer Dielectric layer (ILD) 7 needs to be deposited by a PECVD process, and the thickness thereof may be To Between the deposition materials may be SiOx or SiNx, or a combination of the two, these deposition processes are completed below 400 ° C.
  • a via hole 8 for forming a source/drain electrode is etched at the source and drain positions by a dry etch process, and the via hole 8 is in communication with the poly-Si of the active layer 4.
  • S/D doping where S is the source source, D is the drain Drain
  • RTA above 600 °C Rapid Thermal Annealing
  • FIG. 2 is a schematic structural view after forming an SD through hole according to a preferred embodiment of the present disclosure.
  • a transition layer between the source and the drain (herein referred to as a transition layer, ie, the above ohmic contact layer) 10, and the deposition thickness is To between. Since the deposition material is single crystal silicon or polycrystalline silicon, good contact with the active layer can be formed, and atomic level deposition precision during atomic layer deposition is very high, so that interface defects can be sufficiently repaired to form a good ohmic contact.
  • ALD atomic layer deposition
  • transition layer 10 After the transition layer 10 is deposited, the patterning of the transition layer 10 is completed by an exposure, development, and etching process, so that the heavily doped material deposited by the ALD process is in close contact with the active layer 4 in the via hole 8. .
  • FIG. 3 is a schematic structural view after forming an ohmic contact layer in accordance with a preferred embodiment of the present disclosure.
  • a source-drain electrode is deposited by a magnetron sputtering device, wherein the electrode thickness can be To Between, the material used may be a metal such as Al, Mo, Cu, W, or a combination or combination of these metals. Thereafter, exposure, development, and etching are performed in three steps to pattern the electrodes. At this point, the LTPS thin film transistor on the flexible substrate is completed.
  • FIG. 4 is a schematic structural view of the final formation of the LTPS TFT according to a preferred embodiment of the present disclosure.
  • the source and the drain is not required, the contamination of the device by the ion implantation process and a large number of defects for the active layer are avoided, and high-temperature activation after ion implantation is not required, and the low
  • the deposition temperature is fully compatible with the flexible process. Since atomic layer deposition can accurately ensure complete anastomosis at the contact interface, it is possible to deposit heavily doped single crystal silicon or polycrystalline silicon at a low temperature to form a good ohmic contact with the source and drain metals.
  • the embodiment of the present disclosure further provides a low-temperature polysilicon thin film transistor (the description is not described herein with reference to the accompanying drawings, and the preparation process thereof can be referred to Referring to FIG. 2 to FIG. 4), the low temperature polysilicon thin film transistor includes:
  • An active layer disposed on the base substrate
  • An ohmic contact layer disposed on the active layer, the ohmic contact layer comprising a plurality of conductive ion layers and a plurality of single crystal silicon layers/polysilicon layers, wherein the ohmic contact layer is formed by an atomic layer deposition process Formed on the active layer;
  • a source and a drain disposed on the ohmic contact layer, the source and the drain being in contact with the active layer through the ohmic contact layer.
  • the ions in the conductive ion layer may include: boron ions or phosphorus ions; the doping concentration of ions in the conductive ion layer may range from 10 14 to 10 18 /cm 3 . In the case where the ions in the conductive ion layer are boron ions, the doping concentration threshold is 10 15 /cm 3 .
  • the base substrate may be a flexible substrate, and the ohmic contact layer is formed using the atomic layer deposition process at a temperature of less than 300 ° C.
  • the ALD deposition requires only a temperature condition of 20-300 ° C, which is much lower than the upper temperature limit of the flexible substrate, the precise deposition process makes the interface contact good, and at the same time, a better ohmic contact can be obtained, and the flexibility is greatly improved.
  • the device characteristics of the LTPS TFT on the substrate are of great significance for the flexible display technology using LTPS.

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Abstract

一种低温多晶硅薄膜晶体管及其制备方法。其中，该方法包括：在衬底基板（1）上形成有源层（4）；利用原子层沉积工艺在所述有源层（4）上形成欧姆接触层（10），其中，所述欧姆接触层（10）包括多个导电离子层和多个单晶硅层/多晶硅层；在所述欧姆接触层上形成源极和漏极，所述源极和所述漏极通过所述欧姆接触层（10）与所述有源层（4）接触。

Description

低温多晶硅薄膜晶体管及其制备方法
相关申请的交叉引用
本申请主张在2015年6月23日在中国提交的中国专利申请号No.201510350156.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其是涉及一种低温多晶硅薄膜晶体管及其制备方法。
背景技术
与非晶硅(a-Si)薄膜晶体管(thin film transistor，TFT)相比，低温多晶硅薄膜晶体管(Low Temperature Poly-silicon TFT，LTPS TFT)技术具备诸多优点，如迁移率很高，可达到10-100cm2/Vs左右，同时可以在较低温条件(低于600℃)下制备而成，基底选择灵活，制备成本较低等。由于LTPS TFT的诸多优良特性在制备柔性显示器方面具备明显优势，因此已经成为业内柔性显示生产中的最重要材料。
目前，在非柔性的玻璃基底上制备LTPS TFT的工艺过程中，为了使源极、漏极和LTPS有源层之间形成良好的欧姆接触，需要先在LTPS有源层的源漏区域用离子注入工艺进行重掺杂，以达到降低接触电阻的目的，从而能够获得较好的TFT电学特性。值得注意的是，重掺杂之后必须经过600℃以上的高温活化(高温退火)才能基本消除掺杂给有源层带来的大量缺陷。
然而，由于目前的柔性工艺温度上限是400℃，因此无法完成离子注入工艺之后的高温活化，导致采用上述非柔性基板TFT制备工艺形成的柔性基板LTPS TFT的器件特性很差，无法避免重掺杂所产生的大量缺陷。
针对上述技术问题，现有技术中并没有提供一种有效的解决方案。
发明内容
本公开的主要目的在于提供一种可以在低于400℃的温度条件下，即可以完成在柔性基板上形成LTPS TFT器件，而避免离子注入工艺和高温活化造成LTPS TFT器件性能较差的技术方案。
为了达到上述目的，本公开提供了一种低温多晶硅薄膜晶体管制备方法， 包括：在衬底基板上形成有源层；利用原子层沉积工艺在所述有源层上形成欧姆接触层，其中，所述欧姆接触层包括多个导电离子层和多个单晶硅层/多晶硅层；在所述欧姆接触层上形成源极和漏极，所述源极和所述漏极通过所述欧姆接触层与所述有源层接触。
可选地，形成所述欧姆接触层的步骤包括：在所述有源层上形成栅绝缘层、栅极以及层间绝缘层，其中，所述层间绝缘层位于所述栅极与所述源极和所述漏极之间；利用干刻工艺，在所述层间绝缘层、所述栅绝缘层以及所述有源层上形成通孔；利用原子层沉积工艺，在所述通孔中交叠形成所述导电离子层和所述单晶硅层/多晶硅层。
可选地，所述欧姆接触层的厚度大于等于
Figure PCTCN2015092001-appb-000001
且小于等于
Figure PCTCN2015092001-appb-000002
可选地，所述导电离子层中的离子包括：硼离子或磷离子。
可选地，所述导电离子层中离子的掺杂浓度的范围为：1014～1018个/cm3。
可选地，在所述导电离子层中的离子为硼离子的情况下，所述掺杂浓度阈值为1015个/cm3。
可选地，衬底基板为柔性基板。
可选地，利用所述原子层沉积工艺形成所述欧姆接触层时的温度小于300℃。
本公开还提供了一种低温多晶硅薄膜晶体管，包括：衬底基板；设置在所述衬底基板上的有源层；设置在所述有源层上的欧姆接触层，所述欧姆接触层包括多个导电离子层和多个单晶硅层/多晶硅层，其中，所述欧姆接触层是利用原子层沉积工艺在所述有源层上形成的；设置在所述欧姆接触层上的源极和漏极，所述源极和所述漏极通过所述欧姆接触层与所述有源层接触。
可选地，所述导电离子层中的离子包括：硼离子或磷离子；所述导电离子层中离子的掺杂浓度的范围为：1014～1018个/cm3。
可选地，在所述导电离子层中的离子为硼离子的情况下，所述掺杂浓度阈值为1015个/cm3。
可选地，衬底基板为柔性基板，所述欧姆接触层是利用所述原子层沉积工艺在温度小于300℃的情况下形成的。
与现有技术相比，本公开所述的低温多晶硅薄膜晶体管及其制备方法， 可以克服采用离子注入和高温活化工艺在柔性基板形成的LTPS TFT器件性能较差的缺陷，只需在柔性基板的温度上限之下的较低温度条件下，可以精确地形成介质面接触良好的欧姆接触层，从而大大提高柔性基板上LTPS TFT器件的性能。
附图说明
图1是根据本公开实施例的低温多晶硅薄膜晶体管制备方法示意图；
图2是根据本公开实施例的形成SD通孔后的结构示意图；
图3是根据本公开实施例的形成欧姆接触层后的结构示意图；以及
图4是根据本公开实施例的最终形成LTPS TFT的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域的普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
目前，在柔性基板上制备LTPS TFT的过程中，如果为了在源极、漏极和LTPS有源层之间形成良好的欧姆接触，需要采用离子注入工艺在源极、漏极和LTPS有源层之间形成重掺杂区域，同时需要在较高温度下进行长时间(例如，2小时以上)的高温活化。由于高温活化的温度最低应该在600℃以上，柔性基板能承受的最高温度在400℃左右，而400℃的温度条件下几乎没有活化作用，导致目前的柔性显示器背板活化效果很差，使得掺杂造成的 缺陷无法修复，从而造成LTPS TFT器件的电学特性无法达标。
为了克服上述缺陷，本公开主要通过应用ALD(Atomic Layer Deposition，原子层沉积)方法在源极和漏极形成一个欧姆接触良好的欧姆接触层。由于ALD工艺的温度条件在400摄氏度以下，而且该工艺的沉积精度较高，因此可以取代离子注入和高温活化两个步骤。通过在源极和漏极前先沉积一层高掺杂的单晶硅或者多晶硅，然后再用磁控溅射设备(sputter)沉积源极和漏极金属，在柔性基板上形成LTPS TFT器件，从而解决了使用现有的离子注入和高温活化工艺在柔性基板上形成的LTPS TFT器件性能过差的问题。
本公开实施例提供了一种低温多晶硅薄膜晶体管制备方法。图1是根据本公开实施例的低温多晶硅薄膜晶体管制备方法示意图。如图1所示，该流程包括以下步骤(步骤S102-步骤S106)：
步骤S102、在衬底基板上形成有源层；
步骤S104、利用原子层沉积工艺在所述有源层上形成欧姆接触层，其中，所述欧姆接触层包括多个导电离子层和多个单晶硅层/多晶硅层；
步骤S106、在所述欧姆接触层上形成源极和漏极，所述源极和所述漏极通过所述欧姆接触层与所述有源层接触。
通过上述步骤，无需进行离子注入和高温活化，而采用原子层沉积工艺直接进行离子掺杂，从而在源极和漏极与有源层之间形成欧姆接触良好的欧姆接触层。
在本公开实施例中，上述步骤S104可以采用这样的方式实现：先在所述有源层上形成栅绝缘层、栅极以及层间绝缘层，其中，所述层间绝缘层位于所述栅极与所述源极和所述漏极之间；接着，利用干刻工艺，在所述层间绝缘层、所述栅绝缘层以及所述有源层上形成通孔；最后，利用原子层沉积工艺，在所述通孔中交叠形成所述导电离子层和所述单晶硅层/多晶硅层。
由于原子层沉积工艺的沉积具有精确度高的特点，因此只需要沉积很薄的一层欧姆接触层即可以保证源极和漏极之间具有较高的电子迁移率。在本实施例中，为了达到较好的效果，可以为需要沉积的所述欧姆接触层的厚度选择一个较优的厚度范围：大于等于
Figure PCTCN2015092001-appb-000003
且小于等于
Figure PCTCN2015092001-appb-000004
目前，通常在有源层中掺杂的导电离子的种类主要是硼离子或磷离子， 而本公开实施例仍然可以采用这两种离子，也就是说，在本公开实施例中，可选地，所述导电离子层中的离子可以包括：硼离子或磷离子。当然，虽然目前只是这两种离子掺杂进有源层后导电率较好，但在实际应用中随着技术的发展，其余离子都是可以考虑的，并不以这两种离子为限。
在本公开实施例中，所述导电离子层中离子的掺杂浓度的范围为：1014～1018个/cm3。需要说明的是，这个掺杂浓度符合重掺杂的条件，从而使掺杂形成的欧姆接触层满足要求。
进一步地，为了简化工艺和增强上述欧姆接触层的导电率，可以优选硼离子作为导电离子层与单晶硅层/多晶硅层进行原子层沉积。在所述导电离子层中的离子为硼离子的情况下，所述掺杂浓度阈值为1015个/cm3。
在本公开实施例中，衬底基板可以为柔性基板。对于柔性基板来说，其所能承受的最高温度是400℃，而原子沉积工艺的温度条件只需在20-300℃。也就是说，利用所述原子层沉积工艺形成所述欧姆接触层时的温度是小于300℃的，因此对于生产基于柔性基板的LTPS TFT来说，上述方法是非常适合的。当然，这并排除采用上述方法来制备非柔性基板的LTPS TFT。
由此可见，对于柔性基板的LTPS TFT的制备工艺来说，本公开实施例主要通过在源漏极两端通过原子层沉积形成欧姆接触层(由于很薄且未与有源层独立设置，也可以称之为过渡层)，这种方法可以避免高温对柔性基板的伤害，同时也避免了离子注入给有源层带来的大量缺陷，对于柔性工艺及柔性产品的量产具有重大意义。
以下结合图2至图4以及优选实施例对上述实施例提供的低温多晶硅薄膜晶体管制备方法进行更加详细的描述。
优选实施例
首先需要说明的是，本优选实施例是对在柔性基板上制备LTPS TFT的过程进行说明的，请同时参考图2至图4，该过程包括以下几个步骤：
(1)在玻璃基板1上制备一层柔性基板2，在实际应用中，该柔性基板可以是聚对苯二甲酸乙二醇酯(polyethylene terephthalate，PET)或聚萘二甲酸乙二醇酯(polyethylene naphthalate，PEN)，之后在柔性基板上沉积一层平坦层(即buffer层)3，该平坦层可以是SiOx膜层或SiNx膜层，也可以同时 使用这两种膜层，进行堆叠沉积，其厚度在
Figure PCTCN2015092001-appb-000005
到
Figure PCTCN2015092001-appb-000006
左右，这样可以起到更好的阻挡层和平坦化作用。
(2)在buffer层3上利用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)方法沉积一层a-Si，沉积温度控制在400℃以下，厚度为
Figure PCTCN2015092001-appb-000007
随后在接近400℃的温度条件下进行100分钟以上时间的去氢退火。
(3)用ELA(准分子激光退火)工艺，对沉积的a-Si进行结晶处理，ELA工艺可以采用波长308nm的XeCl激光，激光重叠率在90％到98％之间，经过ELA工艺之后，a-Si在激光能量作用下发生重构，成为多晶硅(poly-Si)层，作为器件的有源层4。
(4)利用离子注入工艺对poly-Si层进行channel dopping(沟道掺杂)，以修正器件的阈值电压，增强器件的稳定性。需要特别说明的是，在本优选实施例中，该步骤是可选的，即在实际工艺中，这一步可以省略。
(5)用PECVD在已经完成的有源层4上方沉积栅绝缘层(GI)5，该栅绝缘层5可以是SiOx膜层或者SiNx膜层，也可以是这两者的叠加，其厚度范围可以在
Figure PCTCN2015092001-appb-000008
到
Figure PCTCN2015092001-appb-000009
之间，当然，厚度可以根据具体的工艺条件选择。
(6)利用磁控溅射设备(sputter)沉积栅电极(Gate)，其厚度在
Figure PCTCN2015092001-appb-000010
到
Figure PCTCN2015092001-appb-000011
之间，使用的材料可以是Al、Mo、Cu、W等金属，也可以是这些金属的叠加或组合。沉积完成后，利用曝光、显影和刻蚀工艺，完成Gate电极的图形化，形成栅极金属层6。
(7)在栅极金属层6形成之后，为了防止其与源漏电极之间形成短路，需要采用PECVD工艺沉积一个层间绝缘层(Inter-layer Dielectric layer，ILD)7，其厚度可以在
Figure PCTCN2015092001-appb-000012
到
Figure PCTCN2015092001-appb-000013
之间，沉积材料可以是SiOx或SiNx，也可以是两者的叠加，这些沉积过程都在400℃以下完成。
(8)利用干刻(dry etch)工艺，在源极和漏极位置处刻蚀出用于形成源漏电极的通孔8，通孔8和有源层4的poly-Si连通。需要注意的是，在非柔性工艺中，在执行这一步之前，还需要经过S/D doping(其中，S是源极Source，D是漏极Drain)和高于600℃的RTA(Rapid Thermal Annealing)活 化处理，以形成良好的欧姆接触。但是，本优选实施例中省略了这些步骤，更加适用于柔性基板工艺。
此处，为便于理解上述步骤，可以重点参考图2，图2是根据本公开优选实施例的形成SD通孔后的结构示意图。
(9)利用原子层沉积(ALD)工艺，在低于300℃的低温条件下沉积一层重掺杂(掺杂的材料为硼原子，掺杂后形成导电的硼离子)的单晶硅或者多晶硅作为源极和漏极的过渡层(此处称为过渡层，即上述欧姆接触层)10，沉积厚度在
Figure PCTCN2015092001-appb-000014
到
Figure PCTCN2015092001-appb-000015
之间。由于沉积材料是单晶硅或者多晶硅，可以和有源层形成良好的接触，同时原子层沉积过程中原子级的沉积精度非常高，从而可以充分修补界面缺陷最终形成良好的欧姆接触。
(10)在沉积完过渡层10之后，利用曝光、显影和刻蚀工艺，完成过渡层10的图形化，使得采用ALD工艺沉积的重掺杂材料在通孔8中和有源层4紧密接触。
此处，为便于理解，可以重点参考图3，图3是根据本公开优选实施例的形成欧姆接触层后的结构示意图。
(11)过渡层10完成图形化之后，利用磁控溅射设备(sputter)沉积源漏电极，其中，电极厚度可以在
Figure PCTCN2015092001-appb-000016
到
Figure PCTCN2015092001-appb-000017
之间，使用的材料可以是Al、Mo、Cu、W等金属，也可以是这些金属的叠加或组合。之后，再进行曝光、显影、刻蚀三个步骤，将电极图案化。至此，柔性基板上的LTPS薄膜晶体管就制造完成了。
此处，为便于理解，可以重点参考图4，图4是根据本公开优选实施例的最终形成LTPS TFT的结构示意图。
本优选实施例，不需要进行源极和漏极的重掺杂，避免了离子注入工艺对器件的污染和给有源层带来的大量缺陷，不需要进行离子注入后的高温活化，低的沉积温度和柔性工艺完全兼容。由于原子层沉积可以很精确地保证接触界面处的完全吻合，同时可以在低温下沉积重掺杂的单晶硅或者多晶硅，与源、漏极金属形成良好的欧姆接触。
对应于上述低温多晶硅薄膜晶体管制备方法，本公开实施例还提供了一种低温多晶硅薄膜晶体管(此处不再结合附图进行描述，其制备过程可以参 考图2至图4)，该低温多晶硅薄膜晶体管包括：
衬底基板；
设置在所述衬底基板上的有源层；
设置在所述有源层上的欧姆接触层，所述欧姆接触层包括多个导电离子层和多个单晶硅层/多晶硅层，其中，所述欧姆接触层是利用原子层沉积工艺在所述有源层上形成的；
设置在所述欧姆接触层上的源极和漏极，所述源极和所述漏极通过所述欧姆接触层与所述有源层接触。
在本公开实施例中，所述导电离子层中的离子可以包括：硼离子或磷离子；所述导电离子层中离子的掺杂浓度的范围可以为：1014～1018个/cm3，在所述导电离子层中的离子为硼离子的情况下，所述掺杂浓度阈值为1015个/cm3。
在本公开实施例中，衬底基板可以为柔性基板，所述欧姆接触层是利用所述原子层沉积工艺在温度小于300℃的情况下形成的。
通过本公开实施例，由于ALD沉积只需要20-300℃的温度条件，大大低于柔性基板的温度上限，精确的沉积过程使得介面接触良好，同时还可以取得更好的欧姆接触，大幅提升柔性基板上LTPS TFT的器件特性，对运用LTPS的柔性显示技术意义重大。
以上所述是本公开的优选实施方式，应当指出，对于本领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为包含在本公开的保护范围之内。

Claims (12)

  1. 一种低温多晶硅薄膜晶体管的制备方法，包括：
    在衬底基板上形成有源层；
    利用原子层沉积工艺在所述有源层上形成欧姆接触层，其中，所述欧姆接触层包括多个导电离子层和多个单晶硅层/多晶硅层；
    在所述欧姆接触层上形成源极和漏极，所述源极和所述漏极通过所述欧姆接触层与所述有源层接触。
  2. 根据权利要求1所述的制备方法，其中，形成所述欧姆接触层的步骤包括：
    在所述有源层上形成栅绝缘层、栅极以及层间绝缘层，其中，所述层间绝缘层位于所述栅极与所述源极和所述漏极之间；
    利用干刻工艺，在所述层间绝缘层、所述栅绝缘层以及所述有源层上形成通孔；
    利用原子层沉积工艺，在所述通孔中交叠形成所述导电离子层和所述单晶硅层/多晶硅层。
  3. 根据权利要求1所述的制备方法，其中，所述欧姆接触层的厚度大于等于
    Figure PCTCN2015092001-appb-100001
    且小于等于
    Figure PCTCN2015092001-appb-100002
  4. 根据权利要求1至3中任一项所述的制备方法，其中，所述导电离子层中的离子包括：硼离子或磷离子。
  5. 根据权利要求4所述的制备方法，其中，
    所述导电离子层中离子的掺杂浓度的范围为：1014～1018个/cm3。
  6. 根据权利要求5所述的制备方法，其中，
    在所述导电离子层中的离子为硼离子的情况下，所述掺杂浓度阈值为1015个/cm3。
  7. 根据权利要求1所述的制备方法，其中，衬底基板为柔性基板。
  8. 根据权利要求7所述的制备方法，其中，利用所述原子层沉积工艺形成所述欧姆接触层时的温度小于300℃。
  9. 一种低温多晶硅薄膜晶体管，包括：
    衬底基板；
    设置在所述衬底基板上的有源层；
    设置在所述有源层上的欧姆接触层，所述欧姆接触层包括多个导电离子层和多个单晶硅层/多晶硅层，其中，所述欧姆接触层是利用原子层沉积工艺在所述有源层上形成的；
    设置在所述欧姆接触层上的源极和漏极，所述源极和所述漏极通过所述欧姆接触层与所述有源层接触。
  10. 根据权利要求9所述的低温多晶硅薄膜晶体管，其中，
    所述导电离子层中的离子包括：硼离子或磷离子；
    所述导电离子层中离子的掺杂浓度的范围为：1014～1018个/cm3。
  11. 根据权利要求10所述的低温多晶硅薄膜晶体管，其中，
    在所述导电离子层中的离子为硼离子的情况下，所述掺杂浓度阈值为1015个/cm3。
  12. 根据权利要求9-11任一项所述的低温多晶硅薄膜晶体管，其中，衬底基板为柔性基板，所述欧姆接触层是利用所述原子层沉积工艺在温度小于300℃的情况下形成的。
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