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US4507675A - Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor - Google Patents

Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor Download PDF

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Publication number
US4507675A
US4507675A US06/352,119 US35211982A US4507675A US 4507675 A US4507675 A US 4507675A US 35211982 A US35211982 A US 35211982A US 4507675 A US4507675 A US 4507675A
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United States
Prior art keywords
substrate support
strips
plastic
lead frame
external leads
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US06/352,119
Inventor
Hiroyuki Fujii
Kenichi Tateno
Mikio Nishikawa
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Panasonic Holdings Corp
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Matsushita Electronics Corp
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Assigned to MATSUSHITA ELECTRONICS CORPORATION reassignment MATSUSHITA ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: FUJII, HIROYUKI, NISHIKAWA, MIKIO, TATENO, KENICHI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Definitions

  • the present invention relates to a method for manufacturing a plastic encapsulated semiconductor device which can be used with relatively large power and a lead frame therefor.
  • Plastic encapsulated semiconductor devices are superior to metal encapsulated semiconductor devices in ease of mass production and manufacturing costs. However, the plastic encapsulated semiconductor devices are inferior to the metal encapsulated semiconductor devices in radiation of heat when they are operated. Plastic encapsulation of semiconductor devices has recently been developed. A high power transistor manufactured by plastic encapsulation has been proposed. In this case, sufficient consideration is taken to allow the radiation of heat.
  • the lower surface of the substrate support is not covered with plastic but exposed.
  • the substrate support is mounted on a radiator to radiate heat.
  • the substrate support must be electrically insulated from the radiator. The assembly operation of the semiconductor device on the radiator through an insulating plate is complicated and cumbersome.
  • a plastic encapsulated power transistor wherein a thin plastic layer is formed on the lower surface of the substrate support during plastic encapsulation and an insulating plate is not required for mounting the power transistor on the radiator.
  • plastic is injected while the substrate support is floating in a cavity defined by the molds.
  • the substrate support may be bent in the cavity due to the injection pressure of the plastic.
  • it is very difficult to encapsulate in plastic while keeping the substrate support in a proper position, thus, resulting in non-uniformity in the thickness of the plastic layer on the lower surface of the substrate support and degrading radiation characteristics.
  • a method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor wherein a semiconductor device assembly is formed, using a lead frame an external lead of which extends to one side of a substrate support serving as a heat sink and supporting a semiconductor substrate, and strips of which extend to the other end of the substrate support; the external lead and strips are clamped by upper and lower molds for plastic encapsulation; and a connecting portion between the external lead and a connecting band and the strips extending from a plastic encapsulating housing to the outside are cut.
  • the plastic layer of a desired thickness is formed and with high precision.
  • FIGS. 1 and 2 are sectional views showing the structures of conventional plastic encapsulated power transistors, respectively;
  • FIG. 3 is a plan view of a conventional lead frame
  • FIG. 4 is a view illustrating the state of plastic encapsulation for forming the plastic encapsulated power transistor of FIG. 2 using the lead frame of FIG. 3;
  • FIGS. 5A and 5B are a plan view and a sectional view respectively, of a lead frame according to one embodiment of the present invention.
  • FIGS. 6, 7 and 8 are views illustrating the plastic encapsulation process to the completion of manufacture according to a method for manufacturing the plastic encapsulated semiconductor device of the present invention.
  • FIG. 1 is a sectional view of a conventional power transistor of the plastic encapsulated structure.
  • the lower surface of a substrate support 2 on which a transistor element 1 is adhered is not covered with a plastic encapsulating housing 3 but exposed.
  • a through hole 4 is formed for mounting the power transistor on the radiator with a screw.
  • Reference numeral 5 denotes a protective plastic portion and reference numeral 6 denotes an external lead.
  • the heat radiation effect is guaranteed.
  • the insulating plate must be inserted between the radiator and the substrate support when the substrate support is to be mounted on the radiator, resulting in a complicated packaging operation.
  • the insulating plate must be properly inserted between the radiator and the substrate support.
  • the radiator and the substrate support are to be integrally adhered, they may be misaligned. Thus, electrical insulation cannot be guaranteed. Therefore, as shown in FIG. 2, a plastic encapsulated power transistor is proposed wherein a thin plastic layer 7 is formed on the lower surface of the substrate support 2 and the insulating plate is not required.
  • FIG. 3 is a plan view of a lead frame which is conventionally used for packaging the plastic encapsulated power transistor of FIGS. 1 and 2.
  • External leads 6, 10 and 11 of the power transistor extend in one direction from a connecting band 9 on which apertures 8 for determining the feed pitch and positioning the substrate support 2 at the time of plastic encapsulation are formed.
  • the substrate support 2 is connected to the end of the external lead 6.
  • the transistor is packaged in such a manner that the transistor element 1 is adhered, metal wires 12 are connected between the external leads 10 and 11 and electrodes of the transistor element 1 corresponding thereto, and a protective plastic portion 5 is formed.
  • a transistor assembly is obtained, using the lead frame as described above.
  • This transistor assembly is formed into a plastic encapsulated structure shown in FIG. 2 in the following manner.
  • the substrate support 2 of the transistor assembly is floated in a cavity formed between an upper mold 13 and a lower mold 14.
  • Plastic 30 is then injected into the cavity.
  • the plastic 30 is also filled in the cavity immediately under the lower surface of the substrate support 2.
  • the plastic encapsulated semiconductor device of FIG. 2 is manufactured.
  • FIGS. 5A and 5B are views illustrating the structure of a lead frame according to the present invention in which FIG. 5A is a plan view thereof and FIG. 5B is a sectional view thereof along the line Y--Y.
  • Two strips 15 and 16 extend from a side of the substrate support 2 which opposes the side to which the external lead 6 is connected.
  • the strips 15 and 16 are connected to a second connecting band 17.
  • Apertures 18 formed on the second connecting band 17 serve to fit with part of a mold for alignment in the plastic encapsulation process.
  • the thickness of the strips 15 and 16 is smaller than that of the substrate support 2.
  • a predetermined step is formed between the lower surfaces of the strips 15 and 16 and the lower surface of the substrate support 2.
  • FIG. 6 is a view illustrating the state of plastic encapsulation of the transistor assembly formed by using the lead frame according to the present invention.
  • the plastic 30 is injected into the cavity formed between the upper and lower molds 13 and 14 in the same manner as in the conventional plastic encapsulation.
  • the lead frame according to the present invention is used, as shown in the figure, the external lead 6 of the lead frame is clamped by the upper and lower molds 13 and 14 on one side.
  • the strips 15 and 16 and the second connecting band 17 are clamped by the upper and lower molds 13 and 14 on the other side.
  • Projections (not shown) of the upper mold 13 fit in the apertures 8 formed in the first connecting band 9.
  • projections 19 of the upper mold 13 fit in the apertures 18 of the second connecting band 17.
  • Reference numeral 20 denotes a projection of the upper mold 13 which forms a through hole for mounting the semiconductor device to a radiator with a screw.
  • the substrate support 2 of the lead frame is supported by the external lead 6 and the strips 15 and 16 which are clamped by the upper and lower molds 13 and 14, and thus floats in the cavity of the molds.
  • the first and second connecting bands 9 and 17 are clamped by the upper and lower molds 13 and 14, as described above. Further, since the projections of the upper mold 13 are fitted in the apertures formed in the first and second connecting bands 9 and 17, the first and second bands 9 and 17 are not allowed to move horizontally. Thus, the floating condition of the substrate support 2 is properly controlled.
  • FIG. 7 is a perspective view illustrating the condition after the plastic encapsulation is completed.
  • the plastic encapsulating housing has a thin portion 21 in which the through hole 4 for a screw is disposed and a thick portion 22.
  • a step is formed between the thin portion 21 and the thick portion 22, so that the head of the screw does not extend upward when the transistor is mounted to the radiator.
  • the strips 15 and 16 and the first connecting band 9 are cut along the line X--X and the line X'--X', respectively.
  • the plastic encapsulated transistor shown in FIG. 8 is manufactured.
  • the cut surfaces of the strips 15 and 16 are exposed outside the plastic encapsulating housing.
  • FIG. 5B since another step is formed between the lower surface of the substrate support 2 and the lower surfaces of the strips 15 and 16, an adequate space is provided between the lower surface of the plastic encapsulating housing which is mounted on the radiator and the cut surfaces of the strips 15 and 16. Therefore, short circuiting does not occur at this portion. Further, since the strips 15 and 16 are thin, they are easily cut.
  • the plastic for plastic capsulation used according to the method of the present invention preferably has high thermal conductivity.
  • the thickness of the plastic layer immediately under the substrate support is preferably 0.3 to 0.5 mm in consideration of heat radiation and electrical insulation. Within the above range of thickness, better results are obtained.
  • a plastic encapsulated semiconductor device which has a thin plastic layer immediately under the substrate support which also serves as the heat sink is manufactured with high precision according to the present invention.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)

Abstract

A method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor. An external lead of a lead frame extends to one side of a substrate support serving as a heat sink and supporting a semiconductor substrate, and strips of the lead frame extend to the other end of the substrate support. The external lead and strips are clamped by upper and lower molds for plastic encapsulation, so that a thin film of plastic is uniformly formed on a lower surface of the substrate support. A connecting portion between the external lead and a connecting band and the strips extending from a plastic encapsulating housing to the outside are cut.

Description

BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to a method for manufacturing a plastic encapsulated semiconductor device which can be used with relatively large power and a lead frame therefor.
II. Description of the Prior Art
Plastic encapsulated semiconductor devices are superior to metal encapsulated semiconductor devices in ease of mass production and manufacturing costs. However, the plastic encapsulated semiconductor devices are inferior to the metal encapsulated semiconductor devices in radiation of heat when they are operated. Plastic encapsulation of semiconductor devices has recently been developed. A high power transistor manufactured by plastic encapsulation has been proposed. In this case, sufficient consideration is taken to allow the radiation of heat.
In a transistor adhered on a metal substrate support and encapsulated by plastic, for example, the lower surface of the substrate support is not covered with plastic but exposed. The substrate support is mounted on a radiator to radiate heat. However, in this case, the substrate support must be electrically insulated from the radiator. The assembly operation of the semiconductor device on the radiator through an insulating plate is complicated and cumbersome.
On the other hand, a plastic encapsulated power transistor is proposed wherein a thin plastic layer is formed on the lower surface of the substrate support during plastic encapsulation and an insulating plate is not required for mounting the power transistor on the radiator. However, in this case, at the time of plastic encapsulation, only the side of the lead frame from which extend the external lead is clamped by the upper and lower molds with a transistor assembly which has the external lead on one side. Plastic is injected while the substrate support is floating in a cavity defined by the molds. Thus, the substrate support may be bent in the cavity due to the injection pressure of the plastic. As a result, it is very difficult to encapsulate in plastic while keeping the substrate support in a proper position, thus, resulting in non-uniformity in the thickness of the plastic layer on the lower surface of the substrate support and degrading radiation characteristics.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor wherein, in manufacturing a plastic encapsulated semiconductor device of a structure which has a thin plastic layer on one surface of a substrate support which also serving as a heat sink, to the other surface of which a semiconductor substrate is adhered, the thickness of the thin plastic layer is uniformly formed and with high precision.
In order to achieve the above object of the present invention, there is provided a method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor wherein a semiconductor device assembly is formed, using a lead frame an external lead of which extends to one side of a substrate support serving as a heat sink and supporting a semiconductor substrate, and strips of which extend to the other end of the substrate support; the external lead and strips are clamped by upper and lower molds for plastic encapsulation; and a connecting portion between the external lead and a connecting band and the strips extending from a plastic encapsulating housing to the outside are cut. Thus, the plastic layer of a desired thickness is formed and with high precision.
The above and other objects and features of the present invention will become apparent from the following detailed description of the preferred embodiments when taken in conjunction with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 and 2 are sectional views showing the structures of conventional plastic encapsulated power transistors, respectively;
FIG. 3 is a plan view of a conventional lead frame;
FIG. 4 is a view illustrating the state of plastic encapsulation for forming the plastic encapsulated power transistor of FIG. 2 using the lead frame of FIG. 3;
FIGS. 5A and 5B are a plan view and a sectional view respectively, of a lead frame according to one embodiment of the present invention; and
FIGS. 6, 7 and 8 are views illustrating the plastic encapsulation process to the completion of manufacture according to a method for manufacturing the plastic encapsulated semiconductor device of the present invention.
DETAILED DESCRIPTION OF THE PRIOR ART
FIG. 1 is a sectional view of a conventional power transistor of the plastic encapsulated structure. The lower surface of a substrate support 2 on which a transistor element 1 is adhered is not covered with a plastic encapsulating housing 3 but exposed. A through hole 4 is formed for mounting the power transistor on the radiator with a screw. Reference numeral 5 denotes a protective plastic portion and reference numeral 6 denotes an external lead. When the plastic encapsulated power transistor with the above structure is to be mounted on the radiator (not shown), the exposed lower surface of the substrate support 2 must be thermally coupled with the radiator but must be electrically insulated therefrom. This electrical insulation may be performed by insertion of an insulating plate such as a mica plate.
With the above structure, the heat radiation effect is guaranteed. However, the insulating plate must be inserted between the radiator and the substrate support when the substrate support is to be mounted on the radiator, resulting in a complicated packaging operation. Furthermore, the insulating plate must be properly inserted between the radiator and the substrate support. When the insulating plate, the radiator and the substrate support are to be integrally adhered, they may be misaligned. Thus, electrical insulation cannot be guaranteed. Therefore, as shown in FIG. 2, a plastic encapsulated power transistor is proposed wherein a thin plastic layer 7 is formed on the lower surface of the substrate support 2 and the insulating plate is not required.
FIG. 3 is a plan view of a lead frame which is conventionally used for packaging the plastic encapsulated power transistor of FIGS. 1 and 2. External leads 6, 10 and 11 of the power transistor extend in one direction from a connecting band 9 on which apertures 8 for determining the feed pitch and positioning the substrate support 2 at the time of plastic encapsulation are formed. As shown in FIG. 3, the substrate support 2 is connected to the end of the external lead 6. As shown in the leftmost transistor, the transistor is packaged in such a manner that the transistor element 1 is adhered, metal wires 12 are connected between the external leads 10 and 11 and electrodes of the transistor element 1 corresponding thereto, and a protective plastic portion 5 is formed.
A transistor assembly is obtained, using the lead frame as described above. This transistor assembly is formed into a plastic encapsulated structure shown in FIG. 2 in the following manner. As shown in FIG. 4, the substrate support 2 of the transistor assembly is floated in a cavity formed between an upper mold 13 and a lower mold 14. Plastic 30 is then injected into the cavity. The plastic 30 is also filled in the cavity immediately under the lower surface of the substrate support 2. Thus, the plastic encapsulated semiconductor device of FIG. 2 is manufactured.
As is apparent from FIG. 4, when the plastic encapsulated structure of FIG. 2 is to be obtained by using the lead frame of FIG. 3, plastic is injected into the cavity while only the side on which the external leads are formed is clamped between the upper and lower molds. The substrate support 2 may be bent within the cavity due to the injection pressure of plastic. Therefore, it is very difficult to dispose the substrate support 2 in a proper position. If the substrate support 2 is bent, the uniform thickness of the thin plastic layer 7 is not obtained. Further, this non-uniformity in thickness directly results in degradation of radiation characteristics.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIGS. 5A and 5B are views illustrating the structure of a lead frame according to the present invention in which FIG. 5A is a plan view thereof and FIG. 5B is a sectional view thereof along the line Y--Y.
Two strips 15 and 16 extend from a side of the substrate support 2 which opposes the side to which the external lead 6 is connected. The strips 15 and 16 are connected to a second connecting band 17. Apertures 18 formed on the second connecting band 17 serve to fit with part of a mold for alignment in the plastic encapsulation process. As shown in FIG. 5B, the thickness of the strips 15 and 16 is smaller than that of the substrate support 2. A predetermined step is formed between the lower surfaces of the strips 15 and 16 and the lower surface of the substrate support 2.
FIG. 6 is a view illustrating the state of plastic encapsulation of the transistor assembly formed by using the lead frame according to the present invention. The plastic 30 is injected into the cavity formed between the upper and lower molds 13 and 14 in the same manner as in the conventional plastic encapsulation. However, when the lead frame according to the present invention is used, as shown in the figure, the external lead 6 of the lead frame is clamped by the upper and lower molds 13 and 14 on one side. At the same time, the strips 15 and 16 and the second connecting band 17 are clamped by the upper and lower molds 13 and 14 on the other side. Projections (not shown) of the upper mold 13 fit in the apertures 8 formed in the first connecting band 9. Simultaneously, projections 19 of the upper mold 13 fit in the apertures 18 of the second connecting band 17. Reference numeral 20 denotes a projection of the upper mold 13 which forms a through hole for mounting the semiconductor device to a radiator with a screw.
According to the present invention, the substrate support 2 of the lead frame is supported by the external lead 6 and the strips 15 and 16 which are clamped by the upper and lower molds 13 and 14, and thus floats in the cavity of the molds. The first and second connecting bands 9 and 17 are clamped by the upper and lower molds 13 and 14, as described above. Further, since the projections of the upper mold 13 are fitted in the apertures formed in the first and second connecting bands 9 and 17, the first and second bands 9 and 17 are not allowed to move horizontally. Thus, the floating condition of the substrate support 2 is properly controlled.
FIG. 7 is a perspective view illustrating the condition after the plastic encapsulation is completed. As shown in the figure, the plastic encapsulating housing has a thin portion 21 in which the through hole 4 for a screw is disposed and a thick portion 22. A step is formed between the thin portion 21 and the thick portion 22, so that the head of the screw does not extend upward when the transistor is mounted to the radiator.
The strips 15 and 16 and the first connecting band 9 are cut along the line X--X and the line X'--X', respectively. Thus, the plastic encapsulated transistor shown in FIG. 8 is manufactured.
In the transistor manufactured according to the method of the present invention, the cut surfaces of the strips 15 and 16 are exposed outside the plastic encapsulating housing. However, as shown in FIG. 5B, since another step is formed between the lower surface of the substrate support 2 and the lower surfaces of the strips 15 and 16, an adequate space is provided between the lower surface of the plastic encapsulating housing which is mounted on the radiator and the cut surfaces of the strips 15 and 16. Therefore, short circuiting does not occur at this portion. Further, since the strips 15 and 16 are thin, they are easily cut.
The plastic for plastic capsulation used according to the method of the present invention preferably has high thermal conductivity. The thickness of the plastic layer immediately under the substrate support is preferably 0.3 to 0.5 mm in consideration of heat radiation and electrical insulation. Within the above range of thickness, better results are obtained.
As is apparent from the above description, a plastic encapsulated semiconductor device which has a thin plastic layer immediately under the substrate support which also serves as the heat sink is manufactured with high precision according to the present invention.

Claims (3)

What is claimed is:
1. In combination, a lead frame and a plastic encapsulated semiconductor device, comprising:
a lead frame comprising:
first and second parallel connecting bands;
a relatively thick substrate support disposed between said connecting bands, said support having opposed upper and lower surfaces;
a plurality of external leads extending from said first connecting band toward said substrate support, at least one of said external leads having an end adjacent said support, another of said external leads being mechanically connected to a first side of said substrate support adjacent said first connecting band;
at least two relatively thin strips disposed substantially parallel to said other of said external leads and mechanically connecting said second connecting band to a second side of said substrate support adjacent said second connecting band and opposite said first side of said substrate support, each of said strips having opposed upper and lower surfaces,
said strips being connected relatively close to the upper surface of said substrate support and relatively remote from the lower surface of said substrate support, so that a step is formed between the lower surface of said substrate support and the adjacent lower surfaces of said strips;
said substrate support being mechanically supported between said first and second connecting bands by means of said other of said external leads and said strips;
a semiconductor element disposed on said substrate support and electrically connected to said external leads; and
a plastic mass surrounding said substrate support and semiconductor element and adjacent portions of said external leads and said strips, the thickness of said plastic mass below said adjacent portions of said strips being substantially greater than the thickness of said plastic mass below said substrate support, whereby the parts of said strips extending from said plastic mass may be readily severed therefrom.
2. A lead frame according to claim 1, wherein the number of strips the ends of which are connected to said substrate support is two.
3. A lead frame according to claim 1, wherein a plurality of apertures are formed in each of said first and second connecting bands at an equal pitch.
US06/352,119 1981-03-05 1982-02-25 Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor Expired - Lifetime US4507675A (en)

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JP3222981A JPS57147260A (en) 1981-03-05 1981-03-05 Manufacture of resin-sealed semiconductor device and lead frame used therefor
JP56-32229 1981-03-05

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JPS57147260A (en) 1982-09-11
EP0059926A1 (en) 1982-09-15
JPS6220705B2 (en) 1987-05-08
EP0059926B1 (en) 1986-10-08
US4637130A (en) 1987-01-20
DE59926T1 (en) 1983-02-03
DE3273693D1 (en) 1986-11-13
CA1174821A (en) 1984-09-25

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