TWM578459U - Power-saving level shifting circuit - Google Patents

Abstract

This creation proposes an energy-saving voltage level converter, which is composed of a latch circuit (1), an output control circuit (2), an input circuit (3), and a mode control switch (4). The latch circuit (1) is used to store the differential input signal from the input circuit (3); the output control circuit (2) is used to control the output signal of the energy-saving voltage level converter; the input circuit (3) is used To provide a differential input signal; the mode control switch (4) is used to control different operation modes of the energy-saving voltage level converter.

The simulation results confirm that the energy-saving voltage level converter proposed by this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. At the same time, it can effectively suppress the competition between the pull-up path and the pull-down path. Therefore, the delay time can be greatly reduced, and short-circuit power loss can be eliminated.

Description

Energy-saving voltage level converter

This creation proposes an energy-saving voltage level converter, which is composed of a latch circuit (1), an output control circuit (2), an input circuit (3), and a mode control switch (4). An electronic circuit that accurately converts voltage levels and effectively avoids competition between pull-up and pull-down paths, thereby reducing power loss.

The voltage level converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transmit signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the voltage level converter is responsible for converting low-voltage working signals into high-voltage working signals. .

FIG. 1 shows a latch-type voltage level converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1 ), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter The inverter (INV) constitutes an energy-saving voltage level converter circuit. The bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the input voltage (V (IN) ) Is also between ground (GND) and the second high potential voltage (VDDL). The input voltage (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected separately. Connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2). Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch No static current is generated in the lock-type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the process of the conventional voltage level converter described above, when the second PMOS transistor (MP2) is approaching on (or off) and when the second NMOS transistor (MN2) is approaching off (or on), There is a phenomenon of contention between the pull-up and pull-down of the potential at the output node (OUT), so the output voltage signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the input voltage (V (IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that the first Two PMOS transistors (MP2) are turned on. Therefore, the output is a first high potential voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower input voltage (V (IN)) during the transition may not be Method to make the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1), and the second NMOS transistor (MN2) to be completely turned on or completely turned off. There is a static current between the high potential voltage (VDDH) and the ground (GND). This static current will increase the power loss.

In addition, the performance of the latch-type voltage level converter is affected by the first high potential voltage (VDDH), because the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The voltage is the first high-potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high-potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch-type voltage level converter operate normally is limited.

Figure 2 shows a mirrored voltage level converter circuit, which is one of the other prior art. The voltage level converter is connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit. The first PMOS transistor (MP1) is in The saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type voltage level converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high-potential voltage (VDDH) changes, the voltage The performance of the level converter will not change much. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor is turned on When (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned off. Continuity. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of this creation is to propose an energy-saving voltage level converter, which can not only accurately and quickly convert a first signal to a second signal, but also effectively suppress the difference between the pull-up path and the pull-down path Competition, which in turn reduces power loss.

This creation proposes an energy-saving voltage level converter, which is composed of a latch circuit (1), an output control circuit (2), an input circuit (3), and a mode control switch (4). The latch circuit (1) is used to store the differential input signal from the input circuit (3); the output control circuit (2) is used to control the output signal of the energy-saving voltage level converter; the input circuit (3) is used To provide a differential input signal; the mode control switch (4) is used to control different operation modes of the energy-saving voltage level converter.

The simulation results confirm that the energy-saving voltage level converter proposed by this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to miniaturization of the device. At the same time, it can also effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power loss.

1‧‧‧ latch circuit

2‧‧‧Output control circuit

3‧‧‧input circuit

4‧‧‧Mode control switch

EN‧‧‧Enable control terminal

N1‧‧‧First Node

N2‧‧‧Second Node

N3‧‧‧ third node

N4‧‧‧ fourth node

N5‧‧‧ fifth node

MP1‧‧‧The first PMOS transistor

MP2‧‧‧Second PMOS transistor

MP3‧‧‧Third PMOS Transistor

MP4‧‧‧Fourth PMOS transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧The third NMOS transistor

MN4‧‧‧Fourth NMOS transistor

MN5‧‧‧Fifth NMOS transistor

GND‧‧‧ Ground

IN‧‧‧first input

V (IN) ‧‧‧First Signal

INB‧‧‧Second Input

I1‧‧‧first inverter

OUT‧‧‧output

V (OUT) ‧‧‧Second signal

VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧The second highest power supply voltage

Fig. 1 is a circuit diagram showing a voltage level converter in the first prior art; Fig. 2 is a circuit diagram showing a voltage level converter in the second prior art; FIG. 3 is a circuit diagram showing the energy-saving voltage level converter of the preferred embodiment of the present invention; FIG. 4 is a timing diagram of the transient analysis of the first signal and the second signal of the preferred embodiment of the present invention;

According to the above purpose, the present invention proposes an energy-saving voltage level converter, as shown in FIG. 3, which is composed of a latch circuit (1), an output control circuit (2), an input circuit (3) and a A mode control switch (4), wherein the latch circuit (1) is used to store a differential input signal from the input circuit (3); the output control circuit (2) is used to control the energy-saving voltage level conversion Output signal of the converter; the input circuit (3) is used to provide a differential input signal; the mode control switch (4) is used to control different operation modes of the energy-saving voltage level converter; the latch circuit (1) is provided by A first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1) and a second NMOS transistor (MN2), wherein the first PMOS transistor The source of (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the first The source of two PMOS transistors (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is Connected to the second node (N2); the source of the first NMOS transistor (MN1) is connected to the third node (N3), its gate is connected to the second input terminal (INB), and its sink The pole is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the fourth node (N4), and the gate is connected to the first input terminal (IN), and Its drain is connected to the second node (N2); the output control circuit (2) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), where the first The source of the three PMOS transistor (MP3) is connected to the first high power supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain The source is connected to the first node (N1); the source of the fourth PMOS transistor (MP4) is connected to the first high power supply voltage (VDDH), and the gate is connected to the second input terminal (INB) ), And its drain is connected to the second node (N2); the input circuit (3) is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a first inverter A phaser (I1), wherein the source of the third NMOS transistor (MN3) is connected to the fifth node (N5), its gate is connected to the first input terminal (IN), and its drain is Is connected to the third node (N3); the source of the fourth NMOS transistor (MN4) is connected to the fifth node (N5), its gate is connected to the second input terminal (INB), and its The drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V (IN)), and Provide a signal that is opposite to the first signal (V (IN)); the mode control switch (4) is composed of a fifth NMOS transistor (MN5), the source of which is connected to the ground (GND), and The gate is connected to the enable control terminal (EN), and its drain is connected to the fifth node (N5). Connected; the first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the energy-saving voltage level converter, and the second high power supply voltage (VDDL) is used to provide the power-saving voltage level The second high power supply voltage required by the quasi-converter. The level of the second high power supply voltage (VDDL) is lower than the level of the first high power supply voltage (VDDH). The first signal is between 0 volts. And a rectangular wave between 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage ( VDDL) is 1.2 volts, the first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V (OUT)) is between 0 volts and 1.8 volts Corresponding waveform.

Please refer to Fig. 3 again for the description of the working mode of the voltage level converter. Fig. 3 The working principle is as follows:

(I) Active mode

In the active mode, that is, when the enable control terminal (EN) is in a high potential state, the fifth NMOS transistor (MN5) is in an ON state.

Now consider the steady-state operation of the energy-saving voltage level converter when the first signal (V (IN)) is a logic low level (0 volts): the logic low level on the first input (IN) is simultaneously transmitted to the first An input terminal of an inverter (I1), a gate of the second NMOS transistor (MN2) and a third NMOS transistor (MN3), so that the second NMOS transistor (MN2) and the third NMOS transistor The crystal (MN3) is turned off, and the first inverter (I1) transmits a logic high level (VDDL) to the gate of the first NMOS transistor (MN1) and the gate of the fourth NMOS transistor (MN4). , So that the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are both turned on (ON), at this time, because the second NMOS transistor (MN2) is turned off (OFF), the fourth NMOS transistor The transistor (MN4) is turned on, the potential of the fourth node (N4) is pulled down to a logic low level (0 volts), and the logic low level on the fourth node (N4) is transmitted to the first PMOS circuit. The gate of the crystal (MP1) causes the first PMOS transistor (MP1) to be turned on. At this time, since the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are both turned on, the third NMOS Transistor (MN3) is off, so this The potential of the three node (N3) will be pulled up to a logic high level. The logic high level of the third node (N3) causes the second PMOS transistor (MP2) to be turned off. And the second PMOS transistor (MP2) are both turned off, and the fourth NMOS transistor (MN4) is turned on, so the potential of the fourth node (N4) will be maintained at a logic low level (0 volts), and the output terminal ( The potential of OUT) is maintained at a steady state value at a logic low level (0 volts). In other words, when the first signal (V (IN)) is at a logic low level (0 volts), it is converted into a logic low level (0 volts) by an energy-saving voltage level converter. The second signal is output from the output terminal (OUT).

Consider again the steady-state operation of the energy-saving voltage level converter when the first signal (V (IN)) is the logic high level (VDDL): the logic high level (VDDL) on the first input (IN) is simultaneously transmitted to An input terminal of the first inverter (I1), a gate of the second NMOS transistor (MN2), and a gate of the third NMOS transistor (MN3) make the second NMOS transistor (MN2) and the third The NMOS transistor (MN3) is all turned on, and the first inverter (I1) transmits a logic low level to the gates of the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4), The first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are both turned OFF. At this time, because the third NMOS transistor (MN3) is turned on, the first NMOS transistor (MN1) is turned on. ) OFF, the potential of the third node (N3) is pulled down to a logic low level, and the logic low level on the third node (N3) is transmitted to the gate of the second PMOS transistor (MP2). Electrode, so that the second PMOS transistor (MP2) is turned on. At this time, because the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are both turned on, and the fourth NMOS transistor (MN4) is turned off. And therefore, the fourth node (N4) The bit will be pulled up to a logic high level. The logic high level of the fourth node (N4) causes the first PMOS transistor (MP1) to turn off. At this time, the first PMOS transistor (MP1) and the first The NMOS transistor (MN1) is turned off and the third NMOS transistor (MN3) is turned on. Therefore, the potential of the third node (N3) will be maintained at a logic low level and the potential of the fourth node (N4) It will also be maintained at a logic high level. Therefore, the potential of the output terminal (OUT) will be maintained at a steady state value of a logic high level. In other words, when the first signal (V (IN)) is a logic high level (VDDL), it is converted into a second signal with the first high power supply voltage (VDDH) by the energy-saving voltage level converter, and is output by the output terminal. (OUT) output.

In summary, since the second PMOS transistor (MP2) and the fourth NMOS The transistor (MN4) can be turned on simultaneously in a short time. This work reduces the competition by cutting off the pull-up path corresponding to the second NMOS transistor (MN2). When the fourth NMOS transistor (MN4) is turned on (that is, the pull-down path is enabled), the second NMOS transistor (MN2) cuts off the pull-up path to avoid the difference between the pull-up path and the pull-down path. Competition, therefore, can significantly reduce the delay time and can eliminate short circuit power loss.

(II) Standby mode

Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in a low-potential state, the fifth NMOS transistor (MN5) is in an OFF state. At this time, the voltage level converter stops action. At this time, the input of any first signal (V (IN)) will not affect the value of the second signal (V (OUT)) that has been locked. Its working principle is not repeated here.

The Spice transient analysis simulation results of the energy-saving voltage level converter proposed by this creation are shown in Figure 4. From the simulation results, it can be confirmed that the energy-saving voltage level converter proposed by this creation can not only quickly The first signal is accurately converted into a second signal, and the power loss can be effectively reduced.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims (8)

An energy-saving voltage level converter is used for converting a first signal (V (IN)) into a second signal (V (OUT)), which includes: a first node (N1) for converting a first signal (N1) A drain of a PMOS transistor (MP1), a drain of a first NMOS transistor (MN1), and a drain of a third PMOS transistor (MP3) are connected together; a second node (N2) is used for Connect the drain of a second PMOS transistor (MP2), the drain of a second NMOS transistor (MN2), and the drain of a fourth PMOS transistor (MP4); a third node (N3) To connect the source of the first NMOS transistor (MN1), the drain of a third NMOS transistor (MN3), and the gate of the second PMOS transistor (MP2); a fourth node (N4), used to connect the source of the second NMOS transistor (MN2), the drain of a fourth NMOS transistor (MN4), and the gate of the first PMOS transistor (MP1); The fifth node (N5) is used to connect the source of the third NMOS transistor (MN3), the source of the fourth NMOS transistor (MN4), and the drain of a fifth NMOS transistor (MN5) to Together; a first input terminal (IN) is coupled to the third PMOS transistor (MP3) and the gate of the third NMOS transistor (MN3) are used to provide a first signal (V (IN)); a second input terminal (INB) is coupled to the fourth PMOS transistor ( MP4) and the gate of the fourth NMOS transistor (MN4) to provide an inverted signal of the first signal (V (IN)); an output terminal (OUT) is coupled to the fourth node (N4) ) To output the second signal (V (OUT)); a first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V (IN) ), And provide a signal opposite to the first signal (V (IN)); the uniform energy control terminal (EN) is coupled to the gate of the fifth NMOS transistor (MN5) to provide uniform energy Signal; a first high power supply voltage (VDDH), coupled to the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS The source of the transistor (MP4) is used to provide the first high potential voltage required by the energy-saving voltage level converter; a second high power supply voltage (VDDL) is used to provide the energy-saving voltage level converter. The second highest potential voltage required, the second highest power supply voltage (VDDL) The potential is less than the first high power supply voltage (VDDH); a latch circuit (1) is used to save the differential input signal from an input circuit (3); an output control circuit (2) is used to Controlling an output signal of the energy-saving voltage level converter; an input circuit (3) coupled to the first input terminal (IN) for providing a differential input signal; and a mode control switch (4) for Control different operation modes of the energy-saving voltage level converter. The energy-saving voltage level converter according to item 1 of the scope of patent application, wherein the latch circuit (1) includes: a first PMOS transistor (MP1) whose source is connected to the first high power supply voltage ( VDDH), whose gate is connected to the fourth node (N4), and whose drain is connected to the first node (N1); a second PMOS transistor (MP2), whose source is connected to the first High power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); a first NMOS transistor (MN1), its source Connected to the third node (N3), its gate is connected to the second input terminal (INB), and its drain is connected to the first node (N1); and a second NMOS transistor (MN2) Its source is connected to the fourth node (N4), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2). The energy-saving voltage level converter according to item 2 of the scope of patent application, wherein the output control circuit (2) includes: a third PMOS transistor (MP3) whose source is connected to the first high power supply voltage ( VDDH), whose gate is connected to the first input terminal (IN), and whose drain is connected to the first node (N1); and a fourth PMOS transistor (MP4), whose source is connected to the The first high power supply voltage (VDDH) has a gate connected to the second input terminal (INB) and a drain connected to the second node (N2). The energy-saving voltage level converter according to item 3 of the scope of patent application, wherein the input circuit (3) includes: a third NMOS transistor (MN3), the source of which is connected to the fifth node (N5), and The gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); a fourth NMOS transistor (MN4), and its source is connected to the fifth node (N5) ), Its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); and a first inverter (I1) is coupled to the first input The terminal (IN) is used to receive the first signal (V (IN)) and provide a signal that is opposite to the first signal (V (IN)). The energy-saving voltage level converter according to item 4 of the scope of patent application, wherein the mode control switch (4) is composed of the fifth NMOS transistor (MN5), and its source is connected to the ground (GND). The gate is connected to the enable control terminal (EN), and its drain is connected to the fifth node (N5). The energy-saving voltage level converter according to item 1 of the scope of patent application, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL). The energy-saving voltage level converter according to item 6 of the patent application scope, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH). The energy-saving voltage level converter according to item 7 of the patent application scope, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).