TWM576366U - Level conversion circuit with auxiliary circuit - Google Patents

Abstract

This creation proposes a level conversion circuit with an auxiliary circuit, which is composed of an input circuit (1), a potential conversion circuit (2), and an output control transistor (3), where the input circuit (1) Is coupled to a first input terminal (IN) for providing a differential input signal; the potential conversion circuit (2) is coupled to the first high power supply voltage (VDDH) for potential conversion; The output control transistor (3) is coupled to the first input terminal (IN) to control the output potential of the first node (N1).

The level conversion circuit with an auxiliary circuit proposed in this creation cuts the corresponding pull-up path through the third NMOS transistor (MN3) to reduce competition. When the second NMOS transistor (MN2) is turned on, the third NMOS transistor (MN3) cuts off the pull-up path to avoid competition between the pull-up path and the pull-down path. Therefore, the delay time can be greatly reduced. And can eliminate short circuit power loss.

Description

Level conversion circuit with auxiliary circuit

This creation relates to a level conversion circuit with auxiliary circuits, especially using an input circuit (1), a potential conversion circuit (2), and an output control transistor (3) to obtain accurate voltage levels Switch and effectively avoid the competition between the pull-up path and the pull-down path, thereby reducing the power loss of the electronic circuit.

The level conversion circuit is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transfer signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the level conversion circuit is responsible for converting low-voltage working signals into high-voltage working signals.

FIG. 1 shows a latch-type level conversion circuit circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1) , A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter (INV) to form a level conversion circuit with an auxiliary circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the input voltage (V (IN )) Is also between ground (GND) and the second high potential voltage (VDDL). Input voltage (V (IN)) and inverting input voltage output through inverter (INV) The voltage signals are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2). Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), the latch is latched when the output (OUT) of the level conversion circuit is in a stable state. No level current is generated in the level conversion circuit of the type. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the process of the above-mentioned conventional level conversion circuit, when the second PMOS transistor (MP2) is approaching on (or off) and when the second NMOS transistor (MN2) is approaching off (or on), the output of There is a phenomenon of contention between the pull-up and pull-down of the potential at the node (OUT), so the output voltage signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the input voltage (V (IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that the first Two PMOS transistors (MP2) are turned on. Therefore, the output is a first high potential voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower input voltage (V (IN)) during the conversion may not be possible Make the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1), and the second NMOS transistor (MN2) reach full conduction or completely cut off. There is a static current between the potential voltage (VDDH) and the ground (GND). This static current will increase the power loss.

In addition, the performance of the latch-type level conversion circuit is affected by the first high potential voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). Is the first high potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch type level conversion circuit operate normally is limited.

Figure 2 shows one of the other prior art mirror level switching circuits. The level switching circuit connects the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) together. And connected to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in a saturation region And its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type level conversion circuit is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high-potential voltage (VDDH) changes, the level The performance of the conversion circuit will not change much. Therefore, the mirror-type level conversion circuit can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of this creation is to propose a level conversion circuit with an auxiliary circuit, which can accurately and quickly convert the first signal into a second signal, and can effectively suppress the pull-up path and pull-down path Competition between them, which in turn reduces power loss.

This creation proposes a level conversion circuit with an auxiliary circuit, which is composed of an input circuit (1), a potential conversion circuit (2), and an output control transistor (3), where the input circuit (1) Is coupled to a first input terminal (IN) for providing a differential input signal; the potential conversion circuit (2) is coupled to the first high power supply voltage (VDDH) for potential conversion; The output control transistor (3) is coupled to the first input terminal (IN) to control the output potential of the first node (N1). .

The simulation results confirm that the level conversion circuit with the auxiliary circuit proposed in this creation can not only accurately and quickly convert a first signal into a second signal, but also effectively suppress the difference between the pull-up path and the pull-down path Competition can also effectively reduce power loss.

1‧‧‧input circuit

2‧‧‧potential conversion circuit

3‧‧‧Output control transistor

N1‧‧‧First Node

N2‧‧‧Second Node

N3‧‧‧ third node

MP1‧‧‧The first PMOS transistor

MP2‧‧‧Second PMOS transistor

MP3‧‧‧Third PMOS Transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧The third NMOS transistor

I1‧‧‧first inverter

GND‧‧‧ Ground

IN‧‧‧first input

V (IN) ‧‧‧First Signal

INB‧‧‧Second Input

OUT‧‧‧output

V (OUT) ‧‧‧Second signal

VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧The second highest power supply voltage

Figure 1 shows the circuit diagram of the level conversion circuit in the first prior art; Figure 2 shows the circuit diagram of the level conversion circuit in the second prior art; Figure 3 shows the Circuit diagram of level conversion circuit; Figure 4 is a timing diagram showing the transient analysis of the first signal and the second signal in the preferred embodiment of the present invention;

According to the above purpose, this creation proposes a level conversion circuit with an auxiliary circuit, as shown in FIG. 3, which is composed of an input circuit (1), a potential conversion circuit (2), and an output control transistor (3 ), Wherein the input circuit (1) is coupled to the first input terminal (IN) for providing a differential input signal; it is composed of a first NMOS transistor (MN1), a second NMOS The transistor (MN2) is composed of a first inverter (I1), and the source of the first NMOS transistor (MN1) is connected to the ground (GND), and the gate is connected to the first input terminal ( IN), and its drain is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to ground (GND), and its gate is connected to the second input terminal (INB ), And its drain is connected to the third node (N3); the first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V ( IN)) and provide a signal that is opposite to the first signal (V (IN)); the potential conversion circuit (2) is coupled to the first high power supply voltage (VDDH) and is used as a potential Conversion; it consists of a first PMOS transistor (M P1), a second PMOS transistor (MP2) and a third NMOS transistor (MN3), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH) ), Its gate is connected to the third node (N3), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power source The supply voltage (VDDH), whose gate is connected to the first node (N1), and whose drain is connected to the second node (N2); the source of the third NMOS transistor (MN3) is connected to the The third node (N3), whose gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2); the output control transistor (3) is coupled to the A first input terminal (IN) for controlling the first node (N1) Output potential; it is composed of a third PMOS transistor (MP3), its source is connected to the second high power supply voltage (VDDL), its gate is connected to the first input terminal (IN), and Its drain is connected to the first node (N1); the first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the level conversion circuit, and the second high power supply voltage (VDDL) is used to provide a second high power supply voltage required by the level conversion circuit. The level of the second high power supply voltage (VDDL) is less than the level of the first high power supply voltage (VDDH). The first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V (OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

Please refer to FIG. 3 again, the operation mode of the level-dependent conversion circuit is described below. The working principle of FIG. 3 is as follows: Now consider the level conversion circuit when the first signal (V (IN)) is a logic low level (“0”). Steady-state operation: the logic low level ("0") on the first input (IN) is simultaneously transmitted to the input of the first inverter (I1), the first NMOS transistor (MN1), the The gate of the third NMOS transistor (MN3) and the gate of the third PMOS transistor (MP3) cause the first NMOS transistor (MN1) and the third NMOS transistor (MN3) to be turned off, and the third The PMOS transistor (MP3) is turned on, so that the first node (N1) is at a logic high level (VDDL), and the first inverter (I1) transmits a logic high level (VDDL) to the second NMOS transistor ( MN2), the second NMOS transistor (MN2) is turned on, and the potential of the third node (N3) is pulled down to a logic low level ("0"). A logic low level ("0") turns on the first PMOS transistor (MP1), since both the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are turned on, and the first NMOS transistor (MP1) is turned on MN1) ends, so this The potential of a node (N1) is pulled up to a logic high level (VDDH), and the logic high level ("1") on the first node (N1) is transmitted to the second PMOS transistor (MP2). The gate makes the second PMOS transistor (MP2) turn off; Both the second PMOS transistor (MP2) and the third NMOS transistor (MN3) are turned off, and the second NMOS transistor (MN2) is turned on, so the potential of the third node (N3) is maintained at a logic low Level ("0"), therefore, the potential of the output (OUT) is maintained at a steady state value of a logic low level ("0").

Consider again the steady-state operation of the level conversion circuit when the first signal (V (IN)) is the logic high level (VDDL): the logic high level (VDDL) on the first input terminal (IN) is simultaneously transmitted to the first An input terminal of an inverter (I1), a gate of the first NMOS transistor (MN1), a gate of the third NMOS transistor (MN3), and a gate of the third PMOS transistor (MP3) make the first An NMOS transistor (MN1), the third NMOS transistor (MN3) is turned on, the third PMOS transistor (MP3) is turned off, and the first inverter (I1) transmits a logic low level ("0") to The gate of the second NMOS transistor (MN2) turns off the second NMOS transistor (MN2). At this time, since the first NMOS transistor (MN1) is turned on, the first node (N1) The potential is pulled down to a logic low level ("0"), and the logic low level ("0") on the first node (N1) is transmitted to the gate of the second PMOS transistor (MP2), so that the The second PMOS transistor (MP2) is turned on; since the second PMOS transistor (MP2) and the third NMOS transistor (MN3) are both turned on, the second NMOS transistor (MN2) is turned off, so the third node (N3) will be pulled up to a logic High level (VDDH); and the logic high level ("1") of the third node (N3) causes the first PMOS transistor (MP1) to be turned off. At this time, due to the first PMOS transistor (MP1) and the first All three PMOS transistors (MP3) are turned off. Therefore, the potential of the first node (N1) will be maintained at a logic low level ("0"), and the potential of the third node (N3) will also be maintained at a logic high level (VDDH). Therefore, the potential of the output terminal (OUT) is pulled up to a steady state value of the first high power supply voltage (VDDH).

In summary, the second PMOS transistor (MP2) and the second NMOS transistor (MN2) can be turned on simultaneously in a short time. This creation through this third NMOS transistor (MN3) Cut off the corresponding pull-up path to reduce competition. When the second NMOS transistor (MN2) is turned on (that is, the pull-down path is enabled), the third NMOS transistor (MN3) cuts off the pull-up path to avoid a situation between the pull-up path and the pull-down path. Competition, therefore, can significantly reduce the delay time and can eliminate short circuit power loss.

The Spice transient analysis simulation result of the level conversion circuit with the auxiliary circuit proposed in this work is shown in Figure 4. From the simulation results, it can be confirmed that the level conversion circuit with the auxiliary circuit proposed in this work, the Not only can the first signal be quickly and accurately converted into a second signal, but also the power loss can be effectively reduced.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims (7)

A level conversion circuit with an auxiliary circuit is used to convert a first signal (V (IN)) into a second signal (V (OUT)). The level conversion circuit includes a first node (N1) for converting A drain of a first PMOS transistor (MP1), a drain of a third PMOS transistor (MP3), a gate of a second PMOS transistor (MP2), and a drain of a first NMOS transistor (MN1) A second node (N2) for connecting the drain of the second PMOS transistor (MP2) and the drain of a third NMOS transistor (MN3); a third node (N2) N3) to connect the gate of the first PMOS transistor (MP1), the source of the third NMOS transistor (MN3), and the drain of a second NMOS transistor (MN2); a first An input terminal (IN) is coupled to the gate of the third PMOS transistor (MP3) and the first NMOS transistor (MN1) to provide a first signal (V (IN)); a second An input terminal (INB) is coupled to the gate of the second NMOS transistor (MN2) to provide an inverted signal of the first signal (V (IN)); an output terminal (OUT) is coupled to The third node (N3) is used to output the second signal (V (OUT)); a first inverter (I1 ), Coupled to the first input terminal (IN), for receiving the first signal (V (IN)) and providing a signal that is opposite to the first signal (V (IN)); a first A high power supply voltage (VDDH) is coupled to the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) to provide a first high power voltage required by the level conversion circuit A second high power supply voltage (VDDL) coupled to the source of the third PMOS transistor (MP3) to provide a second high power supply voltage required by the level conversion circuit, the second high power supply The potential of the supply voltage (VDDL) is less than the potential of the first high power supply voltage (VDDH); an input circuit (1) is coupled to the first input terminal (IN) to provide a differential input signal; The potential conversion circuit (2) is coupled to the first high power supply voltage (VDDH) for potential conversion; and an output control transistor (3) is coupled to the first input terminal (IN), It is used to control the output potential of the first node (N1). The level conversion circuit with an auxiliary circuit according to item 1 of the scope of patent application, wherein the input circuit (1) includes: a first NMOS transistor (MN1), the source of which is connected to the ground (GND), and the gate Is connected to the first input terminal (IN), and its drain is connected to the first node (N1); a second NMOS transistor (MN2), its source is connected to ground (GND), and its gate Terminal is connected to the second input terminal (INB), and its drain terminal is connected to the third node (N3); and a first inverter (I1) is coupled to the first input terminal (IN) To receive the first signal (V (IN)) and provide a signal that is inverse to the first signal (V (IN)). The level conversion circuit with an auxiliary circuit according to item 2 of the scope of patent application, wherein the potential conversion circuit (2) includes: a first PMOS transistor (MP1) whose source is connected to the first high power supply Voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the A first high power supply voltage (VDDH), a gate of which is connected to the first node (N1), and a drain of which is connected to the second node (N2); and a third NMOS transistor (MN3), Its source is connected to the third node (N3), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2). The level conversion circuit with an auxiliary circuit according to item 3 of the scope of patent application, wherein the output control transistor (3) is composed of a third PMOS transistor (MP3), and its source is connected to the second The high power supply voltage (VDDL) has a gate connected to the first input terminal (IN), and a drain connected to the first node (N1). The level conversion circuit with an auxiliary circuit according to item 1 of the scope of patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL). The level conversion circuit with an auxiliary circuit according to item 5 of the scope of the patent application, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL). The level conversion circuit with an auxiliary circuit according to item 6 of the scope of the patent application, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH).