TWM576365U - Low power voltage level converter - Google Patents

Abstract

This creation proposes a low-power voltage level converter, which is composed of an input circuit (1), a potential conversion circuit (2), and a mode control switch (3), where the input circuit (1) is used To provide a differential input signal; the potential conversion circuit (2) is used to suppress the competition of the potential at the output terminal (OUT); and the mode control switch (3) is used to control different operations of the voltage level converter mode.

The low power voltage level converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device, and can also effectively The competition between the pull-up path and the pull-down path is suppressed, thereby reducing power loss.

Description

Low power voltage level converter

This creation proposes a low-power voltage level converter, especially one composed of an input circuit (1), a potential conversion circuit (2), and a mode control switch (3) to obtain accurate voltage level conversion. Electronic circuit that can also effectively reduce power loss.

The voltage level converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transmit signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the voltage level converter is responsible for converting low-voltage working signals into high-voltage working signals. .

Figure 1 shows a mirror-type voltage level converter circuit of another prior art. The voltage level converter uses a first PMOS transistor (MP1) and a second PMOS transistor (MP2). The gates are connected together and connected to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) MP1) is in the saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) Also equal. Since the performance of the mirrored voltage level converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output of the first high power supply voltage (VDDH) changes , Voltage level converter performance It will not change much. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

Figure 2 shows a latch-type voltage level converter circuit, one of the prior art, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor ( MN1), a second NMOS transistor (MN2) and an inverter (INV) to form a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second highest power supply voltage ( VDDL) and ground (GND), and the potential of the first signal (V (IN)) is also between ground (GND) and the second highest power supply voltage (VDDL). The first signal (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch No static current is generated in the lock-type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. Making the first PMOS transistor (MP1) conductive, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; furthermore, When the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that The gate potential of the first PMOS transistor (MP1) is pulled up to turn off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, the above-mentioned conventional voltage level converter is approaching (or turning off) the second PMOS transistor (MP2) and the process of turning off (or turning on) the second NMOS transistor (MN2). There is a phenomenon of contention between the pull-up and pull-down of the potential at the output terminal (OUT), so the second signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the first signal (V (IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower first signal (V (IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are fully turned on or completely turned off. This will cause a static current (static) between the first high power supply voltage (VDDH) and ground (GND). current), this quiescent current will increase power loss.

Furthermore, the performance of the latch-type voltage level converter is affected by the first high power supply voltage (VDDH), due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The electrode voltage is the first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second highest power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch-type voltage level converter operate normally is limited. In the process of the second PMOS transistor (MP2) approaching to turn on (or off) and the second NMOS transistor (MN2) approaching to turn off (or on), the pull-up of the potential on the output terminal (OUT) There is a phenomenon of contention between rising and pulling down, so the second signal (V (OUT)) is slower when it changes to a low potential.

In view of this, the main purpose of this creation is to propose a low power voltage level converter, which can not only accurately and quickly convert a first signal to a second signal, but also effectively reduce the pull-up path and pull-down path. Compete with each other, thereby reducing power loss.

This creation proposes a low-power voltage level converter, which is composed of an input circuit (1), a potential conversion circuit (2), and a mode control switch (3), where the input circuit (1) is used To provide the first signal (V (IN)) and the inverted signal of the first signal (V (IN)); the potential conversion circuit (2) is used to suppress the competition of the potential of the output terminal (OUT); The mode control switch (3) is used to control different operation modes of the voltage level converter.

The simulation results confirm that the low-power voltage level converter proposed by this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple advantages such as simple circuit structure and conducive to the miniaturization of the device. Efficiency, while also effectively reducing power loss.

1‧‧‧input circuit

2‧‧‧potential conversion circuit

3‧‧‧Mode control switch

I1‧‧‧first inverter

N1‧‧‧First Node

N2‧‧‧Second Node

N3‧‧‧ third node

N4‧‧‧ fourth node

N5‧‧‧ fifth node

MP1‧‧‧The first PMOS transistor

MP2‧‧‧Second PMOS transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧The third NMOS transistor

MN4‧‧‧Fourth NMOS transistor

MN5‧‧‧Fifth NMOS transistor

OUT‧‧‧output

V (OUT) ‧‧‧Second signal

IN‧‧‧first input

V (IN) ‧‧‧First Signal

INB‧‧‧Second Input

EN‧‧‧Mode selection signal

V (INB) ‧‧‧ Inverted input signal

VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧The second highest power supply voltage

GND‧‧‧ Ground

Fig. 1 is a circuit diagram showing a voltage level converter in the first prior art; Fig. 2 is a circuit diagram showing a voltage level converter in the second prior art; FIG. 3 is a circuit diagram showing a low power voltage level converter of the preferred embodiment of the present invention; FIG. 4 is a timing analysis diagram of the first signal and the second signal of the preferred embodiment of the present invention;

According to the above purpose, the present invention proposes a low-power voltage level converter, as shown in FIG. 3, which is composed of an input circuit (1), a potential conversion circuit (2), and a mode control switch (3). The input circuit (1) is used to provide a first signal (V (IN)) and an inverted signal of the first signal (V (IN)); the potential conversion circuit (2) is used to Suppress the competition of the potential of the output terminal (OUT); and the mode control switch (3) is used to control different operation modes of the voltage level converter; the input circuit (1) is composed of a third NMOS transistor ( MN3), a fourth NMOS transistor (MN4) and a first inverter (I1), wherein the source of the third NMOS transistor (MN3) is connected to the fifth node (N5), which The gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); the source of the fourth NMOS transistor (MN4) is connected to the fifth node (N5) , Its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal ( IN) to accept the first Signal (V (IN)) and provide a signal that is opposite to the first signal (V (IN)); the potential conversion circuit (2) is composed of a first PMOS transistor (MP1), a second PMOS A transistor (MP2), a first NMOS transistor (MN1), and a second NMOS transistor (MN2). The source of the first PMOS transistor (MP1) is connected to a first high power supply. Voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first High power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); the first NMOS power The source of the crystal (MN1) is connected to the third node (N3), its gate is connected to the second input (INB), and its drain is connected to the first node (N1); the second The source of the NMOS transistor (MN2) is connected to the fourth node (N4), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2); the The mode control switch (3) is composed of a fifth NMOS transistor (MN5). Its source is connected to ground (GND), its gate is connected to the mode selection signal (EN), and its drain is connected to the The fifth node (N5) is connected; the first high power supply voltage (VDDH) is used to provide a first high power supply voltage required by the low power voltage level converter, and the second high power supply voltage (VDDL) Is used to provide the second high power supply voltage required by the low power voltage level converter, and the level of the second high power supply voltage (VDDL) is lower than the level of the first high power supply voltage (VDDH), The first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts. The first high power supply voltage (VDDH) 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts, the first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V (OUT) ) Is the corresponding waveform between 0 volts and 1.8 volts.

Please refer to Figure 3 again. Now consider the steady-state operation of the low-power voltage level converter when the first signal (V (IN)) is a logic low level (0 volts): The logic low level is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the second NMOS transistor (MN2) and the gate of the third NMOS transistor (MN3), so that the second NMOS transistor ( MN2) and the third NMOS transistor (MN3) are both OFF, and the first inverter (I1) transmits a logic high level (VDDL) to the first NMOS transistor (MN1) and the fourth NMOS The gate of the transistor (MN4) causes both the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) to be turned on. At this time, because the second NMOS transistor (MN2) is turned off ( OFF), and The fourth NMOS transistor (MN4) is turned on, the potential of the fourth node (N4) is pulled down to a logic low level (0 volts), and the logic low level on the fourth node (N4) is transmitted to the The gate of the first PMOS transistor (MP1) causes the first PMOS transistor (MP1) to be turned on. At this time, because the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are both turned on, and The third NMOS transistor (MN3) is turned off. Therefore, the potential of the third node (N3) is pulled up to a logic high level, and the logic high level of the third node (N3) makes the second PMOS transistor (MP2) is turned off. Because both the second NMOS transistor (MN2) and the second PMOS transistor (MP2) are turned off, and the fourth NMOS transistor (MN4) is turned on, therefore, the fourth node (N4) The potential will be maintained at a logic low level (0 volts), and the potential at the output (OUT) will be maintained at a steady state value at a logic low level (0 volts). In other words, when the first signal (V (IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) by a low-power voltage level converter. OUT) output.

Consider again the steady-state operation of the low power voltage level converter when the first signal (V (IN)) is a logic high level (VDDL): the logic high level (VDDL) on the first input (IN) is transmitted simultaneously To the input terminal of the first inverter (I1), the gate of the second NMOS transistor (MN2), and the gate of the third NMOS transistor (MN3), so that the second NMOS transistor (MN2) and the first The three NMOS transistors (MN3) are all turned on, and the first inverter (I1) transmits a logic low level to the gates of the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4). , So that both the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are turned OFF. At this time, because the third NMOS transistor (MN3) is turned on, the first NMOS transistor (MN3) MN1) is turned off, the potential of the third node (N3) is pulled down to a logic low level, and the logic low level on the third node (N3) is transmitted to the second PMOS transistor (MP2). The gate electrode causes the second PMOS transistor (MP2) to be turned on. At this time, the second PMOS transistor (MP2) and the second PMOS transistor (MP2) are turned on. The NMOS transistor (MN2) is turned on, and the fourth NMOS transistor (MN4) is turned off. Therefore, the potential of the fourth node (N4) will be pulled up to a logic high level. The logic high level causes the first PMOS transistor (MP1) to be turned off. At this time, because both the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are turned off, and the third NMOS transistor (MN3) is turned off. It is turned on, therefore, the potential of the third node (N3) will be maintained at a logic low level, and the potential of the fourth node (N4) will also be maintained at a logic high level. Therefore, the potential of the output terminal (OUT) will be Maintain a steady state value at a logic high level. In other words, when the first signal (V (IN)) is a logic high level (VDDL), it is converted into a second signal with a first high power supply voltage (VDDH) by a low power voltage level converter, and is output by (OUT) output.

In summary, when the first signal (V (IN)) is a logic low level (0 volts), the second signal (V (OUT)) is also a logic low level (0 volts); and the first signal When (V (IN)) is a logic high level (VDDL), the second signal (V (OUT)) is a first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

The simulation results of Spice transient analysis of the low power voltage level converter proposed in this work are shown in Figure 4. From the simulation results, it can be confirmed that the low power voltage level converter proposed in this work is not only still The first signal can be quickly and accurately converted into a second signal, and the competition between the pull-up path and the pull-down path of the output (OUT) can be effectively reduced, thereby reducing power loss.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims (7)

A low power voltage level converter is used to convert a first signal (V (IN)) into a second signal (V (OUT)). The converter includes a first node (N1) for converting a The drain of the first PMOS transistor (MP1) and the drain of a first NMOS transistor (MN1) are connected together; a second node (N2) is used to connect the drain of a second PMOS transistor (MP2) And the drain of a second NMOS transistor (MN2) are connected together; a third node (N3) is used to gate the second PMOS transistor (MP2), the first NMOS transistor (MN1) ) And the source of a third NMOS transistor (MN3) are connected together; a fourth node (N4) is used to gate the first PMOS transistor (MP1), the second NMOS transistor The source of the crystal (MN2) and the drain of a fourth NMOS transistor (MN4) are connected together; a fifth node (N5) is used to connect the source of the third NMOS transistor (MN3), the first The source of the four NMOS transistors (MN4) and the drain of a fifth NMOS transistor (MN5) are connected together; a first input terminal (IN) is coupled to the second NMOS transistor (MN2) and the The gate of the third NMOS transistor (MN3) is used to provide a first signal (V (IN)); a second input terminal (INB) is coupled to the gates of the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) to provide the first signal ( V (IN)) is the inverting input signal (V (INB)); an output terminal (OUT) is coupled to the fourth node (N4) to output the second signal (V (OUT)); The first inverter (I1) is coupled to the first input terminal (IN), and is used for receiving the first signal (V (IN)) and providing an inverse of the first signal (V (IN)). Phase signal; a first high power supply voltage (VDDH) is coupled to the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) to provide the voltage level converter A first high power supply voltage required; a second high power supply voltage (VDDL) for providing a second high power supply voltage required by the voltage level converter, and a potential of the second high power supply voltage (VDDL) Is a potential lower than the first high power supply voltage (VDDH); a mode selection signal (EN) is coupled to the gate of the fifth NMOS transistor (MN5) to provide a uniform energy signal; an input circuit ( 1), coupled to the first input terminal (IN), for providing A differential input signal; a potential conversion circuit (2) coupled to the first high power supply voltage (VDDH) and the input circuit (1) for suppressing a competition phenomenon of the potential of the output terminal (OUT); and The mode control switch (3) is used to control different operation modes of the voltage level converter. The low-power voltage level converter according to item 1 of the scope of patent application, wherein the input circuit (1) includes a third NMOS transistor (MN3), the source of which is connected to the fifth node (N5), Its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); a fourth NMOS transistor (MN4), its source is connected to the fifth node ( N5), whose gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); and a first inverter (I1) is coupled to the first The input terminal (IN) is used to receive the first signal (V (IN)) and provide a signal that is opposite to the first signal (V (IN)). The low power voltage level converter according to item 2 of the scope of patent application, wherein the potential conversion circuit (2) includes: a first PMOS transistor (MP1), the source of which is connected to a first high power supply voltage ( VDDH), whose gate is connected to the fourth node (N4), and whose drain is connected to the first node (N1); a second PMOS transistor (MP2), whose source is connected to the first high The power supply voltage (VDDH), whose gate is connected to the third node (N3), and whose drain is connected to the second node (N2); a first NMOS transistor (MN1), whose source is connected To the third node (N3), its gate is connected to the second input terminal (INB), and its drain is connected to the first node (N1); and a second NMOS transistor (MN2), Its source is connected to the fourth node (N4), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2). The low power voltage level converter according to item 3 of the scope of patent application, wherein the mode control switch (3) is composed of a fifth NMOS transistor (MN5), and its source is connected to the ground (GND), Its gate is connected to the mode selection signal (EN), and its drain is connected to the fifth node (N5). The low power voltage level converter according to item 1 of the scope of patent application, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL). The low power voltage level converter according to item 5 of the patent application, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH). The low-power voltage level converter according to item 6 of the application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).