TWI833356B - Metallization structure and manufacturing method thereof - Google Patents

Abstract

A metallization structure includes a substrate having a via region, an island raised from the substrate and at least partially located in the via region, a conductive layer disposed on the substrate in a manner that a portion of the conductive layer conformally covers the island, and a dielectric layer disposed on the conductive layer to join a sidewall of the portion of the conductive layer, so the portion of the conductive layer at least partially becomes a portion of a conductive via in the via region.

Description

Metalized structures and methods of making them

The present invention generally relates to a metallized structure and a manufacturing method thereof. Specifically, the present invention relates to a metallized structure that reduces the aspect ratio of a deep hole process and a manufacturing method thereof.

The metallization process generally involves the layout and connection between multi-layer circuits, and the process of the conductive interlayer connected between two layers of metal circuits greatly affects the electrical connection quality of the metallization structure. With the trend of miniaturization and diversification of components or integrated circuits, problems with via hole patterning and filling often occur in the metallization process. This is particularly prominent in the deep hole process of antenna packaging and rewiring layers.

It is known that deep hole processes using general photoresist (such as via hole patterning processes with an aspect ratio of 10:1 or above) are usually not fully exposed due to the nature of the photoresist during development, and it is easy to form holes in the via holes. Photoresist residue is formed inside, and effective deep hole development cannot be achieved. Therefore, special photoresists have been developed for deep hole processes to achieve effective deep hole development. However, the cost of this special photoresist is relatively high, resulting in a manufacturing burden.

In addition, high aspect ratio via holes increase the difficulty of filling in the metallization process, especially in back-end processes such as antenna packaging and redistribution layers, where it is difficult to effectively fill deep holes using electroplating methods.

One object of the present invention is to provide a metallized structure and a manufacturing method thereof, which can effectively form a high aspect ratio conductive dielectric layer without using special photoresist.

One object of the present invention is to provide a metallized structure and a manufacturing method thereof, which reduce the aspect ratio of the interposer hole in the photolithography process by forming bumps in the via area, and facilitate subsequent filling of the via hole through electroplating. .

In one embodiment, the present invention provides a metallization structure, which includes a substrate, an island, a conductive layer and a first dielectric layer, wherein the substrate has a via region; the island protrudes from the substrate and is at least partially located in the via. area; the conductive layer is disposed on the substrate, and a portion of the conductive layer conformally covers the island; the first dielectric layer is disposed on the conductive layer to at least adjoin the sidewalls of the portion of the conductive layer, so that the conductive layer The portion at least partially forms a portion of the conductive dielectric layer located in the via region.

In one embodiment, the metallization structure of the present invention further includes a second dielectric layer and a circuit layer, wherein the second dielectric layer is disposed on the first dielectric layer, and the circuit layer is at least partially embedded in the second dielectric layer according to the circuit layer pattern. in the electrical layer and in contact with that portion of the conductive layer.

In one embodiment, the metallization structure of the present invention further includes a seed layer, wherein the circuit layer is an electroplated metal layer disposed on the seed layer.

In one embodiment, the island is formed of a dielectric material, where the dielectric material is selected from the group consisting of polyimide (PI), polybenzoxazole (PBO), epoxy, and silicone. Siloxane or combinations thereof.

In one embodiment, the substrate has a substrate dielectric layer, the islands are formed on the substrate dielectric layer, the thermal expansion coefficient of the islands is less than or equal to the thermal expansion coefficient of the substrate dielectric layer, and the islands and the first dielectric layer The dielectric layer and the substrate can be formed of the same or different materials.

In one embodiment, the aspect ratio of the conductive via is 10:1 to 100:1.

In one embodiment, the width of the conductive via layer is Wv, the thickness of the conductive layer is Tm, the width of the island is Wi, and Wi≧Wv-(2xTm).

In one embodiment, the depth of the conductive dielectric layer is Hv, the thickness of the conductive layer is Tm, the height of the island is Hi, and Hi≦(Hv-Tm).

In one embodiment, the conductive layer is an electroplated or laminated metal layer, and the material of the conductive layer is selected from copper, nickel, tin, silver, gold or combinations thereof.

In another embodiment, the present invention provides a method for manufacturing a metallized structure, including: providing a substrate with a via region; forming an island on the substrate, the island protruding from the substrate and at least partially located in the via region ; Forming a conductive layer on the substrate, a portion of the conductive layer conformally covering the island; and forming a first dielectric layer on the conductive layer, the first dielectric layer being at least adjacent to the sidewalls of the portion of the conductive layer so as to conduct electricity The portion of the layer at least partially forms a portion of the conductive dielectric layer located in the via region.

In one embodiment, the manufacturing method of the metallized structure of the present invention further includes forming a second dielectric layer and a circuit layer, wherein the second dielectric layer is formed on the first dielectric layer, and the circuit layer is at least partially inlaid according to the circuit layer pattern. in the second dielectric layer and in contact with the portion of the conductive layer.

In one embodiment, the manufacturing method of the metallized structure of the present invention further includes forming a seed layer before forming the second dielectric layer, and forming the circuit layer includes using an electroplating method to form a metal layer on the seed layer according to the circuit layer pattern. .

Compared with the prior art, the metallized structure and its manufacturing method of the present invention reduce the aspect ratio of the interposer hole in the subsequent lithography process by forming island-shaped bumps in the via area, effectively reducing the chance of photoresist residue, and It is beneficial to the subsequent formation of metal layers by electroplating.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout this specification, the same reference numbers refer to the same elements. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, “electrical connection” or “coupling” may mean the presence of other components between the two components.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and/or "includes" designate the presence of stated features, regions, integers, steps, operations, elements and/or components but do not exclude one or more The presence or addition of other features, regions, steps, operations, elements, parts and/or combinations thereof.

Additionally, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation illustrated in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" may include both "lower" and "upper" orientations, depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "lower" may include both upper and lower orientations.

As used herein, "about," "approximately," or "substantially" includes the stated value and an average within an acceptable range of deviations from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the A specific amount of error associated with a measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the terms "about", "approximately" or "substantially" used in this article can be used to select a more acceptable deviation range or standard deviation based on optical properties, etching properties or other properties, and one standard deviation may not apply to all properties. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations in the shapes illustrated in the illustrations are to be expected as a result of, for example, manufacturing techniques and/or tolerances. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, regions shown or described as flat may typically have rough and/or non-linear characteristics. Additionally, the acute angles shown may be rounded. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the claims.

The present invention provides a metallization structure and a manufacturing method thereof, which can be applied to any integrated circuit, and is preferably applied to integrated circuits with high aspect ratio conductive dielectric layers, such as antenna packaging or rewiring of integrated circuits. The metallization structure of the layer, etc., but is not limited to this. The details of the metallized structure and its manufacturing method of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic diagram of a metallization structure 10 according to an embodiment of the present invention. As shown in FIG. 1 , in one embodiment, the metallization structure 10 includes a substrate 100 , an island 120 , a conductive layer 130 and a first dielectric layer 140 . The substrate 100 has a via region 101 . The island 120 protrudes from the substrate 100 and is at least partially located in the via region 101 . The conductive layer 130 is disposed on the substrate 100, and a portion 132 of the conductive layer 130 conformally covers the island 120. The first dielectric layer 140 is disposed on the conductive layer 130 to at least abut the sidewalls of the portion 132 of the conductive layer 130 so that the portion 132 of the conductive layer 130 at least partially forms a portion of the conductive dielectric layer 190 located in the via region 101 .

Specifically, the substrate 100 can be a substrate that requires a metallization structure 10 in the manufacturing process of any integrated circuit product, such as a substrate that requires antenna packaging, a substrate that requires a rewiring layer, etc., but is not limited thereto. In one embodiment, the substrate 100 may have a substrate dielectric layer 110 , wherein the substrate dielectric layer 110 is located on the top of the substrate 100 , and conductive circuits (not shown) may be embedded in the substrate dielectric layer 110 , but this is not considered to be the case. limit. The substrate dielectric layer 110 may be formed of any dielectric material suitable for isolating conductive lines to avoid short circuits. In one embodiment, the material of the substrate dielectric layer 110 may be selected from polyimide (PI), polybenzoxazole (PBO), epoxy resin, siloxane or combinations thereof, but is not limited thereto. The substrate 100 has one or more via regions 101 , and the via regions 101 are regions where conductive vias 190 are to be subsequently formed. In this embodiment, only two adjacent via regions 101 are shown for explanation. However, the number, position and size of the via regions 101 may vary according to actual applications and are not limited to those shown in the embodiment.

In one embodiment, preferably corresponding to the number of via regions 101, one or more islands 120 are respectively disposed on the substrate 100, such as on the substrate dielectric layer 110, so that the islands 120 are at least partially located on the via. Layer area 101. Specifically, the island 120 may be an island-shaped bump independently provided on the surface of the substrate 100, and the top surface of the island 120 protrudes from the top surface of the substrate 100 (or the substrate dielectric layer 110). The plurality of islands 120 are not connected to each other, and each island 120 is at least partially located in the corresponding via region 101 . In other words, the vertical projection of the island 120 on the substrate 100 may at least partially overlap with the corresponding via region 101 . For example, the vertical projection of the island 120 on the substrate 100 may be partially located in the via region 101 , completely located in the via region 101 , or even beyond the via region 101 . In this embodiment, the vertical projection of the island 120 on the substrate 100 preferably completely falls in the via region 101 . The shape, size, position, and number of the islands 120 correspond to the conductive dielectric layer 190 to be formed later. In one embodiment, the island 120 is preferably formed of a dielectric material, and the dielectric material may be selected from polyimide (PI), polybenzoxazole (PBO), epoxy resin, siloxane or combinations thereof, but not limited to this. Depending on the actual application, the island 120 may also be formed of conductive material (such as conductive metal or non-metal). In one embodiment, the thermal expansion coefficient of the island 120 is preferably less than or equal to the thermal expansion coefficient of the substrate dielectric layer 110, thereby suppressing warpage.

The conductive layer 130 is preferably one of the conductive circuits of the metallized structure 10, and the conductive layer 130 is disposed on the substrate 100 (for example, on the substrate dielectric layer 110) and is formed in contact with the conductive circuits embedded in the substrate dielectric layer 110. Electrical connection. A portion 132 of the conductive layer 130 conformally covers the island 120 such that the portion 132 of the conductive layer 130 covering the island 120 has a substantially consistent profile with the island 120 . For example, the portion 132 of the conductive layer 130 covering the island 120 has a cap-like shape, such that the top surface of the portion 132 of the conductive layer 130 covers the top surface of the island 120 and is smaller than other portions of the conductive layer 130 . The top surface of a portion (for example, the portion in contact with the substrate dielectric layer 110 or its embedded circuit) protrudes, and the sidewall of the portion 132 of the conductive layer 130 covers the sidewall of the island 120 and is connected to the top of the portion 132 of the conductive layer 130 surface and other parts of the top surface. The conductive layer 130 is preferably a layered structure with a uniform thickness and undulating along the surface contour of the substrate 100 (including the islands 120 ), so that the dimensions of the conductive layer 130 in the thickness and width directions are substantially consistent, for example, the conductive layer 130 is on the substrate. The thickness on the top surface of 100 (and island 120) is preferably substantially consistent with the width of the conductive layer 130 on the side walls of island 120. In one embodiment, the conductive layer 130 is preferably an electroplated or laminated metal layer, and the material of the conductive layer 130 is selected from copper, nickel, tin, silver, gold or combinations thereof, but is not limited thereto. Depending on the actual application, the conductive layer 130 may be a non-metal conductive layer, such as an indium tin oxide (ITO) layer. Furthermore, since the island 120 is at least partially located in the via region 101 , the portion 132 of the conductive layer 130 covering the island 120 is also at least partially located in the via region 101 . For example, depending on the shape, size, position, etc. of the island 120 , the top surface and/or sidewalls of the portion 132 of the conductive layer 130 may be at least partially located in the via region 101 . In other words, the vertical projection of the portion 132 of the conductive layer 130 on the substrate 100 at least partially overlaps the via region 101 . In one embodiment, the vertical projection of the portion 132 of the conductive layer 130 on the substrate 100 preferably substantially completely overlaps the via region 101 .

The first dielectric layer 140 is a patterned dielectric layer that defines the conductive dielectric layer 190 so that the conductive dielectric layer 190 is embedded in the first dielectric layer 140 . The material of the first dielectric layer 140 may be selected from, but is not limited to, polyimide (PI), polybenzoxazole (PBO), epoxy resin, siloxane, or combinations thereof. Depending on the actual application, the island 120 , the first dielectric layer 140 and the substrate dielectric layer 110 may be formed of the same or different dielectric materials. Specifically, the first dielectric layer 140 is disposed on the conductive layer 130 and is at least adjacent to the sidewall of the portion 132 of the conductive layer 130, so that the portion 132 of the conductive layer 130 is embedded in the first dielectric layer 140 and is electrically conductive. The remainder of layer 130 except for portion 132 is located beneath first dielectric layer 140 . From another point of view, the vertical projection of the first dielectric layer 140 on the substrate 100 substantially covers the rest of the substrate 100 except the via region 101 , so that the portion of the conductive layer 130 that is not covered by the first dielectric layer 140 (For example, the portion of the conductive layer 130 located in the via region 101 ) serves as part or all of the conductive via layer 190 . In this embodiment, the first dielectric layer 140 only conformally covers the sidewalls of the portion 132 of the island 120 adjacent to the conductive layer 130 , so that the portion 132 of the conductive layer 130 completely serves as a part of the conductive dielectric layer 190 , but does not This is the limit. Depending on the actual application, the first dielectric layer 140 may be adjacent to the conductive layer 130 and conformally cover the sidewalls of the portion 132 of the island 120 and part of the top surface of the portion 132 so that the portion 132 is not covered by the first dielectric layer. The portion of the top surface covered by 140 forms part of the conductive dielectric layer 190 (as shown in FIG. 9 ). In other words, depending on the shape, size, position of the island 120 and the thickness of the conductive layer 130 , etc., the first dielectric layer 140 may not only cover the sidewall of the portion 132 of the island 120 adjacent to the conductive layer 130 but also completely or partially not cover it. The top surface of this portion 132 of conductive layer 130 .

As shown in the figure, the thickness of the first dielectric layer 140 substantially determines the depth of the conductive via layer 190 , and the width of the conductive via layer 190 is substantially the width of the via region 101 . In one embodiment, the depth of the conductive via 190 is Hv (ie, the thickness of the first dielectric layer 140 ), the width of the conductive via 190 is Wv (ie, the width of the via region 101 ), and the depth of the conductive via 190 is Wv (ie, the width of the via region 101 ). The width ratio (Hv:Wv) is preferably 10:1 or more, more preferably 10:1 to 100:1. In one embodiment, the sum of the height (or thickness) of the island 120 and the thickness of the conductive layer 130 is preferably less than or equal to the depth of the conductive dielectric layer 190 . For example, the thickness of the conductive layer 130 is Tm, the height of the island 120 is Hi, and (Hi+Tm)≦Hv, that is, Hi≦(Hv-Tm). As shown in FIG. 1 , when the sum of the height (or thickness) of the island 120 and the thickness of the conductive layer 130 is less than the depth of the conductive dielectric layer 190 (ie, Hi<(Hv-Tm)), this part of the conductive layer 130 132 covers the island 120 to form the bottom of the conductive dielectric layer 190 , and the subsequently formed circuit layer (for example, 170 ) is electrically connected to the portion 132 of the conductive layer 130 and is partially embedded in the first dielectric layer to form the conductive dielectric layer 190 of the top. When the sum of the height (or thickness) of the island 120 and the thickness of the conductive layer 130 is equal to the depth of the conductive dielectric layer 190 (that is, Hi=(Hv-Tm)) (not shown), the conductive dielectric layer 190 is essentially conductive. The portion 132 of the layer 130 covers the island 120 , that is, the subsequently formed circuit layer 170 is electrically connected to the portion 132 of the conductive layer 130 and is not embedded in the first dielectric layer 140 . Furthermore, the sum of the width of the island 120 and the width (ie, thickness) of the sidewalls of the conductive layer 130 covering both sides of the island 120 is preferably greater than or equal to the width of the conductive dielectric layer 190 . For example, the width of the island 120 is Wi, the thickness of the conductive layer 130 is Tm, and (Wi+2xTm)≧Wv, that is, Wi≧Wv-(2xTm). Through the above-mentioned design relationship between the island 120 and the conductive layer 130 and the conductive dielectric layer 190, it can be ensured that the portion of the conductive layer 130 covering the island 120 effectively forms a part of the conductive dielectric layer 190 at least partially. In other words, since the conductive layer 130 partially extends into the via hole to form a portion of the conductive dielectric layer 190 by conformally covering the island 120, the depth of the remaining portion of the conductive dielectric layer 190 is subsequently formed/filled by the circuit layer 170. It is effectively reduced and is beneficial to the production of the circuit layer 170 .

Furthermore, as shown in FIG. 1 , the metallization structure 10 may further include a second dielectric layer 180 and a circuit layer 170 . The second dielectric layer 180 is disposed on the first dielectric layer 140 , and the circuit layer 170 is at least partially embedded in the second dielectric layer 180 according to the circuit layer pattern and contacts the portion 132 of the conductive layer 130 . The material of the second dielectric layer 180 may be selected from, but is not limited to, polyimide (PI), polybenzoxazole (PBO), epoxy resin, siloxane, or combinations thereof. Depending on the actual application, the island 120 , the first dielectric layer 140 , the second dielectric layer 180 and the substrate dielectric layer 110 may be formed of the same or different dielectric materials. In addition, the metallization structure 10 may further include a seed layer 150 , and the circuit layer 170 is an electroplated metal layer disposed on the seed layer 150 . Specifically, the first dielectric layer 140 defines a conductive dielectric layer 190, and the second dielectric layer 180 has a pattern of the circuit layer 170 (ie, circuit layer pattern) that is in contact with the conductive layer 130 through the conductive dielectric layer 190. In one embodiment, the circuit layer 170 may be a packaged antenna or a rewiring layer, but is not limited thereto. The seed layer 150 is selectively provided and is located on the first dielectric layer 140 and the conductive layer 130 not covered by the first dielectric layer 140 to facilitate the subsequent formation of the metal circuit layer 170 by electroplating. For example, the portion of the seed layer 150 that is not covered by the second dielectric layer 180 corresponds to the circuit layer pattern, so that the electroplated metal only exists on the portion of the seed layer 150 that is not covered by the second dielectric layer 180 to form a circuit. Layer 170. In one embodiment, the material of the circuit layer 170 can be selected from copper, nickel, tin, silver, gold or combinations thereof, but is not limited thereto.

Furthermore, as shown in FIG. 9 , when the width of the island 120 ′ is greater than the width of the conductive dielectric layer 190 (ie, Wi > Wv), since the conductive layer 130 conformally covers the island 120 ′, even if the island 120 ′ is 120' When the vertical projection of the substrate 100 substantially exceeds the via region 101, the circuit layer 170 can still pass through the conductive dielectric layer 190 defined by the first dielectric layer 140 (for example, the top surface of the portion 132 of the conductive layer 130) and the conductive layer 190. Layer 130 forms electrical connections. From another point of view, the distance between adjacent islands 120' is greater than 2 times the width of the sidewalls of the portion 132 of the conductive layer 130 (ie, 2 times the thickness of the conductive layer 130), so that the first The dielectric layer 140 can be disposed between adjacent islands 120' (or between the adjacent portions 132 of the conductive layer 130) and define the conductive dielectric layer 190 in the portion 132 of the conductive layer 130, thereby enabling The adjacent conductive dielectric layer 190 is effectively isolated to avoid short circuit, and the circuit layer 170 and the conductive layer 130 are electrically connected through the conductive dielectric layer 190 .

The manufacturing method of the metallized structure 10 according to an embodiment of the present invention will be described below with reference to FIG. 10 and in conjunction with FIGS. 2 to 8 . As shown in Figure 10, in one embodiment, the method 200 for manufacturing a metallized structure includes step 210, providing a substrate 100, and the substrate 100 has a via region 101; step 220, forming an island 120 on the substrate 100. The object 120 protrudes from the substrate 100 and is at least partially located in the via region 101; step 230, forming a conductive layer 130 on the substrate 100, a portion 132 of the conductive layer 130 conformally covering the island 120; and step 240, forming a via An electrical layer (such as a first dielectric layer 140 ) is on the conductive layer 130 , and the first dielectric layer 140 is at least adjacent to the sidewalls of the portion 132 of the conductive layer 130 , so that the portion 132 of the conductive layer 130 is at least partially formed in the via region 101 part of the conductive dielectric layer 190 .

Specifically, details (such as materials, structures, etc.) of the substrate 100, the island 120, the conductive layer 130 and the dielectric layer (such as the first dielectric layer 140) can be referred to the descriptions of the previous embodiments, and will not be described again here. . The details of the steps of the method 200 for manufacturing the metallized structure will be emphasized below. As shown in FIG. 2 , in step 210 , the provided substrate 100 can be any substrate that requires a metallization structure in the manufacturing process of integrated circuit products. In one embodiment, the substrate 100 may have a substrate dielectric layer 110 , wherein the substrate dielectric layer 110 is located on the top of the substrate 100 , and conductive circuits (not shown) may be embedded in the substrate dielectric layer 110 , but this is not considered to be the case. limit. The substrate 100 has one or more via regions 101 to define a region where the conductive via 190 is to be formed later. Here, two via regions 101 are used as an example, but are not limited thereto.

In step 220 , the step of forming the island 120 may include forming the island 120 on the via region 101 of the substrate 100 using processes such as lithography and etching. For example, a blanket dielectric material layer can be formed on the substrate 100 (for example, on the substrate dielectric layer 110), a photoresist layer can be coated on the dielectric material layer, and steps such as exposure and development can be performed. The photoresist layer defines a pattern of two islands 120 in, for example, two via regions 101 respectively. Next, the portion of the dielectric material layer that is not protected by the developed photoresist layer is removed, and then the remaining photoresist layer is removed to form mutually separated island-shaped protrusions formed by the dielectric material in the two via regions 101 . block (i.e. island 120). It should be noted that although this embodiment illustrates that the dielectric material layer is formed and then the islands 120 are formed through processes such as photolithography and etching, it is not limited to this. In other embodiments, the conductive material layer may be formed, and then the islands 120 formed of the conductive material may be formed through processes such as lithography and etching. In addition, if the photoresist material can withstand subsequent process conditions (such as high temperature, high pressure, etc.), the islands 120 can be directly formed from the photoresist material through photolithography processes such as coating, exposure, and development, thereby eliminating the need to form and The step of patterning a dielectric material layer or a conductive material layer on the substrate 100 .

As shown in FIG. 3 , in step 230 , the step of forming the conductive layer 130 may include forming a conformal conductive layer 130 on the substrate 100 using processes such as photolithography and etching. For example, a conformal seed layer can be formed on the substrate 100 by deposition, that is, the outline of the seed layer undulates along with the outline of the islands 120 on the substrate 100, and then patterned (lithography). ) process, so that the area of the seed layer not covered by the photoresist has the pattern of the circuit to be formed. Then, electroplating or lamination is used to form an electroplated or laminated metal layer only on the patterned seed layer. The remaining photoresist and the portion of the seed layer covered by the remaining photoresist can then be removed by techniques such as stripping and etching (for example, the portion of the seed layer that does not have an electroplated metal layer formed thereon). Thereby, the conductive layer 130 with a predetermined circuit pattern can be formed on the substrate 100, and a part of the conductive layer 130 conformally covers the island 120. It should be noted here that although the metal layer is formed by electroplating or lamination in this step, it is not limited to this. In other embodiments, depending on the actual application, a conformal conductive layer 130 can be formed on the substrate 100 by deposition, and then the conductive layer 130 with a circuit pattern and a portion 132 of the conductive layer 130 can be formed through techniques such as lithography and etching. Conformally covering the islands 120 eliminates the step of forming a seed layer. Therefore, the material of the conductive layer 130 can not only use metal (such as copper, nickel, tin, silver, gold or combinations thereof), but also can use non-metal conductive materials (such as indium tin oxide (ITO)), but this is not the case. is limited.

As shown in FIG. 4 , in step 240 , the step of forming a dielectric layer includes forming a dielectric layer (eg, a first dielectric layer) defining a pattern of the conductive dielectric layer 190 on the conductive layer 130 using processes such as photolithography and etching. 140). For example, a blanket dielectric material layer can be formed on the conductive layer 130, a photoresist layer can be coated on the dielectric material layer, and steps such as exposure and development can be performed, so that the photoresist layer can be formed on, for example, two The via regions 101 respectively define two patterns corresponding to conductive vias. Next, the portion of the dielectric material layer that is not protected by the developed photoresist layer is removed to expose the conductive layer 130 underneath (ie, the portion of the conductive layer 130 in the via region 101 ), and then the remaining photoresist layer is removed. Thereby, the first dielectric layer 140 having the corresponding via hole 142 (that is, the opening corresponding to the conductive via layer) is formed in the via region 101 . In this embodiment, since the island 120 and the conductive layer 130 covering it are at least partially located in the via region 101, that is, the portion 132 of the conductive layer 130 covers the island 120 and forms the bottom of the conductive via layer 190, so that The photoresist layer defines the required exposure/development depth (or bottom) of the conductive via 190 and is elevated (ie, the aspect ratio is reduced) due to the presence of the islands 120 . Since the aspect ratio is reduced, the probability of photoresist residue after exposure and development is also reduced. Therefore, commonly used photoresist and photolithography techniques are sufficient to achieve effective development of via holes 142 without using expensive special photoresist. Reduce manufacturing costs. Furthermore, due to the reduced aspect ratio, the depth of the via hole 142 defined in the first dielectric layer 140 (that is, the opening corresponding to the conductive via layer 190) is also reduced, making the via hole 142 easier to fill, which is beneficial to Subsequently, techniques such as electroplating are used to complete the electrical connection with the conductive layer 130 .

As shown in FIGS. 5 to 8 , after forming the first dielectric layer 140 defining the via hole 142 , in one embodiment, the method 200 for manufacturing the metallization structure may further include forming a second dielectric layer 180 and a circuit layer. 170, wherein the second dielectric layer 180 is formed on the first dielectric layer 140, and the circuit layer 170 is at least partially embedded in the second dielectric layer 180 according to the circuit layer pattern and contacts the portion 132 of the conductive layer 130. In one embodiment, the circuit layer 170 is preferably a metal layer formed by electroplating. Therefore, the manufacturing method 200 of the metallized structure may further include forming the seed layer 150, and forming the circuit layer 170 includes forming the circuit layer 170 by using an electroplating method according to the circuit layer pattern. The metal layer is on the seed layer 150 .

Specifically, as shown in FIG. 5 , the step of forming the seed layer 150 may include using a deposition method to form the seed layer 150 on the first dielectric layer 140 and the exposed conductive layer 130 (eg, conductive layer 130 ) in the via hole 142 . on the top surface of this portion 132 of layer 130). For example, the seed layer 150 is conformally formed on the first dielectric layer 140 and the exposed conductive layer 130 so that the via holes 142 of the first dielectric layer 140 are not filled. As shown in FIG. 6 , the photoresist layer 165 is coated on the seed layer 150 . For example, the photoresist layer 165 is coated to fill the opening 142 and provide the photoresist layer 165 with a substantially flat surface. As shown in FIG. 7 , a patterned photoresist layer 160 is formed to define the pattern of the circuit layer 170 (ie, the circuit layer pattern). For example, the photoresist layer 165 is exposed and developed, so that the patterned photoresist layer 160 exposes the portion of the seed layer 150 on which the circuit layer 170 is to be subsequently formed, that is, the seed layer 150 is not a patterned photoresist layer. The portion covered by 160 corresponds to the circuit layer pattern, wherein the circuit layer pattern includes the opening 162 overlapping the via hole 142 of the first dielectric layer 140 . In other words, the circuit layer pattern defined by the patterned photoresist layer 160 at least includes the opening 162 formed in the via region 101 to expose the seed layer 150 located in the via region 101 . In this step, since the island 120 and the portion 132 covered by the conductive layer 130 have been formed in the via region 101, the photoresist layer 165 is patterned and the opening 162 to be defined in the via region 101 is patterned. The depth is significantly reduced (i.e. the aspect ratio is reduced). Since the aspect ratio is reduced, the probability of photoresist residue after exposure and development is also reduced. Therefore, commonly used photoresist and photolithography techniques are sufficient to achieve effective development of the openings 162 of the photoresist layer without using expensive special photoresist. Can effectively reduce manufacturing costs. Due to the reduced aspect ratio, the depth of the opening 162 defining the conductive dielectric layer in the patterned photoresist layer 160 is also reduced, making the opening 162 easier to fill, which is beneficial to subsequent use of electroplating and other techniques to complete electrical connection with the conductive layer 130 .

As shown in FIG. 8 , the step of forming the circuit layer 170 includes using electroplating to form a metal layer only on the exposed seed layer 150 in the patterned photoresist layer 160 . Since the island 120 is at least partially located in the via region 101 , the depth of the opening 162 of the patterned photoresist layer 160 is significantly reduced, which is conducive to filling the opening 162 by electroplating and improves the feasibility of the electroplating process. Afterwards, the remaining photoresist and the portion of the seed layer 150 covered by the remaining photoresist can be removed by techniques such as stripping and etching (for example, the portion of the seed layer 150 that does not have an electroplated metal layer formed thereon). Then, the second dielectric layer 180 can be formed using techniques such as coating (or deposition) and etching, so that the circuit layer 170 is at least partially embedded in the second dielectric layer 180 . In this way, the circuit layer 170 with a predetermined circuit pattern can be formed, and the circuit layer 170 is in electrical contact with the portion (for example, 132) of the conductive layer 130 located in the via region 101, so as to electrically connect the circuit layer 170 and the conductive layer 130 through the conductive via layer 190. The conductive layer 130 is formed to complete the metallization structure 10 shown in FIG. 1 , but is not limited thereto.

As shown in FIG. 9 , depending on the actual application, the second dielectric layer 180 with the above circuit layer pattern can be formed on the first dielectric layer 140 through deposition, coating, lithography, etching and other techniques, and then through deposition , etching, planarization and other techniques to form the circuit layer 170 that is at least partially embedded in the second dielectric layer 180 based on the circuit layer pattern, thereby eliminating the step of forming a seed layer.

The present invention has been described by the above-mentioned relevant embodiments, but the above-mentioned embodiments are only examples of implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claimed patent are included in the scope of the present invention.

10:Metalized structure 100:Substrate 101: Intermediate area 110:Substrate dielectric layer 120, 120’: island 130:Conductive layer 132:Part 140: First dielectric layer 142: Via hole 150:Seed layer 160:Patterned photoresist layer 162:Open your mouth 165: Photoresist layer 170: Line layer 180: Second dielectric layer 190: Conductive dielectric layer Hi: height of island Hv: Depth of conductive dielectric layer Tm: thickness of conductive layer Wi: Width of the island Wv: Width of conductive dielectric layer

FIG. 1 is a schematic diagram of a metallization structure according to an embodiment of the present invention. 2 to 8 are schematic diagrams of various stages of a method for manufacturing a metallized structure according to an embodiment of the present invention. FIG. 9 is a schematic diagram of a metallization structure according to another embodiment of the present invention. FIG. 10 is a flow chart of a method for manufacturing a metallized structure according to an embodiment of the present invention.

10:Metalized structure

100:Substrate

101: Intermediate area

110:Substrate dielectric layer

120:Island

130:Conductive layer

132:Part

140: First dielectric layer

150:Seed layer

170: Line layer

180: Second dielectric layer

190: Conductive dielectric layer

Hi: height of island

Hv: Depth of conductive dielectric layer

Tm: thickness of conductive layer

Wi: Width of the island

Wv: Width of conductive dielectric layer

Claims (20)

A metallized structure containing: a substrate having a via region; An island protrudes from the substrate and is at least partially located in the via region; A conductive layer is disposed on the substrate, and a portion of the conductive layer conformally covers the island; and A first dielectric layer is disposed on the conductive layer so as to be adjacent to at least the sidewalls of the portion of the conductive layer such that the portion of the conductive layer at least partially forms a portion of a conductive dielectric layer located in the via region. The metallization structure of claim 1 further includes a second dielectric layer and a circuit layer, wherein the second dielectric layer is disposed on the first dielectric layer, and the circuit layer is based on a circuit layer pattern at least The portion is embedded in the second dielectric layer and contacts the portion of the conductive layer. The metallization structure of claim 2 further includes a seed layer, wherein the circuit layer is an electroplated metal layer disposed on the seed layer. The metallized structure of claim 1, wherein the island is formed of dielectric material. The metallized structure of claim 4, wherein the dielectric material is selected from polyimide, polybenzoxazole, epoxy resin, siloxane or combinations thereof. The metallized structure of claim 4, wherein the substrate has a substrate dielectric layer, the island is formed on the substrate dielectric layer, and the thermal expansion coefficient of the island is less than or equal to that of the substrate dielectric layer Thermal expansion coefficient, and the island, the first dielectric layer and the substrate dielectric layer may be formed of the same or different materials. The metallization structure of claim 1, wherein the conductive dielectric layer has an aspect ratio of 10:1 to 100:1. The metallization structure as claimed in claim 1, wherein the width of the conductive dielectric layer is Wv, the thickness of the conductive layer is Tm, the width of the island is Wi, and Wi≧Wv-(2xTm). The metallization structure of claim 1, wherein the depth of the conductive dielectric layer is Hv, the thickness of the conductive layer is Tm, the height of the island is Hi, and Hi≦(Hv-Tm). The metallized structure of claim 1, wherein the conductive layer is an electroplated or laminated metal layer, and the material of the conductive layer is selected from copper, nickel, tin, silver, gold or combinations thereof. A method for making a metallized structure, including: Provide a substrate having a via region; Forming an island on the substrate, the island protrudes from the substrate and is at least partially located in the via region; forming a conductive layer on the substrate, a portion of the conductive layer conformally covering the island; and Forming a first dielectric layer on the conductive layer, the first dielectric layer is at least adjacent to the sidewall of the portion of the conductive layer, so that the portion of the conductive layer at least partially forms a conductive dielectric located in the via region. part of the layer. The manufacturing method of claim 11 further includes forming a second dielectric layer and a circuit layer, wherein the second dielectric layer is formed on the first dielectric layer, and the circuit layer is based on a circuit layer pattern at least The portion is embedded in the second dielectric layer and contacts the portion of the conductive layer. The manufacturing method of claim 12, wherein before forming the second dielectric layer, it further includes forming a seed layer, and forming the circuit layer includes using an electroplating method to form a metal layer on the crystal according to the circuit layer pattern. On the seed level. The manufacturing method of claim 11, wherein forming the island includes forming the island from a dielectric material. The manufacturing method of claim 14, wherein the dielectric material is selected from the group consisting of polyimide, polybenzoxazole, epoxy resin, siloxane or combinations thereof. The manufacturing method of claim 14, wherein the substrate has a substrate dielectric layer, and forming the island includes forming the island on the substrate dielectric layer, wherein the thermal expansion coefficient of the island is less than or equal to The thermal expansion coefficient of the substrate dielectric layer, and the island, the first dielectric layer and the substrate dielectric layer may be formed of the same or different materials. The manufacturing method as claimed in claim 11, wherein the aspect ratio of the conductive dielectric layer is 10:1 to 100:1. The manufacturing method of claim 11, wherein the width of the conductive dielectric layer is Wv, the thickness of the conductive layer is Tm, the width of the island is Wi, and Wi≧Wv-(2xTm). The manufacturing method of claim 11, wherein the depth of the conductive dielectric layer is Hv, the thickness of the conductive layer is Tm, the height of the island is Hi, and Hi≦(Hv-Tm). The manufacturing method of claim 11, wherein forming the conductive layer includes forming an electroplated or laminated metal layer, and the material of the conductive layer is selected from copper, nickel, tin, silver, gold or combinations thereof.

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