TWI766556B - computing system - Google Patents

Abstract

A computing system includes a lower circuit substrate and an upper circuit substrate. The upper circuit substrate has a die package mounted thereon and a plurality of connection vias outside the die package therethrough, and the upper circuit substrate is mounted on the lower circuit substrate. Wherein, the upper circuit substrate only partially overlaps the lower circuit substrate, so that a part of the lower circuit substrate extends outward from the edge of the upper circuit substrate and forms a reinforcing ring surrounding the upper circuit substrate.

Description

computing system

The present invention relates to the field of connector systems, and more particularly to a connector system suitable for high data rate applications

Historically, computing device boxes have been provided with some type of a processor (disposed in a chip package) and connectors on a front panel of the box. The plurality of connectors and the processor are mounted on a circuit substrate (often referred to as a mother substrate) and the circuit substrate includes a plurality of traces connecting the plurality of connectors to the processor, thereby Information can be provided between the plurality of connectors and the processor. Unfortunately, as data rates have increased, this well-known system design has become difficult to use due to losses in the circuit substrate.

Various bypass connector systems are known to provide between an input/output (IO) connector and an integrated circuit such as, but not limited to, an application specific integrated circuit (ASIC) disposed in a chip package Connection. A common configuration would be to have a first connector (often an IO connector) at a panel of a box and a second connector to a circuit board (or another connector) at the chip package Nearby, where the first connector and the second connector are connected via a cable. As is known, cables are much lower in loss than standard circuit substrates and using a cable significantly reduces the losses between the first connector and the second connector. While this situation is well suited for 56Gbps applications, especially those using fourth-order pulse amplitude modulation (PAM 4) encoding, as data rates move toward Increasing to 112Gbps (with PAM 4 encoding) makes it more challenging to keep the insertion loss low enough to support one lane length usable. Some options provide good electrical performance but are difficult to assemble and thus create process problems when trying to build a component, such as a 1U server. Accordingly, some would appreciate a connector system that enables a connection to a chip package with low loss and still be easy to assemble.

A computing system includes a lower circuit substrate and an upper circuit substrate. an upper circuit substrate having a chip package mounted thereon and a plurality of connection vias outside the chip package therethrough, the upper circuit substrate being mounted on the lower circuit substrate, wherein the upper circuit substrate The lower circuit substrate is only partially overlapped so that a portion of the lower circuit substrate extends outward from the edge of the upper circuit substrate and forms a reinforcing ring surrounding the upper circuit substrate.

In one embodiment, the computing system further includes a plurality of upper grid array connector systems mounted on the upper circuit substrate, each upper grid array connector system comprising a base held by a base and connected to the upper circuit. Multiple cables for multiple connection paths on a substrate.

In one embodiment, the computing system further includes a compressible element and a heat sink. The compressible element includes a base having compressible fingers extending therefrom and snap arms extending therefrom that engage snap clasps on the base. A heat spreader engages the compressible fingers and the die package.

In one embodiment, the compressible element is formed from a single base that engages all of the bases of the plurality of upper grid array connector systems.

In one embodiment, the upper grid array connector system forms a central channel in which the die package is seated, and wherein the compressible element has a notch aligned with the central channel, the heat sink The device has a protrusion extending through the central channel and through the notch. .

In one embodiment, a computing system includes a plurality of lower grid array connector systems mounted on the lower circuit substrate, each lower grid array connector system including a plurality of cables held by a base.

In one embodiment, the computing system further includes a compressible element and a lower holding frame. The compressible element includes a base having compressible fingers extending therefrom and latching arms extending therefrom that engage the bases of the plurality of lower grid array connector systems. Buckle. A lower retention frame is attached to the heat sink and engages the compressible fingers.

In one embodiment, the computing system further includes a plurality of lower grid array connector systems mounted on the lower circuit substrate, each lower grid array connector system including a plurality of cables held by a base.

In one embodiment, the computing system further includes retention legs connecting the lower retention frame and the heat sink together, the retention legs passing through the reinforcement ring.

A computing system is provided for mounting a chip package. The computing system includes a first circuit substrate, a grid array connector system, a second circuit substrate and a terminal. The first circuit substrate has a mounting surface and a connection surface opposite to the mounting surface, the first circuit substrate has a first array of pads on the mounting surface, and the first array of pads is connected to the mounting surface. the chip package connection, the first circuit substrate further includes a plurality of support vias extending from the mounting surface to the connection surface and The signal pads on the connection surface are connected with the respective supporting vias. A grid array connector system is located on one side of the die package, the grid array connector system includes a plurality of cables, each cable includes a pair of conductors, wherein each conductor is electrically connected to one of the support vias . A grid array connector system is located on one side of the die package, the grid array connector system includes a plurality of cables, each cable includes a pair of conductors, wherein each conductor is electrically connected to one of the support vias . The terminals are located in each of the supporting vias of the second circuit substrate and extend outward from the mounting surface of the second circuit substrate, and each terminal includes: a press-fit part that is press-fitted to the second circuit substrate and a flexible portion extending outward from the press-fit portion and from the mounting surface of the second circuit substrate. Wherein, when the first circuit substrate and the second circuit substrate are butted together, the flexible portion is engaged with the signal pad of the first circuit substrate.

In one embodiment, each flexible portion has a folding arm, and the folding arm has a hook-shaped end portion, wherein a free end of the hook-shaped end portion faces the mounting surface of the second circuit substrate.

In one embodiment, each press-fit portion includes a deformable body, and the deformable body deforms when the press-fit portion is press-fitted into the respective support vias on the second circuit substrate.

In one embodiment, each of the support vias into which the press-fit portion of the second circuit substrate is inserted is cylindrical.

In one embodiment, each press-fit portion includes a deformable body, and the deformable body deforms when the press-fit portion is press-fitted into the respective support vias on the second circuit substrate.

In one embodiment, the computing system further includes: a solder carrier connected to each support via of the second circuit substrate.

In one embodiment, the computing system further includes a plurality of first supports mounted on the mounting surface of the first circuit substrate; a plurality of second supports electrically connected to the plurality of first supports; a A base is located on the first circuit substrate and at least partially covers the plurality of first supports and the plurality of second supports.

In one embodiment, the computing system further includes a heat sink mounted on the first circuit substrate.

20, 220, 420, 520, 920: Cable

21, 21', 221: conductor

23, 23': insulating layer

24, 224: Welding Department

26: Outer covering

28, 228: shielding layer

30, 30': support

43, 243: Opening

47, 247: Bevel

47': Tapered pilot hole

50, 150', 250, 450, 550, 650, 750, 850: Substrate

51a, 251a, 1010a: Mounting surface

51b, 251b, 1010b: connection surface

52, 252, 952: connection path

53, 253, 1053: support guide hole

54, 54', 259a, 259b: Ground plane

55, 255: Opening

55a: Cone

56, 258: Ground pad

57, 1057: Short traces

58, 256, 656, 1058: Signal pad

59: Taper angle

61, 561, 1061: Solder Loader

62: Connection Pattern

70, 170, 170', 170a, 170b, 270, 370, 470, 670, 770, 870: Grid Array Connector System

71, 271, 471, 798a, 799a, 871, 971: Base

72: Attachment Features

185: Mezzanine Connector

186: Clamping element

191: first connector

193: Cable Set

194, 394, 494, 994: Chip Packaging

195, 305, 405, 605, 905: Radiator

210, 310, 410, 610, 710, 910, 950: circuit substrate

229a: first pitch

229b: second spacing

240a, 540a: first support

240b, 540b: Second support

241: Depression

273, 473: Counterpoint Foot

275: Fingers

277: Hold Moldings

280, 480, 580, 680, 880: Inserts

281, 481, 581, 681: Frame

282, 282a~c, 582, 682: Contacts

283a~c, 283c': end

284a~c: middle part

301, 901, 1001: Computing Systems

305a, 905a: protrusions

306, 406, 906: Attachment elements

307, 407: Keep the frame

308, 908: keep the legs

398: Connection area

410a, 910a: Top side

410b, 910b: Bottom side

458: Alignment opening

464, 964.1: Compressible elements

465, 965: base

466, 966: Compressible fingers

467, 967: Buckle Arm

470a: First end

470b: Second end

471a, 971a: buckle buckle

494a: first edge

494b: second edge

670a: Subgrid Array Module

694a: Integrated Circuits

594b, 694b: Wafer substrate

682a, 682b: Butt end

798, 799: Connector

798b: Terminal

799c: Solder connection

873: Feet

874: Locking element

875: Cover

876: Buckle Arm

877: Fastening openings

884: Fastening opening

907: Lower Hold Frame

911: Substrate

913: Reinforcing Ring

958: Alignment opening

964.1: Upper Compressible Element

964.2: Lower Compressible Element

915, 968: Notch

970.1: Upper Grid Array Connector System

970.2: Lower Grid Array Connector System

978: Central Passage

998: Connection area

1010: Second circuit substrate

1080: Terminal

1087: Press Fitting

1087a: Ontology

1087b: Opening

1088: Flexible part

1088a: Part 1

1088b: Second bend

1088c: Part Three

1088d: Hooked end section

This application shows by way of example and not limitation the drawings in which like numerals refer to like parts, and in the drawings: FIG. 1 shows an example of an embodiment of a cable terminated to a substrate. Stereogram.

FIG. 2 shows a partially exploded perspective view of the embodiment shown in FIG. 1 .

Figure 3 shows a simplified exploded perspective view of an embodiment of a cable and stand that can be connected together.

Figure 4 shows a perspective view of an embodiment of a stand.

Figure 5 shows a bottom view of an embodiment of a substrate.

FIG. 6 shows a top view of the substrate shown in FIG. 5 .

Figure 7 shows a side view of a section of an embodiment of a substrate.

8 illustrates a perspective view of an embodiment of a grid array connector system.

FIG. 9 shows another perspective view of the embodiment shown in FIG. 8 .

Figure 10 shows a partial bottom view of an embodiment of a substrate.

Figure 11 shows a partially cutaway perspective view of a grid array connector system.

12 shows a side view of a grid array connector system configured to interface with a die package connected to a connector located below the die package.

Figure 13 shows a side view of the embodiment of Figure 12 with the connectors in a mated state.

14 shows a schematic diagram of an embodiment of a grid array connector system positioned in a system.

Figure 15 shows a schematic diagram of two grid array connector systems connected by a cable set.

16 shows a schematic diagram of an embodiment of a grid array connector system configured to include a die socket.

17 shows a perspective view of another embodiment of a grid array connector system mounted on a circuit substrate.

FIG. 18 shows a simplified perspective view of the grid array connector shown in FIG. 17 .

FIG. 19 shows a perspective, partially exploded view of the embodiment shown in FIG. 18 .

FIG. 20 shows a perspective view of an embodiment of an internal design of a grid array connector system that can be used with the embodiment shown in FIG. 18 .

21 illustrates a perspective, partially cutaway, partial view of an embodiment of an internal design of a grid array connector system.

FIG. 22 shows a perspective view of an embodiment of an internal design of a grid array connector system that can be used with the embodiment shown in FIG. 18 .

Figure 23 shows a cutaway perspective view of Figure 22 taken along line 23-23.

FIG. 24 shows a simplified perspective view of the embodiment shown in FIG. 23 .

Figure 25 shows a perspective view of an embodiment of a substrate.

Figure 26 shows a side view of an embodiment of a grid array connector system including an interposer mounted on a circuit substrate.

Figure 27A shows an embodiment of a contact suitable for use with an insert.

Figure 27B shows another embodiment of a contact suitable for use with an insert.

Figure 27C shows yet another embodiment of a contact suitable for use with an insert.

Figure 28 shows a perspective view of another embodiment of a grid array connector system that can be used with a heat sink.

FIG. 29 shows a perspective, partially exploded view of the embodiment shown in FIG. 28 .

FIG. 30 shows another perspective view of the embodiment shown in FIG. 29 .

Figure 31 shows a side view of an embodiment of a grid array connector system that can be used with a heat sink.

Figure 32 shows a simplified plan view of an embodiment of a chip package and multiple grid array connector system.

33 shows a perspective view of an embodiment of a chip package and grid array connector system.

FIG. 34 shows a perspective view of a grid array connector system shown in FIG. 33 .

FIG. 35 shows another perspective view of the embodiment shown in FIG. 34 .

FIG. 36 shows a plan view of an embodiment of a chip package mounted on a circuit substrate that can be used with the embodiment shown in FIG. 33 .

Figure 37 shows a partial side view of an embodiment of a grid array connector system showing an alternative insert configuration.

FIG. 37A shows an enlarged simplified side view of the embodiment shown in FIG. 37. FIG.

Figure 38 shows a schematic diagram of a grid array connector system mounted on a wafer substrate.

Figure 39 shows a schematic diagram of an embodiment of a substrate connected to an interposer.

40 illustrates a perspective, partially exploded view of an embodiment of a grid array connector system capable of mating with a circuit substrate via a mating connector.

FIG. 41 shows a perspective view of the grid array connector system shown in FIG. 40 .

FIG. 42 shows a perspective view of the docking connector shown in FIG. 40 .

43 shows a perspective view of an embodiment of a grid array connector system.

FIG. 44 shows another perspective view of the embodiment shown in FIG. 43 .

45 illustrates a top perspective view of an embodiment of a computing system.

FIG. 46 illustrates a bottom perspective view of the embodiment of the computing system shown in FIG. 45 .

FIG. 47 shows an exploded top perspective view of the components of the computing system shown in FIG. 45 .

FIG. 48 shows a partial cutaway view taken from a top perspective view of the computing system shown in FIG. 45 .

49 is an exploded top perspective view of components of an embodiment of a computing system.

FIG. 50 is an exploded bottom perspective view of the components of the computing system shown in FIG. 49 .

FIG. 51 is a top perspective view of a terminal of the computing system shown in FIG. 49 .

FIG. 52 is an assembled top perspective view of the components of the computing system shown in FIG. 49 .

FIG. 53 shows a partial cutaway view taken from a top perspective view of the computing system shown in FIG. 49 .

FIG. 54 is a top perspective view of components of the computing system shown in FIG. 49 .

The following detailed description illustrates exemplary embodiments, and the disclosed features are not intended to be limited to the explicitly disclosed combinations. Thus, unless stated otherwise, features disclosed herein may be combined together to form other combinations not shown for the sake of brevity.

As can be appreciated from Figures 1-7, an embodiment features disclosed to allow a cable 20 to be terminated directly to a substrate 50, which can be a conventional circuit substrate or any other desired substrate (such as but not limited to a ceramic and/or plastic-metal composite structure). The substrate 50 includes a mounting surface 51a and a connecting surface 51b, wherein one or more connecting vias 52 extend between the mounting surface 51a and the connecting surface 51b. Although terminating one or both conductors from a single cable 20 to a substrate can be accomplished in a wide range of ways, when attempting to terminate a larger number of cables 20 in a compact array, especially if This becomes more complicated when good electrical performance is required while providing the required flexibility in the manufacturing process. The illustrated embodiment includes a cable 20 having a pair of conductors 21 that can function as a differential pair. The pair of conductors 21 is surrounded by an insulating layer 23 , and then the insulating layer 23 is covered by a shielding layer 28 , and then the shielding layer 28 is covered by an outer covering 26 . It is contemplated that a drain wire is not required in most applications, but may be included if desired and connected to the standoff if included.

In order to connect the conductors 21 to signal pads 58 provided in a signal layer within the substrate 50, each conductor 21 may be attached by a solder 24 to a support via 53 provided by the substrate 50 ( or via a solder or other known attachment connection if desired). Figure 7 A cross-section of an embodiment of a support guide hole 53 configuration is shown. The conductor 21 can be inserted into an opening 43 in the substrate 50 aligned with an opening 55 which optionally includes a taper 55a to facilitate easy insertion of the conductor 21 . Preferably, opening 43 will also include a sloped surface 47 for assisting in guiding conductor 21 to the desired position corresponding to support guide hole 53 and then positioned such that one end of conductor 21 is adjacent to a front side of support guide hole 53 been positioned. A laser can then be used to weld conductors 21 to support vias 53 or to pin-bond conductors 21 to support vias 53 . In order to connect the shielding layer 28 of the cable 20 to the ground pad 56 on the connection surface 51 b , the standoff 30 is arranged to connect the shielding layer 28 to a grounding surface 54 on the substrate 50 .

If conductor 21 is soldered to support via 53, solder 24 will resist disengagement when exposed to the high temperatures associated with soldering, and after conductor 21 is soldered to support via 53, standoff 30 is at a higher Temperature (eg, using a higher temperature solder) enables attachment to substrate 50 and shield 28 without fear of loss of connection between conductor 21 and support via 53 . Once all the required cables 20 are attached, this in turn will allow subsequent soldering of the substrate 50 to other structures using lower temperature solder, thereby making the process of assembling a complete system easier to manufacture. Note that the use of solder to attach the standoff 30 to the ground plane 54 is not required, however, for some applications the standoff 30 may be attached by a conductive adhesive or may even be spotted by a laser Welding (potentially in multiple locations).

As described above, in order to easily install the conductors 21 into the base plate 50, the base plate 50 may be drilled with a tapered hole to obtain the structure shown in FIG. 7 . If a taper is provided, the taper angle 59 can be a wide range of angles, but will typically be from 15 degrees to about 40 degrees, and the actual angle will depend, at least in part, on the spacing of the apertures and the thickness of the substrate . Preferably, the taper angle 59 is sufficient to allow a natural spacing between a pair of conductors 21 to fit into the two enlarged openings 43 and then automatically align the two conductors 21 In two separate and adjacent openings 55 , so that when further inserted into the openings 55 , the two conductors 21 will automatically be guided to positions corresponding to the two supporting guide holes 53 .

To allow for improved attachment and proper ball grid array spacing, support vias 53 may be connected to a signal pad 58 via a short trace 57, as shown in FIG. As can be appreciated, only a portion of the short trace 57 is visible due to the solder mask. A solder charge 61 (eg, shown in FIG. 9 ), which may be a solder ball, can be positioned on both ground pads 56 and signal pads 58 to allow attachment of the grid array. Note that the design shown shows a uniform solder ball layout but non-uniformly spaced layouts are also contemplated. An additional benefit of this configuration is that attaching a solder carrier 61 to a solder joint 24 is less repeatable from a manufacturing point of view and supports the connection of vias 53 to signal pads 58 with short traces 57 Allows a solder carrier 61 to be positioned on conventional pads in a more reliable manner.

Although the illustrated weld 24 is fairly strong, it is generally desirable to provide some strain relief for the cable 20 . In one embodiment, portions of the plurality of wires 21 and the substrate 50 may be encapsulated in an insulating material (potentially using a low pressure molding process) to provide a base 71 . Base 71 may include attachment features 72 (such as shown in FIG. 8 ) to form a grid array connector system 70 . The grid array connector system 70 may include a substrate 50 having a connection surface 51b including a plurality of solder carriers 61 forming a connection pattern 62 . As can be appreciated, the internal design of the grid array connector system 70 may be arranged in accordance with FIGS. 1-7 .

As can be appreciated from FIG. 9, in a compact and low profile configuration, a relatively large connection pattern 62 can be formed to allow a greater number of connections, thereby enabling grid array connectors System 70 is more closely located to a corresponding application specific integrated circuit (ASIC). While such a configuration is beneficial for connecting a large number of differential pairs together, the resulting size can cause problems when attempting to solder attach the connection pattern 62 to another surface, as it prevents sufficient thermal energy from reaching the solder inside Loader 61. To prevent non-uniform thermal energy distribution (and resulting connectivity issues), one or more thermal vias (which may be slots or apertures) may be provided in substrate 50 and/or base 71, to allow improved and more uniform heat transfer to all solder loads 61 . The thermal path may come from the side or extend through the base 71 and substrate 50 within the connection pattern 62 (thereby creating a discontinuity in the connection pattern 62). The scheme for introducing thermal vias to improve the thermal performance of the solder attachment is based on the size of the pattern connection and many other parameters, such as cycle times and materials, and is thus left to one of ordinary skill in the art to determine as needed.

As described above, as shown in FIG. 5 , in certain embodiments, solder carrier 61 is attached to signal pad 58 spaced from support via 53 . Note that this has the advantage of avoiding soldering to surfaces being soldered prior to reflow that are inconsistent and may be difficult for a solder ball to attach reliably. As can be appreciated, such a configuration allows isolation to be beneficially used by surrounding signal pads 58 with ground pads 56 , such as shown in FIG. 10 . The disadvantage of such a configuration is that a short trace 57 is required to connect the support via 53 to the signal pad 58 and the short trace 57 can affect signal integrity. Figure 11 shows another embodiment with a configuration that allows via-solder ball direct attachment. As shown, conductor 21' is supported by an insulating layer 23' which is located in a standoff 30' attached to ground plane 54'. Conductor 21' extends through a tapered guide hole 47' and end portions are positioned and soldered to corresponding pads. Solder loads 61 are then positioned on all pads in a conventional manner. For larger gauge conductors 21', such a configuration can be more This is easy to do because the spacing between conductors 21' will be more consistent with the spacing required for the ball grid array. However, as is known, it is challenging to uniformly bond solder balls to a soldered surface, especially if the soldered surface is not completely uniform. One possible approach to this is to make the support vias 53 extend into the substrate 50 by a smaller amount and solder the conductors 21 to the support vias 53 below the top surface, so that the solder carrier 61 is placed in a location other than the soldering portion 24 itself part. Such a configuration may allow for good electrical performance while providing a more consistent surface for placing the solder balls, since the resulting contact area supporting the vias 53 may provide a rounded rim-shaped surface or may even be slightly concave.

As can be appreciated from FIGS. 12-13 , one potential application of the embodiment shown in FIGS. 1-11 is the inclusion of a mezzanine connector 185 in a grid array connector system 170 . As is known, the mezzanine connector 185 can be made to function in a compact space, can be hermaphroditic, and can have excellent electrical performance due to the ability to provide a relatively linear configuration. Thus, the illustrated embodiment includes a mezzanine connector 185 that allows the grid array connector system 170 to be mounted on a substrate 150, (which may be any desired type of substrate, as described above , a reversible connection between a chip package 194 on which the substrate 150' is mounted on another mezzanine connector 185). Such a configuration can provide excellent electrical performance while also providing a low insertion force for mating the die package 194 to the grid array connector system 170 . As can be appreciated, one advantage of this design is that it allows die package 194 to be attached to a connector (eg, mezzanine connector 185) separate from substrate 150', and that the connector can be mated to a different mating connection connector (eg, grid array connector system 170). This allows the two parts to be machined independently and can help reduce scrap and/or rework. Naturally, if desired, the design shown also allows existing wafer packages 194 (which are Can consist of an integrated circuit of a desired design and any other typical structure provided in a chip package 194) can be quickly replaced with a higher performance chip package 194.

Figure 14 shows a simplified schematic diagram of another potential configuration. A first connector 191 is located adjacent to a box mounting surface and is connected to a grid array connector system 170 via a cable set 193 (which includes a plurality of cables). A chip package 194 is mounted directly to the grid array connector system 170 and a heat spreader 195 is disposed on the chip package 194 . As can be appreciated, such a system allows for additional flexibility in the system, especially when the connector 191 is removably mounted (thus allowing for a complete update if needed).

Note that, in some embodiments, the substrate-attached grid array connector system may also be provided in a socket design having a plurality of contacts configured to attach directly to multiple contacts on an ASIC package. a pad. For example, such a grid array connector system could include an interposer (with a plurality of flexible contacts) and the base would be formed into a socket-type shape (which is slightly more complex) but could allow the elimination of A second connector and thus satisfactory. As schematically shown in FIG. 16, the grid array connector system 170' is configured to include a receptacle assembly that will directly receive a chip package 194 and will include a clamping element 186 (which may be integrally disposed or disposed separately) ) to hold the die package 194 in place. Although a rotating clamping element 186 is shown and is fairly common in known wafer packages 194, the clamping element 186 is not so limited and a wide range of clamping configurations are possible. In certain embodiments, for example, the clamping element 186 can be integrated into a heat sink and can be attached by separate fasteners. Although conventional socket designs are less suitable for high signaling frequencies and correspondingly high data rates due in part to terminal design and uniform spacing, through a more customized and relatively The non-uniform grid array, along with the ability to connect wires extremely cleanly (electrically speaking) to the multiple contacts of the bonded die package 194 in the grid array connector system 170', the illustrated embodiment overcomes these limitations.

As can be appreciated from FIG. 15, the utility of the grid array connector system disclosed herein is not limited to a particular application, such as a bypass application. This technique works well as a jumper between two die packages and allows significantly more flexibility at the location of the die packages. For example, one or more of the grid array connector systems 170a, 170b can be located adjacent to a liquid cooling seat located at the rear of the adjacent device (which reduces air flow through the main chassis of the server). need). Furthermore, although two grid array connector systems 170a, 170b are shown connected together by a cable set 193, in one embodiment, three or more grid array connector systems (and corresponding Chip packages) can be connected together by a cable set to help provide improved high performance computing (HPC) performance.

17-27C, another embodiment of a grid array connector system 270 is shown. The grid array connector system 270 includes a base 271 located on a substrate 250 and a plurality of cables 220 are terminated on a substrate 250 . In one embodiment, the plurality of cables 220 are arranged in columns of four, which provides the desired compactness and density, although other configurations are suitable depending on the application. Similar to the aforementioned substrate 50, the substrate 250 includes a mounting surface 251a and a connecting surface 251b and a plurality of connecting vias 252 extending between the mounting surface 251a and the connecting surface 251b. The interior of the substrate 250 may further include ground planes 259a, 259b to provide improved electrical performance. The plurality of connection passages 252 include two openings 243 , and the two openings 243 are aligned with an opening 255 in a supporting guide hole 253 respectively. Substrate 250 provides the connection A grid of signal pads 256 and ground pads 258 on junction 251b may be connected to a chip substrate or interposer (such as interposer 280 ) or directly on circuit substrate 210 .

The plurality of cables 220 are terminated to the base plate 250 by using a first support 240a and a second support 240b, and once terminated, the base plate 250 and the first support 240a and the second support 240b can be held by a The molding 277 is retained, and the retaining molding 277 may be a low pressure molding or a potting compound. As can be appreciated, base 271 includes a plurality of fingers 275 that form passages through which a plurality of cables extend, and base 271 includes a plurality of alignment feet 273 that align Feet 273 may be used to align base 271 with a docking member.

The first pedestal 240a may be mounted on the base plate 250 in a manner similar to the attachment of the pedestal 30 to the base plate 50 and the cable 220 is first connected to the second pedestal 240b, and in one embodiment, the plurality of cables 220 A shield layer 228 of each is electrically connected (via solder or fusion or conductive adhesive) to the corresponding second standoff 240b. The second support 240b is butted against the first support 240a, and is pressed against the second support 240b by an adhesive, a welding part or an interference fit (such as a recess 241 on the first support 240a, which 20-21), the first support 204a and the second support 240b may be held together. In other words, an interference fit can properly hold the first support 240a and the second support 240b together.

As described above for the base plate 50, the base plate 250 includes a plurality of openings 243, each of which may have an inclined surface 247, which may be used to guide the conductor 221 in the cable 220 to a desired position. This allows the two conductors 221 to change from a first pitch 229a to a second pitch 229b different from the first pitch. In one embodiment, the second pitch 229b is at least 50% greater than the first pitch 229a to provide an improved pad layout on the connection surface 251b. Spacing so modified is optional but determined It is beneficial to have cables 220 having conductors 221 of small size. Conductor 221 is mounted to support via 253 (preferably via solder 224, but as noted above, other methods of attachment may also be employed). The support vias 253 may be electrically connected to the signal pads 256 on the connection surface 251b via short traces 257 in the substrate 250 (if such signal pads 256 are separate from the support vias 253).

As previously described, the signal pads 256, ground pads 258 on the substrate 250 may be directly connected to pads on another surface (such as the circuit substrate 210) by solder. However, as shown in Figure 26, a different option is possible. Rather than soldering the substrate 250 to the circuit substrate 210 , an interposer 280 may be used to connect the pads on the substrate 250 to the pads on the circuit substrate 210 . The insert 280 includes a frame 281 that holds a plurality of contacts 282 that can engage the pads on both sides of the insert 280 . The contacts 282a, 282b, 282c are shown in FIGS. 27A to 27C and can be held by the frame body 281 . Contact 282a includes end portions 283a and a middle portion 284a that is not configured to flex in a significant manner. Contact 282b includes two end portions 283b and a middle portion 284b that is configured to flex. Contact 282c includes end portion 283c and end portion 283c', with a middle portion 284c not intended to flex in a significant manner. As can be appreciated, these contacts 282a-c may have multiple contact points at one or both ends and be compressible or incompressible as desired, depending on the application. Additionally, because there may be multiple ground connections, it may be desirable to configure the ground contacts differently than the signal contacts (eg, with different impedances) to help properly adjust the impedances of the common and differential modes. Therefore, the signal contacts may be configured differently than the ground contacts.

FIGS. 28-30 illustrate an embodiment of a computing system 301 that includes a heat sink 305 . As shown, a grid array connector system 370 is mounted on a plurality of wafer packages 394 side. As shown, the grid array connector system 370 is located on four sides of the die package 394 (both positioned on a circuit substrate 310), but the grid array connector system 370 can also be mounted on one fewer side . A retaining frame 307 with a plurality of retaining legs 308 can be provided to help secure the heat sink 305 in place with the attachment elements 306, and the heat sink 305 includes a protrusion 305a designed to press against the chip package 394 to ensure that there is a good thermal connection between the heat sink 305 and the die package 394. To ensure that there is a sufficiently effective thermal connection between the heat spreader 305 and the chip package 394, one may include some type of thermal interface material (TIM), which may be a paste or other suitable material. Chip packages 394 may be soldered directly to heat spreader 305 if their thermal efficiency is required to be better. As can be appreciated, the circuit substrate 310 may include a connection area 398 aligned with the die package 394 to provide additional signal paths to other components (or to mounted components directly below the die package 394). As can be appreciated, the heat spreader 305 presses against both the die package 394 and the grid array connector system 370 and thus ensures that both are pressed firmly in place and a reliable connection is maintained.

Figures 31 to 36 show another embodiment similar to the embodiment shown in Figures 28 to 30 . A heat sink 405 with an attachment element 406 is connected to the holding frame 407 , which is located on a bottom side 410 b of a circuit substrate 410 . A die package 494 and a plurality of grid array connector systems 470 are positioned between the circuit substrate 410 and the heat spreader 405 (on a top side 410a of the circuit substrate 410). As can be appreciated from FIG. 32, each of the grid array connector systems 470 is positioned with a first end 470a aligned with a first edge 494a of the die package 494 and a second end 470b extending beyond the die A second edge 494b of the package 494, thereby improving the connection density. Naturally, other configurations are suitable if this density is not required.

Similar to the above-described embodiments, the grid array connector system 470 includes a plurality of cables 420 held by a base 471 and connected to a substrate 450 and the substrate 450 is connected to an interposer 480, the interposer 480 There is a frame 481 for holding a plurality of contact pieces. The circuit board 410 includes a plurality of alignment holes 458 , and the plurality of alignment holes 458 are configured to be butted with the plurality of alignment legs 473 . Naturally, on each side of the die package 494, the plurality of alignment apertures 458 may be arranged in the same pattern to allow commonality, or may be arranged in a different pattern to ensure that only certain grid array connector systems 470 Can be positioned on certain sides. As can be appreciated, it is desirable that the interface between die package 494 and heat sink 405 define the vertical position of heat sink 405 because the thermal connection between die package 494 and heat sink 405 affects the amount of heat removed from die package 494 . The illustrated system includes a compressible element 464 that ensures that the heat sink 405 is pressed against the grid array connector system 470 with the required force (and thereby allows the heat sink 405 to be held vertically relative to the circuit substrate 410). fluctuate in position). The compressible element 464 shown includes a base 465 having a plurality of compressible fingers 466 and includes a catch arm 467 that engages a catch catch 471a to secure the compressible element 464 to the base 471 . As can be appreciated, although mounting a grid array connector on all four sides of a die package 494 provides a tighter connection for die package 470 and reduces any traces between die package 494 and cables 420 (thereby reducing insertion loss to a predetermined level), but also consider installing grid array connectors 470 on fewer sides of die package 494 (to have the same number of connections, grid array connector system 470 will naturally have to be larger). Additionally, as can be appreciated from FIG. 34, although the grid array connector 470 is shown with four cables 420 in each column of cables 420, some other number of cables 420 may be provided.

Turning to Figures 37-37A, another embodiment of a grid array connector configuration is shown. The simplified partial view of FIG. 37 shows a cable 520 connected to a second support 540b, which is connected to a first support 540a, which in turn is connected to the substrate 550. Thus, part of the design is similar to the previous embodiment. A slight difference, however, is that the insert 580 includes a frame 581 that holds a plurality of contacts 582 in the form of cylinders. The plurality of contacts 582 will be soldered directly to the substrate 550 and can each include a second side that will be soldered to pads on a chip substrate 594b. The chip substrate 594b will directly support the integrated circuits, which are provided in the chip package and are typically connected to a circuit substrate (not shown) through a plurality of solder carriers 561 . The embodiments shown in FIGS. 37-37A thus illustrate a situation in which the grid array connector system can be more tightly integrated with the die package. Naturally, such a configuration would require a slightly larger wafer substrate 594b than would normally be required, but the potential for improved electrical performance may make such a configuration desirable. One benefit of such a configuration is that the wafer substrate 594b can be confined to the grid array connector system prior to soldering the integrated circuit to the wafer substrate 594b, thereby ensuring that the integrated circuit can be mounted on the active system. Naturally, the insert 580 design shown in this embodiment can also be used in a more conventional configuration and allows the grid array connector system to be soldered directly to a circuit substrate.

Note that although the insert 580 is not required, the use of an insert 580 can help with coplanarity of the mating surfaces. An insert 580 tends to be between 0.3 and 2.0 mm in thickness, it will be appreciated that a thinner design will reduce compliance and thus make it more difficult to deal with coplanarity, while a thicker design will take up more space and ultimately becomes even less desirable for a connector.

38 and 39 show a schematic diagram of an embodiment in which the grid array connector system 670 is more tightly integrated into the chip package. As shown, a circuit substrate 610 supports a wafer substrate 694b, which in turn supports an integrated circuit 694a. An insert 680 is mounted on the wafer substrate 694b and connected to a sub-grid array module 670a, the sub-grid array module 670a includes a base, a substrate and a plurality of terminated cables. A heat sink 605 is configured to be thermally connected to the integrated circuit 694a to aid in heat dissipation. As can be appreciated, the illustrated design provides a significant variation. The interposer 680 may be directly soldered to both the substrate (which is not shown separately) and the wafer substrate 494b or may be soldered to only one of the two and employ a contact end that is pressed against a pad on the non-soldered side. An embodiment of the solder side/press side is shown schematically in FIG. 39 , where a substrate 650 engages an insert 680 . The interposer 680 includes a frame body 681 that holds a plurality of contact members 682, the plurality of contact members 682 have a butt end 682a that is flexed when engaged with the signal pad 656 and is configured to be soldered to another circuit substrate or A butted end 682b of the wafer substrate. Depending on the configuration, the heat sink 605 can be pressed against the grid array connector system 670 to ensure an electrical connection (often using a compressible element), or if the grid array connector system 670 is soldered in place, the heat sink 605 may be provided with a gap relative to the grid array connector system 670 .

As can be appreciated from FIGS. 40-42, another embodiment of a grid array connector system 770 is shown, the grid array connector system 770 includes a connector 798 mounted on a substrate 750, and the connector 798 is configured to interface with a connector 799 on a circuit substrate 710 . The connector 798 includes a base 798a that holds a plurality of terminals 798b connected to the substrate 750 in a desired manner, often by a solder attachment. The connector 799 includes a base 799a that holds a plurality of terminals 799b connected to the circuit substrate 710 via solder connections 799c.

Another embodiment is shown in Figures 43-44. Although the internal configuration can be any of the above-described internal designs, a grid array connector system 870 includes a cover 875 having a securing opening 877 . The cover 875 includes a retaining arm 876 that engages a locking element on the base 871 874. Fastening aperture 877 is aligned with a fastening opening 884 extending through grid array connector system 870 (including through substrate 850 and an insert 880). The grid array connector system 870 still has optional feet 873 to help it align with a mating circuit substrate, but the grid array connector system 870 can be held by a separate fastener. The illustrated embodiment thus provides an alternative method of attaching the grid array connector system 870 in place.

45-48 illustrate an embodiment of a computing system 901 that includes the components of FIGS. 28-30 and also includes an upper compressible element 964.1 similar to the compressible element 464 provided in FIGS. 31-36. For ease of illustration, computing system 901 is described with respect to the poses shown in Figures 45-48, using the terms "up", "down", and the like. It should be understood that other gestures are also within the scope of this disclosure.

A heat sink 905 and an attachment element 906 are connected to a lower holding frame 907 by holding legs 908 located on a bottom side 910b of a circuit board 910, and the holding legs 908 hold the frame 907 from below extend. A chip package 994 and a plurality of upper grid array connector systems 970.1 connected to a circuit substrate 950 are located between a top side 910a of the circuit substrate 910 and a lower surface of the heat sink 905. As such, the circuit substrate 950 is an upper circuit substrate and the circuit substrate 910 is a lower circuit substrate.

The circuit substrate 950 can be a conventional circuit substrate like the aforementioned embodiments or any other suitable substrate, such as, but not limited to, a ceramic and/or plastic-metal composite structure. The circuit substrate 950 includes a mounting surface and a connecting surface, and one or more connecting vias 952 extend between the mounting surface and the connecting surface. A ground plane may also be included inside the circuit substrate 950 to improve electrical performance.

Each upper grid array connector system 970.1 is similar to the embodiment discussed above, comprising a plurality of cables 920 held by a base 971 and connected to the connection vias on the circuit substrate 950 as described above. 952 Road. Similar to that shown in FIG. 33, the circuit substrate 950 may be connected to an interposer (such as the interposer 480) having a frame (such as the frame 481) that holds a plurality of contacts. The upper grid array connector systems 970.1 are positioned to form a central channel 978 between the upper grid array connector systems 970.1. The die package 994 is positioned within a central channel 978 formed by a plurality of upper grid array connector systems 970.1.

Circuit substrate 910 includes a substrate 911 having a connection region 998 aligned with die package 994 to provide additional signal paths for other components (or for mounted components below die package 994). The connection region 998 is at a central portion of the substrate 911 . As shown in FIG. 47 , the circuit substrate 950 is mounted at the center of the base material 911 above the connection area 998 and above the portion of the circuit substrate 910 outside the connection area 998 , but the circuit substrate 950 is not connected to the entire base of the circuit substrate 910 . Materials 911 overlap. In this way, a portion of the base material 911 extends outward from each edge of the circuit substrate 950 by a predetermined distance, thereby providing a reinforcing ring 913 . The stiffener ring 913 is attached to the upper grid array connector system 970.1 and the connection vias 952 on the circuit substrate 950 on which the die package 994 is mounted provide reinforcement, planarization and reinforcement. The stiffener ring 913 provides planarity of the connection vias 952 on the circuit substrate 950 because the connection vias 952 on the circuit substrate 950 surround the die package 994 . The substrate 911 also has alignment apertures 958 through which the retention legs 908 extend. The alignment openings 958 are configured to penetrate the reinforcement ring 913 so that the alignment openings 958 are outside the circuit substrate 950 , but the alignment openings 958 do not interfere with the performance provided by the reinforcement ring 913 .

The heat spreader 905 includes a protrusion 905a designed to press against the chip package 994 to ensure that a good thermal connection exists between the heat spreader 905 and the chip package 994. In order to ensure that there is a sufficiently effective thermal connection between the heat spreader 905 and the die package 994, one side may contain certain types of The thermal interface material (TIM) can be a paste or other suitable materials. Chip package 994 may be soldered directly to heat spreader 905 if better thermal efficiency is required. As can be appreciated, the heat spreader 905 presses against both the die package 994 and the upper grid array connector system 970.1 and thus ensures that both are pressed firmly in place and a reliable connection is maintained.

As can be appreciated, it is desirable that the interface between die package 994 and heat sink 905 define the vertical position of heat sink 905 because the thermal connection between die package 994 and heat sink 905 affects the amount of heat removed from die package 994 . The illustrated computing system 901 includes an upper compressible element 964.1 that ensures that the heat sink 905 is pressed against the grid array connector system 970.1 with the required force (and thus allows the heat sink 905 to be opposed to the circuit). Substrate 910 undulates in vertical position). The upper compressible element 964.1 includes a base 965 having a plurality of compressible fingers 966 extending from the upper surface of the base 965 and a plurality of retaining arms 967 extending from the lower surface of the base 965. The retaining arms 967 engage the retaining tabs 971a on the base 971 to secure the upper compressible element 964.1 to the base 971. The base 965 abuts the base 971 and the compressible fingers 966 engage the lower surface of the heat sink 905 . The upper compressible element 964.1 differs from the compressible element 464 shown in FIG. 33 in that a single upper compressible element 964.1 is affixed to all of the grid array connector systems 970.1, rather than multiple independent ones as shown in FIG. 33 The compressible element 464. The single upper compressible element 964.1 of this embodiment has a continuous base 965 with a centrally located notch 968 that is larger than the periphery of the die package 994. A plurality of compressible fingers 966 are disposed around the base 965 such that the compressible fingers 966 are disposed above each base 971 . In one embodiment, the notch 968 conforms to the shape of the perimeter of the die package 994 . In one embodiment, the notch 968 is square. The upper compressible element 964.1 preferably includes a plurality of catch arms 967 that engage respective catch catches 971a.

As can be appreciated, although mounting the grid array connectors 970.1 on all four sides of a die package 994 provides a tighter connection for the die package 994 and reduces the length of any traces between the die package 994 and the cables 920 (thereby reducing the insertion loss to a predetermined level), but also consider mounting the upper grid array connector system 970.1 on fewer sides of the die package 994 (in order to have the same number of connections, the upper grid array connector system 970.1 naturally would have to be bigger).

The embodiment of computing system 901 shown in FIGS. 45-48 also includes a plurality of lower grid array connector systems 970.2 and lower compressible elements 964.2 between bottom side 910b of circuit substrate 910 and lower retention frame 907.

The lower holding frame 907 includes a notch 915 passing through a central portion of the lower holding frame 907 .

Each lower grid array connector system 970.2 may be connected to the circuit substrate 910 in a manner similar to the previous embodiment, or may be connected directly to the circuit substrate 910. Each lower grid array connector system 970.2 is similar to the embodiments discussed above, including a plurality of cables 920 held by a base 971 and connected to the circuit substrate 910. The location of the lower grid array connector system 970.2 may mirror the location of the upper grid array connector system 970.1.

The lower compressible element 964.2 may be formed identically to the upper compressible element 964.1 and such specific details will not be described. In use, the lower compressible element 964.2 is inverted relative to the upper compressible element 964.1. Lower compressible element 964.2 compresses lower grid array connector system 970.2 into engagement with circuit substrate 910.

To form computing system 901, wafer package 994, upper grid array connector system 970.1 and circuit substrate 950 are electrically connected to circuit substrate 910. The upper compressible elements 964.1 are attached to the plurality of bases 971 of the plurality of upper grid array connector systems 970.1. The heat sink 905 is positioned over the upper compressible element 964.1 and the protrusions 905a on the heat sink 905 pass through the indentations 968 in the upper compressible element 964.1 and through the central channel 978 formed by the plurality of upper grid array connector systems 970.1, to bond the top surface of the chip package 994 . The plurality of lower grid array connector systems 970.2 are electrically connected to the circuit substrate 910, and the lower compressible elements 964.2 are attached to the plurality of bases 971 of the plurality of lower grid array connector systems 970.2. The lower holding frame 907 is then attached to the heat sink 905 by passing the holding legs 908 of the lower holding frame 907 through the alignment openings 958 on the circuit substrate 910 . Retention legs 908 are engaged by attachment elements 906 of heat sink 905 to form a sandwich construction. The connection area 998 of the circuit substrate 910 is accessible from below the computing system 901 through the notch 915 in the lower retention frame 907 and through the notch 968 in the lower compressible element 964.2.

Figures 49-54 illustrate another embodiment of a computing system 1001 like the embodiment shown in Figures 29 and 45 (die package not shown in Figures 49-54). Computing system 1001 includes grid array connector system 270, except that interposer 280 is not provided. As such, the plurality of cables 220 are directly terminated to the circuit substrate 250 in the manner described with respect to FIGS. 1-7 and 17-27C and the specific details are not repeated herein. The computing system 1001 further includes a second circuit substrate 1010 , and each cable 220 is connected to the second circuit substrate 1010 through a terminal 1080 . In this embodiment, terminals 1080 are used in place of inserts 280 .

The second circuit substrate 1010 like the circuit substrates 210, 310, 410, 610, 710 can be a conventional circuit substrate or any other desired substrate, such as but not limited to a ceramic and/or plastic-metal composite structure. The second circuit substrate 1010 includes a mounting surface 1010a and a connection surface 1010b, wherein more than one connection path having a conductive support via 1053 therein is on the second circuit substrate 1010 Inside and extending between the mounting surface 1010a and the connecting surface 1010b. In one embodiment, the supporting guide hole 1053 is cylindrical. In one embodiment, each support via 1053 can be connected to a signal pad 1058 on the connection surface 1010b of the second circuit substrate 1010 through a short trace 1057, as shown in FIG. 52, and can be a part of a solder ball. Solder mounts 1061 can be located on signal pads 1058 . Alternatively, the solder carrier 1061 may be located on the end of the support via 1053 at the connection surface 1010b and the short trace 1057 eliminated.

Each terminal 1080 includes a press-fit portion 1087 and a flexible portion 1088 . The press-fit portion 1087 is sized to conform to the inner dimension of the support guide hole 1053 when inserted into the support guide hole 1053 . When inserted, the press-fit portion 1087 contacts the support via 1053, thereby achieving an electrical connection.

In the embodiment shown, the press fit 1087 is formed by an elongated circular or oval body 1087a having an opening 1087b therethrough. The body 1087a may be larger than the inner size of the support guide hole 1053, so that when the press-fit portion 1087 is inserted into the support guide hole 1053, the body 1087a itself deforms and collapses to reduce the diameter of the opening 1087b. In one embodiment, the flexible portion 1088 is formed by a folded-back arm having a hooked end. As shown, the foldback arm consists of a first portion 1088a extending perpendicular to the body 1087a from one end of the body 1087a, a second curved portion 1088b extending from the opposite end of the first portion 1088a, and the opposite end from the second curved portion 1088b A third portion 1088c extending overlying the first portion 1088a is formed such that the third portion 1088c "folds back" over the first portion 1088a through the second curved portion 1088b. The hooked end portion is formed by a hooked end portion 1088d extending from the opposite end of the third portion 1088c and extending beyond the press-fit portion 1087 by a predetermined distance. The free end of the hook-shaped end portion 1088d faces the body 1087a and the support guide hole 1053 and the mounting surface 1010a. The flexible portion 1088 extends outward from the supporting via 1053 as shown in FIG. 52 (only the supporting via 1053 is shown in FIG. 52 and the second circuit substrate is not shown) 1010).

When the circuit substrate 250 is docked with the second circuit substrate 1010 , the signal pads 256 on the connection surface 251 b of the circuit substrate 250 are connected to the third portion 1088 c of the flexible portion 1088 of the terminal 1080 . The turned-back third portion 1088c and hooked end portion 1088d flex toward the first portion 1088a. Preferably, the hooked end portion 1088d engages the support guide hole 1053 when the flexible portion 1088 is flexed. The engagement of the hooked end portion 1088d with the support guide hole 1053 provides several advantages. Engagement on the support guide hole 1053 produces a wiping action. Additionally, when the hooked end portion 1088d directly engages the support guide hole 1053, another path can be provided for the electrical path through the terminal 1080 because the signal can travel from the cable 220 along the third portion 1088c to the hooked end portion 1088d and then to support via 1053. The electrical path through the terminal 1080 is maintained without the hooked end portion 1088d engaging the support via 1053.

Other shapes for the flexible portion 1088 that allow for flexure are also contemplated. For example, the flexible portion 1088 may be formed by a V-shaped first portion having a pair of arms extending from one end of the body 1087a, an inverted V-shaped second portion having a pair of arms extending from the first portion, and an opening. When the flexible portion 1088 is engaged by the circuit substrate 250, the first pair of arms and the second pair of arms flatten to at least partially close the opening such that the first pair of arms engages the support guide holes 1053 and the second pair of arms engages Signal pad 256 .

Compared to soldering the terminals 1080 to the second circuit substrate 1010, the use of the press-fit portion 1087 provides an easier assembly. In addition, since the terminals 1080 are not soldered to the second circuit substrate 1010 , the solder carriers 1061 can be directly soldered to the support vias 1053 . The flexible portion 1088 is also configured to accommodate irregularities with respect to the circuit substrate 210 and the second circuit substrate 1010 while still providing a reliable electrical path between the circuit substrate 210 and the second circuit substrate 1010 .

As can be appreciated from the various embodiments shown herein, different features of the different embodiments described herein may be combined together to form further combinations. For example, the internal design of the grid array connector system shown in FIGS. 1-7 can be used as an alternative to the internal design shown in FIGS. 20-25 . Likewise, various insert configurations can be employed (or omitted) depending on the application and system requirements. As a result, the embodiments shown herein are particularly well suited to provide a wide range of configurations not all shown individually in order to avoid repetition and unnecessary duplication.

The disclosure provided herein is characterized by preferred and exemplary embodiments thereof. Numerous other embodiments, modifications and variations within the scope and spirit of the appended claims will occur to those of ordinary skill in the art upon reading this disclosure.

901: Computing Systems

905: Radiator

906: Attachment element

907: Lower Hold Frame

908: Keep the legs

910: circuit substrate

958: Alignment opening

970.1: Upper Grid Array Connector System

970.2: Lower Grid Array Connector System

Claims (18)

A computing system includes: a lower circuit substrate; and an upper circuit substrate having a chip package mounted thereon and a plurality of connection paths outside the chip package therethrough, the upper circuit substrate being mounted on the On the lower circuit substrate, wherein the upper circuit substrate only partially overlaps the lower circuit substrate, so that a portion of the lower circuit substrate extends outward from the edge of the upper circuit substrate and forms a surrounding of the upper circuit substrate a reinforcing ring. The computing system of claim 1, further comprising a plurality of upper grid array connector systems mounted on the upper circuit substrate, each upper grid array connector system comprising a base held by a base and connected to the upper grid array connector system Multiple cables connecting multiple vias on the upper circuit substrate. The computing system of claim 2, further comprising: a compressible element including a base having compressible fingers extending therefrom and a catch arm extending therefrom, the catch arm engaging the a retaining tab on the base; and a heat sink engaged with the compressible finger and the chip package. The computing system of claim 3, wherein the compressible element is formed from a single base that engages all of the bases of the plurality of upper grid array connector systems. The computing system of claim 4, wherein the upper grid array connector system forms a central channel in which the die package is seated, and wherein the compressible element has a center channel aligned with the central channel A notch, the heat sink having a protrusion extending through the central channel and through the notch. The computing system of claim 5, further comprising a plurality of Each lower grid array connector system includes a plurality of cables held by a base. The computing system of claim 6, further comprising: a compressible element including a base having compressible fingers extending therefrom and a catch arm extending therefrom, the catch arm engaging the a snap-fit buckle on the base of the plurality of lower grid array connector systems; and a lower retention frame attached to the heat sink and engaged with the compressible fingers. The computing system of claim 1, further comprising a plurality of lower grid array connector systems mounted on the lower circuit substrate, each lower grid array connector system comprising a plurality of cables held by a base . The computing system of claim 8, further comprising: a compressible element including a base having compressible fingers extending therefrom and a catch arm extending therefrom, the catch arm engaging the snap-fit tabs on the base of the plurality of lower grid array connector systems; and a lower retention frame attached to a heat sink and engaged with the compressible fingers. The computing system of claim 9, further comprising: holding legs connecting the lower holding frame and the heat sink together, the holding legs passing through the reinforcement ring. A computing system for mounting a chip package, comprising: a first circuit substrate having a mounting surface and a connection surface opposite to the mounting surface, the first circuit substrate having a mounting surface on the mounting surface a first array of pads, the first array of pads is connected to the chip package, the first circuit substrate further includes a plurality of support vias extending from the mounting surface to the connection surface and the connection signal pads on the surface connected to respective support vias; a grid array connector system on one side of the chip package, the grid The grid array connector system includes a plurality of cables, each cable includes a pair of conductors, wherein each conductor is electrically connected to one of the supporting vias; a second circuit substrate has a mounting surface and is opposite to the mounting surface a connection surface of the second circuit substrate and a plurality of support vias extending from the mounting surface of the second circuit substrate to the connection surface of the second circuit substrate; and a terminal located in each of the support vias of the second circuit substrate and extending outward from the mounting surface of the second circuit substrate, each terminal includes: a press-fit portion, which is press-fitted into the respective support vias of the second circuit substrate and electrically connected to the respective support vias. connection; and a flexible portion extending outward from the press-fit portion and from the mounting surface of the second circuit substrate, wherein when the first circuit substrate and the second circuit substrate are butted together, The flexible portion is engaged with the signal pad of the first circuit substrate. The computing system of claim 11, wherein each flexible portion has a foldback arm having a hooked end, wherein a free end of the hooked end faces the second The mounting surface of the circuit board. The computing system of claim 12, wherein each press-fit portion includes a deformable body that can be press-fitted into the respective support vias on the second circuit substrate Deformed body deformation. The computing system of claim 13, wherein each of the support vias into which the press-fit portion of the second circuit substrate is inserted has a cylindrical shape. The computing system of claim 11, wherein each press-fit portion includes a deformable body that can be press-fitted into the respective support vias on the second circuit substrate Deformed body deformation. The computing system of claim 11, further comprising: a solder carrier associated with the first The supporting vias of the two circuit substrates are connected. The computing system of claim 11, further comprising: a plurality of first supports mounted on the mounting surface of the first circuit substrate; a plurality of second supports electrically connected to the plurality of first supports ; a base located on the first circuit substrate and at least partially covering the plurality of first supports and the plurality of second supports. The computing system of claim 11, further comprising a heat sink mounted on the first circuit substrate.

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