CN116667075A

CN116667075A - Computing system

Info

Publication number: CN116667075A
Application number: CN202310816140.5A
Authority: CN
Inventors: 布莱恩·K·洛伊德; 葛瑞格利·沃茨; 柯比·韦格纳; 凯伦·希礼; 布鲁斯·瑞德; 萨加尔·达维; 启韬·蔡
Original assignee: Molex LLC
Current assignee: Molex LLC
Priority date: 2020-02-07
Filing date: 2021-02-05
Publication date: 2023-08-29
Also published as: JP2021125462A; CN214627722U; TWI819598B; TWI766556B; TW202234776A; JP7158511B2; TW202137651A; CN113260207B; CN113260207A

Abstract

A computing system in which a grid array connector system is provided that includes a plurality of cables mounted on a substrate having a packaged chip mounted thereon. The plurality of cables each include a conductor connected to a support via in an opening on the substrate, and the conductor is connected to the support via. The substrate can be connected to a second substrate that provides a stiffener ring. The substrate is connectable to the second substrate by press-fitting flexible terminals in the second substrate.

Description

Computing system

The present application is a divisional application filed with the applicant of "Mo Liesi limited", the application date 2021, 02, month 05, 202110162282.5, and the title of the application "grid array connector system".

Technical Field

The present application relates to the field of connector systems, and more particularly to a connector system suitable for use in high data rate applications.

Background

Historically, computing device cases have been provided with some type of processor (disposed in a chip package) and connectors on a front panel of the case. The plurality of connectors and the processor are mounted on a circuit substrate (often referred to as a motherboard) and the circuit substrate includes a plurality of traces that connect the plurality of connectors to the processor so that information can be provided between the plurality of connectors and the processor. Unfortunately, as data rates have increased, such known system designs have become difficult to use due to losses in the circuit substrate.

Various Bypass (Bypass) connector systems are known to provide a connection between an input/output (IO) connector and an integrated circuit, such as but not limited to an Application Specific Integrated Circuit (ASIC) disposed in a chip package. One common configuration would be to have a first connector (often an IO connector) at a panel of a box and a second connector that interfaces with a circuit substrate (or another connector) near the chip package, where the first and second connectors are connected via a cable. As is known, the cable is much lower in loss than a standard circuit substrate and the use of a cable significantly reduces the loss between the first connector and the second connector. While such a situation is well suited for 56Gbps applications, particularly for applications employing pulse amplitude level 4 (PAM 4) coding, it becomes more challenging to keep the insertion loss available to support a channel length low enough as data rates increase towards 112Gbps (employing PAM 4 coding). Some options provide good electrical performance but are difficult to assemble and thus create process problems when attempting to build a component, such as a 1U server. As a result, certain individuals would appreciate a connector system that would allow a connection to a chip package with low loss and still allow easy assembly.

Disclosure of Invention

According to one aspect of the present application, there is provided a computing system comprising: a lower circuit substrate; and an upper circuit substrate having a chip package mounted thereon and a plurality of connection vias therethrough outside the chip package, the upper circuit substrate being mounted on the lower circuit substrate, wherein the upper circuit substrate only partially overlaps the lower circuit substrate such that a portion of the lower circuit substrate extends outwardly from an edge of the upper circuit substrate and forms a stiffener ring surrounding the upper circuit substrate.

According to an embodiment, the computing system further includes a plurality of upper grid array connector systems mounted on the upper circuit substrate, each upper grid array connector system including a plurality of cables held by a base and connected to a plurality of connection vias on the upper circuit substrate.

According to an embodiment, the computing system further comprises: a compressible element comprising a base having compressible fingers extending therefrom and retaining arms extending therefrom, the retaining arms engaging retaining buttons on the base; and a heat spreader coupled to the compressible fingers and the chip package.

According to an embodiment, the compressible element is formed by a single base that engages all of the pedestals of the plurality of upper grid array connector systems.

According to an embodiment, the upper grid array connector system forms a channel in which the chip package is disposed, and wherein the compressible element has a notch aligned with the channel, the heat spreader having a protrusion extending through the channel and through the notch.

According to an embodiment, the computing system further includes a plurality of lower grid array connector systems mounted on the lower circuit substrate, each lower grid array connector system including a plurality of cables held by a base.

According to an embodiment, the computing system further comprises: a compressible element comprising a base having compressible fingers extending therefrom and retaining arms extending therefrom, the retaining arms engaging retaining snaps on the base of the plurality of lower grid array connector systems; and a lower retention frame attached to the heat sink and engaged with the compressible fingers.

According to an embodiment, the computing system further comprises: and a holding leg connecting the lower holding frame and the heat sink together, the holding leg passing through the reinforcing ring.

A grid array connector system is disclosed for terminating conductors from a plurality of cables directly to a substrate. The conductors may be attached to a support via by a soldering operation and a plurality of standoffs fixedly mounted on the substrate. The conductor in the cable is connected to a signal pad on a connection surface of the substrate. The substrate may be configured to be attached to a chip substrate via a soldering operation that connects pads on a connection face of the substrate to pads on the chip substrate in a grid, and the grid array connector system may include solder mounts on the pads of the connection face. The signal pads may be arranged in differential pairs and may be partially surrounded by a plurality of ground pads. The signal pads on the substrate may be connected to the support via by a short trace that allows the pads to be positioned in a desired pattern, or the support via itself may be used as the signal pad. A pedestal may be formed directly on at least a portion of the plurality of cables and the substrate to provide a structure that provides stress relief for the plurality of cables and helps support the substrate.

Another grid array connector system has an internal design similar to the grid array connector system described above in a socket configuration so that a chip package can be mounted directly to the substrate or interposer (e.g., when an interposer is used).

One embodiment of a grid array connector system includes a base mounted on a plurality of cables in a grid arrangement and including a substrate. A first support is mounted on the substrate. The plurality of cables are each connected to a second mount, and the second mount is inserted into the first mount, the second mount being attached to a substrate to form an array of mounts on the substrate. The standoffs of the array and corresponding cables may be potted on the substrate. The conductor is connected to a signal pad on a connection face of the substrate and the pattern of the conductor may be different from the pattern of the signal pad because the signal pad may be moved on the connection face by employing short traces. The two supports are electrically connected together and to a ground plane on the mounting surface, which in turn is connected to one or more ground pads on the connection surface. The substrate may be directly soldered to a chip substrate supporting a chip package. The substrate may also be connected to the chip substrate via an interposer. The interposer may include a plurality of contacts extending between a first array of pads on the substrate to a second array of pads on the chip substrate.

In one embodiment, the interposer may be soldered to the substrate and either have a solder connection to a substrate (or circuit substrate) or have flex contacts that may engage other pads that may be disposed on a circuit substrate or substrate.

In one embodiment, a grid array connector system is configured to include an interposer having a plurality of deflectable contacts configured to engage a plurality of pads on a mating surface of a chip substrate including a chip package, and a first grid array connector on a first side of the chip package. A compressible element may be located on a pressing side of a base of the first grid array connector system. A second grid array connector system may be located on a second side of the chip package. A heat sink may be mounted on a chip package with the compressible elements of the respective grid array connector system ensuring that the grid array connector system is pressed by the heat sink to make electrical connection with pads on the mating face while allowing the interface between the heat sink and the chip package to control the relative vertical or z-axis position.

A grid array connector system is provided that includes a plurality of cables mounted on a substrate having a packaged chip mounted thereon. The plurality of cables includes a plurality of conductors connected to a plurality of support vias located in a plurality of openings of the substrate, and the plurality of conductors connected to the plurality of support vias. The substrate can be connected to a second substrate that provides a stiffener ring. The substrate can be connected to the second substrate by a flexible terminal press fit into the second substrate.

Drawings

The present application is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:

fig. 1 shows a perspective view of an embodiment of a cable terminated to a substrate.

Fig. 2 shows an exploded perspective view of a portion of the embodiment shown in fig. 1.

Fig. 3 shows a simplified exploded perspective view of an embodiment of a cable and support that can be connected together.

Fig. 4 shows a perspective view of an embodiment of a mount.

Fig. 5 illustrates a bottom view of an embodiment of a substrate.

Fig. 6 shows a top view of the substrate shown in fig. 5.

Figure 7 illustrates a side view of a cross section of an embodiment of a substrate.

Fig. 8 illustrates a perspective view of an embodiment of a grid array connector system.

Fig. 9 shows another perspective view of the embodiment shown in fig. 8.

Fig. 10 illustrates a partial bottom view of an embodiment of a substrate.

Fig. 11 shows a perspective view, partially broken away, of a grid array connector system.

Fig. 12 shows a side view of a grid array connector system configured to interface with a chip package that is connected to a connector located below the chip package.

Fig. 13 shows a side view of the embodiment of fig. 12 with the connector in a mated condition.

Fig. 14 shows a schematic diagram of an embodiment of a grid array connector system positioned in a system.

Fig. 15 shows a schematic diagram of two grid array connector systems connected by a cable set.

Fig. 16 illustrates a schematic diagram of an embodiment of a grid array connector system configured to include a chip socket.

Fig. 17 shows a perspective view of another embodiment of a grid array connector system mounted on a circuit substrate.

Fig. 18 shows a simplified perspective view of the grid array connector of fig. 17.

Fig. 19 shows a perspective partially exploded view of the embodiment of fig. 18.

Fig. 20 shows a perspective view of an embodiment of an internal design of a grid array connector system that can be used with the embodiment of fig. 18.

Fig. 21 shows a perspective, partially cut-away, partial view of an embodiment of an internal design of a grid array connector system.

Fig. 22 shows a perspective view of an embodiment of an internal design of a grid array connector system that can be used with the embodiment of fig. 18.

Fig. 23 shows a cut-away perspective view of fig. 22 taken along line 23-23.

Fig. 24 shows a simplified perspective view of the embodiment of fig. 23.

Fig. 25 shows a perspective view of an embodiment of a substrate.

Fig. 26 illustrates a side view of one embodiment of a grid array connector system mounted on a circuit substrate, wherein the grid array connector system includes an interposer.

Fig. 27A illustrates an embodiment of a contact suitable for use with an insert.

Fig. 27B illustrates another embodiment of a contact suitable for use with an insert.

Fig. 27C illustrates yet another embodiment of a contact suitable for use with an insert.

Fig. 28 shows a perspective view of another embodiment of a grid array connector system that can be used with a heat sink.

Fig. 29 shows a perspective partially exploded view of the embodiment of fig. 28.

Fig. 30 shows another perspective view of the embodiment shown in fig. 29.

Fig. 31 illustrates a side view of an embodiment of a grid array connector system that can be used with a heat sink.

Fig. 32 illustrates a simplified plan view of an embodiment of a chip package and multiple grid array connector system.

Fig. 33 illustrates a perspective view of an embodiment of a chip package and multiple grid array connector system.

Fig. 34 shows a perspective view of a grid array connector system as shown in fig. 33.

Fig. 35 shows another perspective view of the embodiment shown in fig. 34.

Fig. 36 shows a plan view of an embodiment of a chip package mounted on a circuit substrate, which can be used with the embodiment shown in fig. 33.

Fig. 37 illustrates a partial side view of an embodiment of a grid array connector system showing an alternative interposer construction.

Fig. 37A shows an enlarged simplified side view of the embodiment shown in fig. 37.

Fig. 38 shows a schematic view of a grid array connector system mounted on a chip substrate.

FIG. 39 shows a schematic view of an embodiment of a substrate to insert connection.

Fig. 40 illustrates a perspective, partially exploded view of an embodiment of a grid array connector system that can be mated with a circuit substrate via a mating connector.

Fig. 41 shows a perspective view of the grid array connector system shown in fig. 40.

Fig. 42 shows a perspective view of the docking connector shown in fig. 40.

Fig. 43 illustrates a perspective view of an embodiment of a grid array connector system.

Fig. 44 shows another perspective view of the embodiment shown in fig. 43.

FIG. 45 illustrates a top perspective view of an embodiment of a computing system.

FIG. 46 illustrates a bottom perspective view of the embodiment of the computing system shown in FIG. 45.

FIG. 47 illustrates an exploded top perspective view of components of the computing system shown in FIG. 45.

FIG. 48 illustrates a partial cutaway view from a top perspective view of the computing system shown in FIG. 45.

FIG. 49 is an exploded top perspective view of components of an embodiment of a computing system.

FIG. 50 is an exploded bottom perspective view of components of the computing system shown in FIG. 49.

FIG. 51 is a top perspective view of a terminal of the computing system shown in FIG. 49.

FIG. 52 is an assembled top perspective view of the components of the computing system shown in FIG. 49.

FIG. 53 illustrates a partial cutaway view from a top perspective view of the computing system shown in FIG. 49.

FIG. 54 is a top perspective view of components of the computing system shown in FIG. 49.

Detailed Description

The following detailed description illustrates exemplary embodiments, and the disclosed features are not intended to be limited to the explicitly disclosed combinations. Thus, unless otherwise indicated, features disclosed herein may be combined together to form other combinations not shown for purposes of brevity.

As can be appreciated from fig. 1-7, features of an embodiment are disclosed that allow for direct termination of a cable 20 to a substrate 50, which substrate 50 can be a conventional circuit substrate or any other desired substrate (such as, but not limited to, a ceramic and/or plastic metal composite structure). The substrate 50 includes a mounting surface 51a and a connecting surface 51b, wherein one or more connecting passages 52 extend between the mounting surface 51a and the connecting surface 51 b. While terminating one or both conductors from one cable to a substrate can be accomplished in a wide range of ways, it becomes more complex when attempting to terminate a greater number of cables in a compact array, particularly if good electrical performance is desired while providing the required flexibility of the manufacturing process. The illustrated embodiment includes a cable 20, the cable 20 having a pair of signal conductors 21 that can function as a differential pair. The pair of signal conductors 21 is surrounded by an insulating layer 23 and then the insulating layer is covered by a shielding layer 28 and then the shielding layer is covered by an overwrap 26. It is contemplated that a drain wire is not required in most applications, but may be included if desired and connected to the support if included.

To connect conductors 21 to signal pads 58 provided in a signal layer within substrate 50, each conductor 21 may be attached to a support via 53 (or via a solder or other known attachment means if desired) provided by substrate 50 by a solder 24. Fig. 7 shows a cross section of an embodiment of a support via 53 configuration. The conductor 21 can be inserted into an opening 43 in the substrate 50, the opening 43 being aligned with an opening 55, the opening 55 optionally including a taper 55a to assist in the easy insertion of the conductor 21. Preferably, the opening 43 will also include a ramp 47, the ramp 47 helping to guide the conductor 21 to the desired location corresponding to the support via 53 and then positioned such that an end of the conductor 21 is positioned adjacent a front side of the support via. A laser may then be used to weld the conductor 21 to the support via 53 or to braze the conductor 21 to the support via 53. In order to connect the shield 28 of the cable 20 to the ground pad 56 on the connection face, a support 30 is provided to connect the shield 28 to a ground plane 54 on the substrate 50.

If the conductor 21 is soldered to the support via 53, the solder will resist backing out when exposed to the high temperatures associated with soldering, and after soldering the conductor 21 to the support via 53, the standoff 30 can be attached to the substrate 50 and the shield 28 at a higher temperature (e.g., with a higher temperature solder) without fear of losing the connection between the signal conductor 21 and the support via 53. This in turn will allow the substrate 50 to be subsequently soldered to other structures using lower temperature solder once all the required cables are attached, thereby making the process of assembling a complete system easier to manufacture. Note that the use of solder to attach the standoff 30 to the ground plane 54 is not necessary, however, for some applications the standoff 30 may be attached by a conductive adhesive or may even be spot welded (potentially in multiple locations) by a laser.

As described above, in order to facilitate the installation of the conductor 21 into the substrate 50, the substrate 50 may be drilled with a tapered drill to obtain the structure shown in fig. 7. If a taper is provided, the taper angle 59 may be a wide range of angles, but typically will be from 15 degrees to about 40 degrees and the actual angle will depend, at least in part, on the spacing of the openings and the thickness of the substrate. Preferably, the taper angle 59 is sufficient to allow a pair of conductors to be naturally spaced apart to fit into two enlarged openings and then automatically align the two signal conductors in the separate and adjacent two openings 55 so that upon further insertion into the openings 55, the two conductors 21 will automatically be guided to positions corresponding to the two support vias 53.

To allow for improved attachment and proper ball grid array (ball grid array) spacing, the support vias may be connected to a signal pad 58 by a short trace 57, as shown in fig. 5. As can be appreciated, only a portion of the short trace 57 is visible due to solder masking (holder mask). A solder loader 61, which may be a solder ball, may be positioned on both ground pad 56 and signal pad 58 to allow attachment of the grid array. Note that the design shown shows a uniform layout of solder balls but a non-uniform pitch layout is also contemplated. An additional benefit of this configuration is that attaching a solder mount 61 to a solder joint is less repeatable from a manufacturing standpoint, and that supporting the via 53 connected to the signal pad 58 with the short trace 57 allows a solder mount 61 to be positioned on conventional pads in a more reliable manner.

Although the weld 24 is shown to be fairly strong, it is generally desirable to be able to provide some stress relief for the cable. In one embodiment, a portion of the plurality of wires and the substrate may be encapsulated in an insulating material (potentially using a low pressure molding process) to provide a base 71. The base 71 may include attachment features 72 (such as shown in fig. 8) to form a grid array connector system 70. The grid array connector system 70 may include a substrate 50, the substrate 50 having a connection face 51b, the connection face 51b including a plurality of solder mounts 61 forming a connection pattern 62. As can be appreciated, the internal design of the grid array connector system may be arranged in accordance with fig. 1-7.

As can be appreciated from fig. 9, in a compact low profile configuration, a relatively large connection pattern may be formed to allow for a greater number of connections, thereby enabling the grid array connector system to be more closely positioned to a corresponding ASIC. While such a configuration is beneficial for connecting a large number of differential pairs together, the resulting size can cause problems when attempting to solder attach the connection pattern to another surface, as that size can prevent sufficient thermal energy from reaching the internal solder loading. To prevent the occurrence of uneven thermal energy distribution (and the resulting problems with connectivity), one or more thermal vias (which may be slots or openings) may be provided in the substrate and/or base to allow improved and more uniform heat transfer to all of the solder mounts. The thermal vias may come from the sides or extend through the pedestals 71 and the substrate 50 within the connection pattern 62 (thereby creating a break in the connection pattern 62). The decision to include thermal vias to improve the thermal performance of the solder attachment will be based on the size of the pattern connection and many other parameters, such as cycle times and materials, and thus remain to be determined as needed by one of ordinary skill in the art.

As described above, in certain embodiments, the solder loader 61 is attached to the signal pad 58 spaced apart from the support via 53, as shown in fig. 5. Note that it has the advantage of avoiding soldering to a soldered surface that is inconsistent and may be difficult to reliably attach a solder ball prior to reflow. As can be appreciated, such a configuration allows isolation to be advantageously used by surrounding the signal pad 58 with the ground pad 56, such as shown in fig. 10. A disadvantage of such a configuration is that a short trace 57 is required to connect the support via 53 to the signal pad 58 and the short trace can affect signal integrity. Fig. 11 shows another embodiment having a configuration that allows for direct attachment of the via-solder ball. As shown, the conductor 21 'is supported by an insulating layer 23', the insulating layer 23 'being located in a support 30', the support 30 'being attached to the ground plane 54'. The conductor 21 'extends through a tapered via 47' and the end portions are positioned and soldered to corresponding pads. A plurality of solder mounts 61 are then positioned over all of the pads in a conventional manner. For larger gauge conductors, such a configuration may be easier to handle because the spacing between conductors will be more consistent with the spacing required for the ball grid array. However, as is known, it is challenging to uniformly solder the solder balls to a soldered surface, especially if the soldered surface is not completely uniform. One possible approach to this is to extend the support via a smaller amount into the substrate and solder the conductor to the support via below the top surface so that the location where the solder mount is placed is not part of the solder joint itself. Such a configuration may allow for good electrical performance while providing a more consistent surface for placement of solder balls, as the resulting contact area supporting the vias may provide a circular rim-shaped surface or may even be slightly concave.

As can be appreciated from fig. 12-13, one potential application of the embodiment of fig. 1-11 is to include a mezzanine connector 185 in a grid array connector system 170. As is known, mezzanine connectors can be made to function in a compact space, can be hermaphroditic, and can have excellent electrical performance due to the ability to provide a relatively linear configuration. Thus, the illustrated embodiment includes a mezzanine connector 185, the mezzanine connector 185 allowing a reversible connection between the grid array connector assembly 170 and a package 194 mounted on a substrate 150 '(which may be any desired type of substrate, as described above, with the substrate 150' mounted on another mezzanine connector 185). Such a configuration may provide excellent electrical performance while also providing low insertion force for the chip package to interface with the grid array connector assembly 170. As can be appreciated, one advantage of this design is to allow the chip package 194 to be attached to a connector separate from the substrate 150' and which can be mated to a different mating connector. This allows the two parts to be machined independently and can help reduce scrap and/or rework. Naturally, the design shown also allows for quick replacement of existing chip packages (which can be made up of an integrated circuit of a desired design and any other typical structure provided in a chip package) with a higher performance chip package, if desired.

Fig. 14 shows a simplified schematic of another potential configuration. A first connector 191 is located adjacent a box mounting face and is connected to a grid array connector system 170 via a cable set 193 (which includes a plurality of cables). A chip package 194 is mounted directly to the grid array connector system and a heat sink 195 is disposed on the chip package. As can be appreciated, such a system allows additional flexibility in the system, particularly if connector 191 is removably mounted (thereby allowing for complete updating if desired).

Note that in some embodiments, the substrate-attached grid array connector system may also be provided in a socket design having a plurality of contacts configured to attach directly to a plurality of pads on the ASIC package. For example, such a grid array connector system may include an interposer (which has a plurality of deflectable contacts) and the base would be formed in a socket-type shape (which is slightly more complex) that would allow for the elimination of a second connector and thus be satisfactory. As schematically illustrated in fig. 16, the grid array connector system 170' is configured to include a receptacle assembly that directly receives a chip package and that includes a clamping member 186 (which may be integrally provided or separately provided) to hold the chip package 194 in place. Although a rotating clamping member 186 is shown and is quite common in known chip packages, the clamping member is not so limited and a wide range of clamping configurations are possible. In some embodiments, for example, the clamping element may be integrated into a heat sink and can be attached by separate fasteners. While conventional socket designs are less than ideally suited for high signal transmission frequencies and corresponding high data rates due in part to the terminal designs and uniform spacing, the illustrated embodiments overcome these limitations by a more custom and less uniform grid array along with the ability to extremely cleanly (electrically) connect wires to multiple contacts of a bonded chip package in a grid array connector system.

As can be appreciated from fig. 15, the use of the grid array connector system disclosed herein is not limited to a particular application, such as a bypass application. This technique works well as a jumper (jumper) between two chip packages and allows significantly more flexibility in the location of the chip packages. For example, one or more of the grid array connector systems 170a, 170b can be located adjacent a liquid cooling seat at the rear of the adjacent device (which can reduce the need for air to flow through the chassis of the server). Further, although the two grid array connector systems 170a, 170b are shown as being connected together by a cable set 193, in one embodiment, three or more grid array connector systems (and corresponding chip packages) can be connected together by a cable set to help provide improved High Performance Computing (HPC) performance.

Turning to fig. 17-27C, another embodiment of a grid array connector system 270 is shown. The grid array connector system 270 includes a base 271, the base 271 being positioned on a substrate 250, and the plurality of cables 220 terminating to a substrate 250. In one embodiment, the plurality of cables are arranged in a plurality of columns of four, which provides the required compactness and density, but other configurations are suitable, depending on the application. Similar to the substrate 50 described above, the substrate 250 includes a mounting surface 251a and a connection surface 251b and a plurality of connection passages 252 extend between the mounting surface 251a and the connection surface 251 b. The substrate 250 may further include ground planes 319 a, 319 b inside to help provide improved electrical performance. The plurality of connecting passages 252 include two openings 243, each of the two openings 243 being aligned with an opening 255 in a support via 253. Substrate 250 provides a grid arrangement of signal pads 256 and ground pads 258 on the connection face, and pads 256, 258 may be connected to a chip substrate or interposer (such as interposer 280) or directly on circuit substrate 210.

The plurality of cables 220 are terminated to the substrate 250 by employing a first mount 240a and a second mount 240b, and once terminated, the substrate and both mounts can be held by a holding molding 277, which holding molding 277 can be a low pressure molding or a potting compound. As can be appreciated, the base 271 includes a plurality of fingers 275, the plurality of fingers 275 forming a passageway through which a plurality of cables extend, and the base 271 includes a plurality of alignment feet 273, the plurality of alignment feet 273 being usable to align the base with a pair of docking components.

The first support 240a may be mounted on the substrate 250 in a manner similar to the manner in which the support 30 is attached to the substrate 50 and the cables 220 are first connected to the second support 240b, and in one embodiment, a shield 228 of each of the plurality of cables 220 is electrically connected to the corresponding second support 240b (via solder or fusion or conductive adhesive). The second support 240b is abutted against the first support 240a, and the first support 204a and the second support 240b may be held together by an adhesive, a weld, or an interference fit (such as a recess 241 on the first support 240a pressing against the second support 240b, as shown in fig. 20-21). In other words, an interference fit may suitably hold the first and second standoffs 240a, 240b together.

As described above with respect to the substrate 50, the substrate 250 includes a plurality of openings 243, and the plurality of openings 243 may each have a sloped surface 247, and the sloped surface 247 may be used to guide the conductors 221 in the cable 220 to a desired location. This may cause the two conductors 221 to change from a first spacing 229a to a second spacing 229b that is different from the first spacing. In one embodiment, the second spacing 229b is at least 50% greater than the first spacing 229a to provide an improved layout of pads on the connection face 251 b. The spacing so modified is optional but has been determined to be beneficial for cables having conductors of small size. The conductor 221 is mounted to the support via 253 (preferably by solder 224, although other attachment methods may be employed as described above). The support via 253 may be electrically connected to the signal pad 256 on the connection face via a short trace 257 in the substrate 250 (if such a signal pad is independent of the support via 253).

As previously described, pads 256, 258 on substrate 250 may be directly connected to pads on another surface (such as circuit substrate 210) by solder. However, as shown in fig. 26, a different option is possible. Instead of soldering the substrate 250 to the circuit substrate 210, an interposer element 280 may be used to connect pads on the substrate 250 to pads on the circuit substrate 210. The insert 280 includes a frame 281, the frame 281 holding a plurality of contacts 282, the plurality of contacts 282 being engageable with pads on both sides of the insert. Contacts 282a, 282b, 282C are shown in fig. 27A-27C and may be held by frame 281. The contact 282a includes two end portions 283a and an intermediate portion 284a, the intermediate portion 284a not being configured to flex in a significant manner. Contact 282b includes two end portions 283b and an intermediate portion 284b, with intermediate portion 284b configured to flex. Contact 282c includes an end 283c and an end 283c', wherein an intermediate portion 284c is not intended to flex in a significant manner. As can be appreciated, these contacts may have multiple points of contact at one or both ends and may be compressible or incompressible as desired depending on the application. In addition, because there may be multiple ground connections, it may be desirable for the ground contacts to be configured differently (e.g., with different impedances) than the signal contacts to help properly adjust the impedance of the common and differential modes. Thus, the signal contacts may be configured differently than the ground contacts.

Fig. 28-30 illustrate one embodiment of a computing system 301, the computing system 301 including a heat sink 305. As shown, a grid array connector system 370 is mounted on multiple sides of a chip package 394. As shown, the grid array connector system 370 is located on four sides of the chip package 394 (both positioned on a circuit substrate 310), but the grid array connector system 370 may be mounted on a fewer side. A retaining frame 307 having a plurality of retaining legs 308 may be provided to help secure the heat sink 305 in a desired position with the attachment elements 306, and the heat sink 305 includes a protrusion 305a designed to press against the chip package 394 to ensure that a good thermal connection exists between the heat sink 305 and the chip package 394. To ensure a sufficiently effective thermal connection exists between the heat spreader and the chip package, one party may include some type of Thermal Interface Material (TIM), which may be a paste or other suitable material. If their thermal efficiency is required to be better, the chip packages may be soldered directly to the heat sink. As can be appreciated, the circuit substrate 310 may include a connection region 398 aligned with the chip package to provide additional signal paths for other components (or for mounting components directly beneath the chip package). As can be appreciated, the heat sink 305 presses against both the chip package 394 and the grid array connector system 370 and thereby helps ensure that both are firmly pressed into place and maintain a reliable connection.

Fig. 31 to 36 show another embodiment similar to the embodiment shown in fig. 28 to 30. A heat sink 405 with an attachment element 406 is connected to the holding frame 407, the holding frame 407 being located at a bottom side 410b of a circuit substrate 410. Between the circuit substrate 410 and the heat spreader 405 (at a top side 410a of the circuit substrate 410) is positioned a chip package 494 and a plurality of grid array connector systems 470. As can be appreciated from fig. 32, each of the plurality of grid array connector systems 470 is positioned with a first end 470a aligned with a first edge 494a of the chip package 494 and a second end 470b extending beyond a second edge 494b of the chip package 494, thereby improving connection density. Naturally, other configurations are also suitable if such a density is not required.

Similar to the embodiments described above, the grid array connector system 470 includes a plurality of cables 420, the plurality of cables 420 being held by a base 471 and connected to a substrate 450 and the substrate 450 being connected to an insert 480, the insert 480 having a frame 481 holding a plurality of contacts. The circuit substrate 410 includes a plurality of alignment openings 458, the plurality of alignment openings 458 configured to interface with a plurality of alignment feet 473. Naturally, on each side of the chip package, the plurality of alignment openings may be arranged in the same pattern to allow for commonality, or may be arranged in different patterns to ensure that only certain grid array connector systems may be positioned on certain sides. As can be appreciated, it is desirable that the interface between the chip package 494 and the heat spreader 405 define the vertical position of the heat spreader because the thermal connection between the chip package 494 and the heat spreader 405 affects the amount of heat removed from the chip package 494. The illustrated system includes a compressible member 464, the compressible member 464 ensuring that the heat spreader 405 is pressed against the grid array connector system 470 with a desired force (and thus allowing the heat spreader 405 to fluctuate in a vertical position relative to the circuit substrate 410). The illustrated compressible member 464 includes a base 465 having a plurality of compressible fingers 466 and includes a retaining arm 467, the retaining arm 467 engaging a retaining catch 471a to secure the compressible member 464 to the base 471. As can be appreciated, while mounting a grid array connector on each of the four sides of a chip package provides a tighter connection to the chip package and reduces the length of any traces between the chip package and the cable (thereby reducing insertion loss to a predetermined level), it is also contemplated that grid array connectors may be mounted on fewer sides of the chip package (grid array connector systems would naturally have to be larger in order to have the same number of connections). In addition, as can be appreciated from fig. 34, while the grid array connector is shown with 4 cables per column of cables, some other number of cables may be provided.

Turning to fig. 37-38, another embodiment of a grid array connector configuration is shown. The simplified partial view of fig. 37 shows a cable 520 attached to a second mount 540b, the second mount 540b attached to a first mount 540a, the first mount 540a in turn attached to the substrate 550. Thus, a portion of the design is similar to the previous embodiment. However, slightly different is that the insert 580 comprises a frame 581, the frame 581 holding a plurality of contacts 582 in the form of posts. The plurality of contacts will be soldered directly to the substrate 550 and may each include a second side that will be soldered to pads on a die substrate 512. The chip substrate 594b will directly support the integrated circuit that is disposed in the chip package and is typically connected to a circuit substrate (not shown) by a plurality of solder mounts 561. The embodiments shown in fig. 37-38 thus illustrate a situation where the grid array connector system can be more tightly integrated with the chip package. Naturally, such a configuration requires a chip substrate 594b that is slightly larger than is commonly required, but the potential for improved electrical performance may make such a configuration desirable. One benefit of such a configuration is that the chip substrate 594b may be limited to a grid array connector system before the integrated circuit is soldered to the chip substrate 594b, thereby ensuring that the integrated circuit can be mounted to the active system. Naturally, the interposer design shown in this embodiment may also be used in a more conventional configuration and allows the grid array connector system to be soldered directly to the circuit substrate.

Note that although an insert is not required, the use of an insert may help to handle coplanarity of the mating surfaces. An insert will tend to be between 0.3 and 2.0mm in thickness, it will be appreciated that thinner designs will reduce compliance and thereby make it more difficult to handle coplanarity, while a thicker design will take up more space and eventually become less desirable for a connector.

Fig. 38 shows a schematic diagram of an embodiment in which the grid array connector system 670 is more tightly integrated into a chip package. As shown, a circuit substrate 610 supports a chip substrate 694b, the chip substrate 694b in turn supporting an integrated circuit 694a. An interposer 680 is mounted on the chip substrate 694b and is connected to a sub-grid array module 670a, the sub-grid array module 670a including a base, a substrate, and a plurality of terminated cables. A heat sink 605 is configured to be thermally coupled to the integrated circuit 694a to aid in heat dissipation. As can be appreciated, the illustrated design provides a significant variation. The insert may be directly soldered to both the substrate (which is not separately shown) and the die substrate 494b or may be soldered to only one of the two and employ a contact end that is pressed against a pad on the non-soldered side. One embodiment of the welding/pressing side is schematically illustrated in fig. 39, where a substrate 650 engages an insert 680. The interposer includes a frame 681, the frame 681 holds a plurality of contacts 682, the plurality of contacts 682 having a mating end 682a that flexes when engaging the signal pads 656, and a mating end 682b configured to be soldered to another circuit substrate or die substrate. Depending on the configuration, the heat spreader may be pressed against the grid array connector system to ensure an electrical connection (often with a compressible element), or if the grid array connector system is soldered in place, the heat spreader may be provided with a gap relative to the grid array connector system.

As can be appreciated from fig. 40-42, another embodiment of a grid array connector system 770 is shown, the grid array connector system 770 comprising a connector 798 mounted to a substrate 750, and the connector 798 is configured to mate with a connector 799 on a circuit substrate 710. The connector 798 includes a base 798a that holds a plurality of terminals 798b that are connected to the substrate 750 in a desired manner, often by a solder attachment. The connector 799 includes a base 799a that holds a plurality of terminals 799b, the plurality of terminals 799b being connected to the circuit substrate 710 via solder connections 799c.

Another embodiment is shown in fig. 43-44. Although the internal configuration may be any of the internal designs described above, a grid array connector system 870 includes a cover 875 having a fastening aperture 877. The cover 875 includes a retaining arm 876, the retaining arm 876 engaging a locking element 874 on the base 871. The fastening aperture 877 aligns with a fastening opening 884 extending through the grid array connector system 870, including through the substrate 850 and an insert 880. The grid array connector system still has optional feet 873 to help align it with a pair of circuit substrates, but the grid array connector system may be held by a separate fastener. The illustrated embodiment thus provides an alternative method of attaching a grid array connector system in place.

Fig. 45-48 illustrate an embodiment of a computing system 901 that includes the components of fig. 28-30 and further includes a compressible element 964.1 similar to the compressible element 464 provided in fig. 31-36. For ease of description, computing system 901 is described with respect to the poses shown in fig. 45-48, using the terms "upper," "lower," and the like. It should be understood that other poses are also within the scope of the present disclosure.

A heat sink 905 and an attachment element 906 holding leg 908 are connected to a lower holding frame 907, the holding frame 907 being located at a bottom side 910b of a circuit substrate 910, the holding leg 908 extending from the lower holding frame 907. A chip package 994 and a plurality of upper grid array connector systems 970.1 connected to a circuit substrate 950 are located between a top side 910a of the circuit substrate 910 and a lower surface of the heat sink 905. Thus, the circuit substrate 950 is an upper circuit substrate and the circuit substrate 910 is a lower circuit substrate.

The circuit substrate 950, like the previous embodiments, may be a conventional circuit substrate or any other suitable substrate such as, but not limited to, a ceramic and/or plastic metal composite structure. The circuit substrate 950 includes a mounting surface and a connection surface, wherein more than one connection via 952 extends between the mounting surface and the connection surface. The circuit substrate 950 may also include a ground plane inside to help provide improved electrical performance.

Each upper grid array connector system 970.1 is similar to the embodiments discussed above, including a plurality of cables 920 held by a base 971 and connected to connection channels 952 on a circuit substrate 950 as described above. Similar to that shown in fig. 33, the circuit substrate 950 may be connected to an interposer (such as interposer 480) having a housing (such as housing 481) that holds a plurality of contacts. The upper grid array connector system 970.1 is positioned to form a central passage 978 between the upper grid array connector systems 970.1. The chip package 994 is disposed within a central channel 978 formed by a plurality of upper grid array connector systems 970.1.

The circuit substrate 910 includes a substrate 911 with a connection area 998 aligned with the chip package 994 to provide additional signal paths for other components (or for mounting components below the chip package 994). The connection region 998 is at a central portion of the substrate 911. As shown in fig. 47, the circuit substrate 950 is mounted at the center of the base material 911 above the connection region 998 and above the portion of the circuit substrate 910 outside the connection region 998, but the circuit substrate 950 does not overlap the entire base material 911 of the circuit substrate 910. Thus, a portion of the substrate 911 extends outwardly from each edge of the circuit substrate 950 a predetermined distance, thereby providing a stiffener ring 913. The stiffener ring 913 provides stiffening, planarization, and reinforcement to the connection vias 952 on the circuit substrate 950 to which the upper grid array connector system 970.1 is connected and on which the chip package 994 is mounted. Since the connection channels 952 on the circuit substrate 950 surround the chip package 994, the reinforcement ring 913 provides flatness of the connection channels 952 on the circuit substrate 950. The substrate 911 also has alignment apertures 958 through which the alignment feet 973 extend. The alignment openings 958 are disposed through the stiffener ring 913 such that the alignment openings 958 are external to the circuit substrate 950, but the alignment openings 958 do not interfere with the performance provided by the stiffener ring 913.

The heat sink 905 includes a tab 905a that is designed to press against the chip package 894 to ensure a good thermal connection between the heat sink 905 and the chip package 994. To ensure that a sufficiently effective thermal connection exists between the heat spreader 905 and the chip package 994, one party may include some type of Thermal Interface Material (TIM), which may be a paste or other suitable material. If better thermal efficiency is required, the chip package 994 may be soldered directly to the heat sink 905. As can be appreciated, the heat spreader 905 presses against both the chip package 994 and the upper grid array connector system 970.1 and thereby helps ensure that both are firmly pressed into place and maintain a reliable connection.

As can be appreciated, it is desirable that the interface between the chip package 994 and the heat sink 905 define the vertical position of the heat sink 905 because the thermal connection between the chip package 994 and the heat sink 905 affects the amount of heat removed from the chip package 994. The illustrated computing system 901 includes an upper compressible element 964.1, the upper compressible element 964.1 ensuring that the heat sink 905 is pressed against the grid array connector system 970.1 with the required force (and thus allowing the heat sink 905 to fluctuate in a vertical position relative to the circuit substrate 910). The compressible element 964 includes a base 965, the base 965 having a plurality of compressible fingers 966 extending from an upper surface of the base 965 and a plurality of retaining arms 967 extending from a lower surface of the base 965. The catch arms 967 engage catch 971a on base 971 to secure the compressible member 464 to the base 971. The base 965 abuts the base 971 and the compressible fingers 966 engage a lower surface of the heat sink 905. The compressible element 964 differs from the compressible element 464 shown in fig. 33 in that a single compressible element 964 is secured to all of the grid array connector systems 970.1 rather than employing multiple separate compressible elements 464 as shown in fig. 33. The single compressible element 964 of this embodiment has a continuous base 965, the continuous base 965 having a centrally located notch 968, the notch 968 being larger than the periphery of the chip package 994. A plurality of compressible fingers 966 are disposed around the base 965 such that the compressible fingers 966 are disposed above each base 971. In one embodiment, the notch 968 conforms to the shape of the outer perimeter of the chip package 994. In one embodiment, the notch 968 is square. The compressible element 964 preferably includes a plurality of retaining arms 967 that engage with respective retaining buttons 971 a.

As can be appreciated, while mounting the grid array connector 970.1 on each of the four sides of a chip package 994 provides a tighter connection for the chip package 994 and reduces the length of any traces between the chip package 994 and the cable 920 (thereby reducing the insertion loss to a predetermined level), it is also contemplated that the grid array connector system 970.1 may be mounted on fewer sides of the chip package 994 (the grid array connector system 970.1 would naturally have to be larger in order to have the same number of connections).

The embodiment of the computing system 901 illustrated in fig. 45-48 also includes a plurality of lower grid array connector systems 970.2 and a lower compressible element 964.1 between the bottom side 910b of the circuit substrate 910 and the lower retention frame 907.

The lower retaining frame 907 includes a notch 915 passing through a central portion of the lower retaining frame 907.

Each lower grid array connector system 970.2 may be connected to the circuit substrate 910 in a similar manner as the previous embodiments, or may be directly connected to the circuit substrate 910. Each lower grid array connector system 970.2, similar to the embodiments discussed above, includes a plurality of cables 920 held by a base 971 and connected to the circuit substrate 910. The position of the lower grid array connector system 970.2 can mirror the position of the upper grid array connector system 970.1.

The lower compressible element 964.2 can be formed identically to the upper compressible element 964.1 and as such, the details of which are not described. In use, the lower compressible element 964.2 is inverted relative to the upper compressible element 964.1. The lower compressible member 964.2 presses the lower grid array connector system 970.2 into engagement with the circuit substrate 910.

To form the computing system 910, the chip package 994, the upper grid array connector system 970.1, and the circuit substrate 950 are electrically connected to the circuit substrate 910. The upper compressible element 964.1 is attached to the plurality of bases 971 of the plurality of upper grid array connector systems 970.1. The heat spreader 905 is disposed over the upper compressible element 964.1 and the tabs 905a on the heat spreader 905 pass through the notches 968 on the upper compressible element 964.1 and through the central channel 978 formed by the plurality of upper grid array connector systems 970.1 to engage the upper surface of the chip package 994. The plurality of lower grid array connector systems 970.2 are electrically connected to the circuit substrate 910 and the lower compressible elements 964.2 are attached to the plurality of pedestals 971 of the plurality of lower grid array connector systems 970.2. The lower retaining frame 907 is then attached to the heat sink 905 by passing the retaining legs 908 of the lower retaining frame 907 through the alignment openings 958 on the circuit substrate 910. The retaining legs 908 are engaged by the attachment elements 906 of the heat sink 905 to form a sandwich construction. The connection area 998 of the circuit substrate 910 can be accessed from below the computing system 901 through the notch 915 in the lower retaining frame 907 and through the notch 968 in the lower compressible element 964.2.

Fig. 49-53 illustrate another embodiment of a computing system 1001 like the embodiment illustrated in fig. 29 and 45 (the chip package is not shown in fig. 49-53). In addition to the interposer 280 not being provided, the computing system 1001 includes a grid array connector system 270. As such, the plurality of cables 220 are directly terminated to the circuit substrate 250 in the manner described with respect to fig. 1-7 and 17-27C and the specific details are not repeated herein. The computing system 1001 further includes a second circuit board 1010, and each cable 20 is connected to the second circuit board 1010 through a conductive terminal 1080. In this embodiment, conductive terminals 1080 are used in place of insert 280.

The second circuit substrate 1010, like the circuit substrates 210, 310, 410, 610, 710, may be a conventional circuit substrate or any other desired substrate such as, but not limited to, a ceramic and/or plastic metal composite structure. The circuit substrate 1010 includes a mounting surface 1010a and a connection surface 1010b, wherein one or more connection paths having a conductive support via 1053 therein extend within the circuit substrate 1010 between the mounting surface 1010a and the connection surface 1010 b. In one embodiment, support via 1053 is cylindrical. In one embodiment, each support via 1053 can be connected to a signal pad 1058 on the connection surface 1010 of the circuit substrate 1010 by a short trace 1057, as shown in fig. 52, and a solder mount 1061, which can be a solder ball, can be located on the signal pad 1058. Alternatively, the solder mount 1061 may be located on the end of the support via 1053 at the connection face 1010 and the trace 1057 eliminated.

Each terminal 1080 includes a press-fit portion 1087 and a deflectable portion 1088. The press-fit portion 1087 is sized to conform to the inner dimensions of the support guide hole 1053 when inserted into the support guide hole 1053. When inserted, the press-fit portion 1087 contacts the support guide hole 1053, thereby making an electrical connection.

In the illustrated embodiment, the press-fit portion 1087 is formed from an elongated circular or oval-shaped body 1087a having an opening 1087b therethrough. The body 1087a may be larger than the inner dimension of the support guide hole 1053 such that when the press-fit portion 1087 is inserted into the support guide hole 1053, the body 1087b deforms and collapses onto itself to reduce the diameter of the opening 1087 b. In one embodiment, the deflectable portion 1088 is formed by a return arm having a hooked end. As shown, the return arm is formed from a first portion 1088a extending from one end of the body 1087a perpendicular to the body 1087a, a second curved portion 1088b extending from an opposite end of the first portion 1088a, a third portion 1088c extending from an opposite end of the second curved portion 1088b overlying the first portion 1088a such that the third portion 1088c is "folded back" over the first portion 1088a by the curved portion 1088 b. The hooked end is formed by a hooked end portion 1088d extending from an opposite end of the third portion 1088c and extending a predetermined distance beyond the press-fit portion 1087. The free end of hooked end portion 1088d faces body 1087a and support guide hole 1053. The deflectable portion 108 extends outwardly from the support via 1053 as shown in fig. 52 (fig. 52 only shows the support via 1053 and does not show the circuit substrate 1010).

When the circuit substrate 250 is docked with the circuit substrate 1010, the signal pads 256 on the connection face 251b of the circuit substrate 250 are connected to the third portions 1088c of the flexible portions 1088 of the terminals 1080. The folded back third arm 1088c and hooked end 1088d flex toward the first arm 1088 a. Preferably, when the deflectable portion 1088 deflects, the hooked end 1088d engages the support guide hole 1053. Engagement of hooked end 1088d with support guide hole 1053 provides several advantages. The engagement results in a wiping action on support via 1053. In addition, when hooked end 1088d directly engages support via 1053, an electrical path through terminal 1080 is provided to another path because signals can now pass from cable 220, along third arm portion 1088c, to hooked end 1088d and then to support via 1053. With hooked end 1088d not engaged with support via 1053, an electrical path is maintained through terminal 1080.

Other shapes for the deflectable portion 1088 that allow deflection are also contemplated. For example, the deflectable portion 1088 may be formed from a V-shaped first portion having a pair of arms extending from one end of the body 1087a, an inverted V-shaped second portion having a pair of arms extending from the first portion, and an opening. When the flexible portion 1088 is engaged by the circuit substrate 250, the first and second pairs of arms flatten to at least partially close the opening such that the first pair of arms engage the support vias 1053 and the second pair of arms engage the signal pads 256.

The use of the press-fit portion 1087 provides an easier assembly than soldering the terminal 1080 to the second circuit substrate 1050. In addition, since the terminal 1080 is not soldered to the second circuit substrate 1050, the solder mount 61 can be soldered directly to the signal via 1053. The flexible portion 1088 is also configured to accommodate irregularities with respect to the circuit substrates 210, 1010 while still providing a reliable electrical path between the circuit substrates 210, 1010.

As can be appreciated from the various embodiments illustrated herein, different features of the different embodiments described herein can be combined together to form further combinations. For example, the internal design of the grid array connector system shown in fig. 1-7 can be used as an alternative to the internal design shown in fig. 20-25. Likewise, various insert configurations can be employed (or omitted) depending on the application and system requirements. As a result, the embodiments illustrated herein are particularly well suited to providing a wide range of configurations not all of which are independently illustrated to avoid duplication and unnecessary duplication.

The disclosure provided herein describes features by way of preferred and exemplary embodiments thereof. Many other embodiments, modifications, and variations within the scope and spirit of the appended claims will occur to persons of ordinary skill in the art from a reading of this disclosure.

Claims

1. A computing system, comprising:

a lower circuit substrate; and

an upper circuit substrate having a chip package mounted thereon and a plurality of connection vias therethrough outside the chip package, the upper circuit substrate being mounted on the lower circuit substrate, wherein the upper circuit substrate only partially overlaps the lower circuit substrate such that a portion of the lower circuit substrate extends outwardly from an edge of the upper circuit substrate and forms a stiffener ring surrounding the upper circuit substrate.

2. The computing system of claim 1, further comprising a plurality of upper grid array connector systems mounted on the upper circuit substrate, each upper grid array connector system including a plurality of cables held by a base and connected to a plurality of connection paths on the upper circuit substrate.

3. The computing system of claim 2, further comprising:

a compressible element comprising a base having compressible fingers extending therefrom and retaining arms extending therefrom, the retaining arms engaging retaining buttons on the base; and

a heat spreader is coupled to the compressible fingers and the chip package.

4. The computing system of claim 3 wherein the compressible element is formed from a single base that engages all of the pedestals of the plurality of upper grid array connector systems.

5. The computing system of claim 4 wherein the upper grid array connector system forms a channel in which the chip package is disposed, and wherein the compressible element has a notch aligned with the channel, the heat spreader having a protrusion extending through the channel and through the notch.

6. The computing system of claim 5, further comprising a plurality of lower grid array connector systems mounted on the lower circuit substrate, each lower grid array connector system comprising a plurality of cables held by a base.

7. The computing system of claim 6, further comprising:

a compressible element comprising a base having compressible fingers extending therefrom and retaining arms extending therefrom, the retaining arms engaging retaining snaps on the base of the plurality of lower grid array connector systems; and

a lower retention frame is attached to the heat sink and engages the compressible fingers.

8. The computing system of claim 1, further comprising a plurality of lower grid array connector systems mounted on the lower circuit substrate, each lower grid array connector system comprising a plurality of cables held by a base.

9. The computing system of claim 8, further comprising:

10. The computing system of claim 8, further comprising: and a holding leg connecting the lower holding frame and the heat sink together, the holding leg passing through the reinforcing ring.