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TWI749479B - 具靜電放電防護之金屬晶粒的ic封裝結構 - Google Patents

具靜電放電防護之金屬晶粒的ic封裝結構 Download PDF

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TWI749479B
TWI749479B TW109107874A TW109107874A TWI749479B TW I749479 B TWI749479 B TW I749479B TW 109107874 A TW109107874 A TW 109107874A TW 109107874 A TW109107874 A TW 109107874A TW I749479 B TWI749479 B TW I749479B
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die
metal
functional
electrostatic discharge
discharge protection
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TW109107874A
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TW202131417A (zh
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劉芳妏
呂增富
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南亞科技股份有限公司
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Abstract

本發明提供一種具靜電放電防護之金屬晶粒的IC封裝結構，包括：一具 有電源連接線及接地連接線的印刷電路板；一功能性晶粒；一金屬晶粒，係附接於該功能性晶粒並且電氣絕緣於該功能性晶粒，其中該金屬晶粒包含一金屬層及位於該金屬層下方的一仿晶粒，該金屬層電氣耦接至該印刷電路板的一或多道該等電源連接線與該等接地連接線，俾利於提供封裝級靜電放電防護；以及一封膠，係包覆該金屬晶粒，該功能性晶粒及該印刷電路板支撐該金屬晶粒與該功能性晶粒的表面。

Description

具靜電放電防護之金屬晶粒的IC封裝結構
本發明關於一種積體電路(Integrated Circuit，IC)封裝結構及其製造方法，特別是關於一種具有封裝級靜電放電(ESD)防護的封裝結構及其製造方法。
深次微米CMOS尺寸持續縮小與高速度技術的發展使得靜電放電防護設計產生更大的挑戰。在面臨的諸多問題中，由於需要顧及傳輸速度，使得輸入/輸出接腳(I/O pins)的靜電放電電路設計更形複雜。以兩千伏特人體放電模式(Human-Body-Model，HBM)靜電應力而言，其最大電流約1.3安培，而峰值五百伏特的元件充電模式(Charged-Device-Model，CDM)靜電應力其最大電流卻高達10安培。此種元件充電模式靜電放電事件通常具有僅約0.2奈米(0.2ns)的快速上升時間。如此快速的暫時性靜電放電脈衝使得元件充電模式靜電放電事件成為造成先進製程與封裝失敗的主因。深次微米CMOS積體電路的閘極氧化層愈來愈薄化使得元件充電模式靜電放電防護更形重要。藉由增加靜電放電元件來提高輸入/輸出接腳的靜電放電性能亦會增加輸入/輸出接腳的負載，此種作法無法滿足高速度的要求。在靜電放電測試中，積體電路封裝元件經由一靜電放電測試儀來判定此積體電路封裝元件是否在指定的電氣應力規範內。若靜電放電失效發生，晶粒需重新設計的製程會相當昂貴。
美國專利第9,853,446B2號揭示一種嵌入IC封裝基底的第一靜電放電防護部件。該第一靜電放電防護部件係一種半導體元件。該第一靜電放電防護部件耦接至一晶粒的輸入/輸出墊。由於該第一靜電放電防護部件相較於該晶粒的內部靜電放電防護部件具有更大尺寸，該第一靜電放電防護部件提供更佳的靜電放電防護能力。該第一靜電放電防護部件可根據所期待的及/或預期的用途與該晶粒分開設計。然而，該第一靜電放電防護部件是一種半導體元件將會增加該晶粒的輸入/輸出墊的負載並且使成本增加許多。
因此，業界需要一種積體電路封裝，在不需要重新設計其內部晶粒並且成本符合經濟效益的前提下，可以滿足其內部元件需求、可靠度要求及電氣應力規範。
本發明提供一種具靜電放電防護之金屬晶粒的IC封裝結構及其製造方法。本發明的實施例包含一半導體封裝，其包含附接於一功能性晶粒(function die)的一金屬晶粒，該金屬晶粒與該功能性晶粒電氣絕緣。該金屬晶粒電氣耦接至安裝該功能性晶粒的一印刷電路板的一或多道電源連接線(power connections)及接地連接線(ground connections)進而提供相較於該功能性晶粒電力匯流排(power bus)提供的靜電放電途徑具有更低電阻的靜電放電途徑。該金屬晶粒係建構成對於本發明IC封裝結構提供封裝級靜電放電防護並且可將靜電直接傳導至該印刷電路板的電源連接線及接地連接線，以提高元件充電模式靜電放電性能。該金屬晶粒具有一金屬層及位於該金屬層下方的一仿晶粒(dummy die)，該金屬晶粒係可做為一獨立部件，代替整合於該功能性晶粒的作法，因此該金屬 晶粒不會增加該功能性晶粒的輸入/輸出接腳額外的負載。當該功能性晶粒的靜電放電性能不夠好時，該功能性晶粒無需重新被設計，取而代之的，將該金屬晶粒附加至該IC封裝結構即可以有效地提高靜電放電性能。
根據本發明的一實施例，本發明提供一種具靜電放電防護之金屬晶粒的IC封裝結構，其包括一印刷電路板，具有複數電源連接線及複數接地連接線；一功能性晶粒，具有一第一表面及相對於該第一表面的一第二表面以及在該第一表面上的複數導電性墊；其中該功能性晶粒的該第二表面接觸於該印刷電路板的一頂表面，一或多個該等導電性墊電氣耦接至該印刷電路板的一或多道該等電源連接線與該等接地連接線；一金屬晶粒，係位於該功能性晶粒的該第一表面並且電氣絕緣於該功能性晶粒，其中該金屬晶粒包含一金屬層及位於該金屬層下方的一仿晶粒，該仿晶粒接觸於該功能性晶粒的該第一表面，及該金屬層電氣耦接至該印刷電路板的一或多道該等電源連接線與該等接地連接線，俾利於提供封裝級靜電放電防護；以及一封膠，係包覆該金屬晶粒，該功能性晶粒及該印刷電路板的該頂表面。
在本發明的一實施方式中，該金屬晶粒係以黏膠貼附於該功能性晶粒。
在本發明的一實施方式中，該金屬層覆蓋該仿晶粒與其相接的一表面，並且佔據該功能性晶粒的該第一表面的該仿晶粒的面積小於或相等於該功能性晶粒的該第一表面的面積。
在本發明的一實施方式中，該功能性晶粒包含具有一IC結構的一半導體基底。
在本發明的一實施方式中，該仿晶粒的材質相同於該功能性晶粒的該半導體基底。
在本發明的一實施方式中，該金屬層係以濺鍍方式沈積於該仿晶粒。
在本發明的一實施方式中，該金屬層係一整面的金屬層(a comprehensive metal layer)或一圖案化金屬層。
在本發明的一實施方式中，該金屬層的材質係選自下列任一者：銅、鋁及鎢。
在本發明的一實施方式中，該金屬晶粒係經由打線電氣耦接至該印刷電路板的所述一或多道該等電源連接線及該等接地連接線。
在本發明的一實施方式中，該金屬晶粒係經由打線電氣耦接至該印刷電路板的所述一或多道該等電源連接線及該等接地連接線。
在本發明的一實施方式中，該功能性晶粒的一或多個該等導電性墊係經由打線電氣耦接至該印刷電路板的所述一或多道該等電源連接線與該等接地連接線。
根據本發明的一實施例，本發明提供一種具靜電放電防護之金屬晶粒的IC封裝結構的製造方法，其包括：提供一仿晶粒；形成一金屬層於該仿晶粒的一表面，以提供一金屬晶粒；安裝該金屬晶粒於一功能性晶粒上面，並且使該金屬層裸露出來，以令該金屬晶粒與該功能性晶粒電氣隔離；安裝該功能性晶粒於一印刷電路板的一頂表面，並且使該金屬層電氣連接至該印刷電路板的一 或多道電源連接線與接地連接線；及形成一封膠，以包覆該金屬晶粒、該功能性晶粒及該印刷電路板的該頂表面。
在本發明的一實施方式中，該金屬層係以濺鍍方式沈積於該仿晶粒。
10:具靜電放電防護之金屬晶粒的IC封裝結構
100:印刷電路板
101a、101b、101c、101d:電源連接線
102a、102b、102c、102d:接地連接線
103a、103b、103c、103d:打線
104a、104b、104c、104d:打線
110:功能性晶粒
110a:第一表面
110b:第二表面
111a、111b、111c、111d:第一導電性墊
112a、112b、112c、112d:第二導電性墊
120:金屬晶粒
122:金屬層
122a、122b、122c、122d:打線
124a、124b、124c、124d:打線
124:仿晶粒
130:封膠
140:黏膠
301、302、303、304:步驟
第一圖係根據本發明一具體實施例的一種具靜電放電防護之金屬晶粒的IC封裝結構的頂視示意圖。
第二圖係第一圖的具靜電放電防護之金屬晶粒的IC封裝結構沿X-X’線剖面示意圖。
第三圖係根據本發明一具體實施例的一種具靜電放電防護之金屬晶粒的IC封裝結構的製造方法流程圖。
本發明將藉由較佳實施例並參照附隨圖式予以說明。各圖式互相對應的部件以相同的符號代表。請注意已知的電路、結構及技術並未詳細的顯示出來，以免模糊本揭露內容的各方面。在此將揭露各種實施例。然而需瞭解的是所揭露的實施例僅是作為舉例說明，其仍可以其他各種形式呈現。除此之外，各種實施例中的例子係做為範例並非用以限制本發明。再者，圖式並不一定符合真實結構的大小及尺寸比例，一些特徵被放大以顯示出特定部件(並且圖式顯示的任何尺寸、材質及相同的細節用於例示說明並非用來限制)。因此，在此揭露的特定結構與功能性細節不應解釋成本發明的限制要件，而僅是用來教導熟悉相關技術領域的技術人員據以實施所揭露的實施例。
第一圖係根據本發明一具體實施例的一種具靜電放電防護之金屬晶粒的IC封裝結構10的頂視示意圖。第二圖是第一圖的具靜電放電防護之金屬晶粒的IC封裝結構10沿其X-X’線剖面示意圖。在此具體實施例中，該具靜電放電防護之金屬晶粒的IC封裝結構10包括一印刷電路板100、一功能性晶粒(function die)110、一金屬晶粒(metal die)120及一封膠130。複數電源連接線(power connections)101a、101b、101c、101d與複數接地連接線(ground connections)102a、102b、102c、102d係設置於該印刷電路板100的一頂表面100a並且延伸通過該印刷電路板100內部。該功能性晶粒110具有一第一表面110a及相對於該第一表面110a的一第二表面110b。該功能性晶粒110藉由其該第二表面110b接觸該印刷電路板100的該頂表面100a而安置在該印刷電路板100上。複數個第一導電性墊111a、111b、111c、111d與複數個第二導電性墊112a、112b、112c、112d係設置在該功能性晶粒110的第一表面110a上。該功能性晶粒110的第一導電性墊111a、111b、111c、111d例如經由各自的打線(wire bonding)103a、103b、103c、103d分別電氣耦接至該等電源連接線101a、101b、101c、101d，以提供來自該印刷電板100的電源至該功能性晶粒110的電氣途徑。該功能性晶粒110的第二導電性墊112a、112b、112c、112d例如經由各自的打線(wire bonding)104a、104b、104c、104d分別電氣耦接至該等接地連接線102a、102b、102c、102d，以提供來自該印刷電板100的接地訊號(ground reference signals)至該功能性晶粒110的電氣途徑。在一實施方式中，該功能性晶粒110包括一具有IC結構的半導體基底，例如是具IC結構的矽基底。
該金屬晶粒120安置在該功能性晶粒110的該第一表面110a上並且與該功能性晶粒110電氣絕緣。在一實施方式中，該金屬晶粒120係以黏膠140貼 附至該功能性晶粒110。該金屬晶粒120包含一金屬層122及位於該金屬層122下方的一仿晶粒(dummy die)124。該仿晶粒124係接觸於該功能性晶粒110的該第一表面110a。在一實施方式中，該仿晶粒124具有與該功能性晶粒110的該半導體基底相同的材質。例如，該仿晶粒124可以是一矽基材。該金屬層122經由打線122a、122b、122c、122d、124a、124b、124c、124d分別電氣耦接該印刷電路板100的該等電源連接線101a、101b、101c、101d及該等接地連接線102a、102b、102c、102d。該金屬晶粒120係建構以提供封裝級的靜電放電防護。該金屬晶粒120提供相較於該功能性晶粒110的電力匯流排(power bus)提供的靜電放電途徑具有更低電阻的靜電放電途徑。例如，該金屬晶粒120將帶負電的靜電電荷傳導至該印刷電路板100的該等電源連接線101a、101b、101c、101d，而該金屬晶粒120將帶正電的靜電電荷傳導至該印刷電路板100的該等接地連接線102a、102b、102c、102d。該金屬晶粒120提供封裝級靜電放電防護，以提高本發明IC封裝結構的元件充電模式(Charged-Device-Model，CDM)靜電放電性能。
在一實施方式中，該金屬層122覆蓋該仿晶粒124與其相接的表面，而該仿晶粒124佔據該功能性晶粒110的該第一表面110a，並且該仿晶粒124佔據的面積小於或等於該功能性晶粒110的該第一表面110a的面積。在一實施方式中，該金屬層122是一整面的金屬層(a comprehensive metal layer)或一圖案化的金屬層。在一實施方式中，該金屬層122係選自下列材質任一者：銅、鋁、鎢等。在一實施方式中，該金屬層122可以是覆蓋該仿晶粒124與其相接的表面及該仿晶粒124的側面，而該仿晶粒124以非導電性膠附接至該功能性晶粒110。該封膠130包覆 該金屬晶粒120、該功能性晶粒110及該印刷電路板100的該頂表面100a。該封膠130可以是樹脂材質(resin material)，例如環氧樹脂(epoxy)及其類似物。
第三圖係根據本發明一具體實施例的一種具靜電放電防護之金屬晶粒的IC封裝結構的製造方法流程圖。該製造方法可用以製造該具靜電放電防護之金屬晶粒的IC封裝結構10。為說明清楚起見，下文將參照第二圖來描述第三圖的步驟流程，但需注意的是，第三圖的製造方法並非僅用以製造該具靜電放電防護之金屬晶粒的IC封裝結構10。首先，在步驟301，提供仿晶粒124。該仿晶粒124可以是一半導體基材，例如是一矽基材。將該金屬層122形成於該仿晶粒124的一表面，以提供該金屬晶粒120。在一實施方式中，該金屬層122係以濺鍍方式沈積在該仿晶粒124上。該金屬層122的材質可以是銅、鋁、鎢等任一者。在步驟302，將該金屬晶粒120安裝於該功能性晶粒110上面，並且使該金屬層122裸露出來，以令該金屬晶粒120與該功能性晶粒110電氣隔離。在一實施方式中，該金屬晶粒120係以黏膠140貼附至該功能性晶粒110。在步驟303，將該功能性晶粒110安裝於該印刷電路板100的頂表面100a，並且將該金屬層122經由打線分別電氣耦接至該印刷電路板100的該等電源連接線101a、101b、101c、101d與該等接地連接線102a、102b、102c、102d。在步驟304，填充樹脂，以形成包覆該金屬晶粒120、該功能性晶粒110及該印刷電路板100的該頂表面110a的封膠130。
在一些實施方式中，上述步驟的順序可以改變或修改。
以上所述僅為本發明之具體實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。
10:具靜電放電防護之金屬晶粒的IC封裝結構
100:印刷電路板
101a、101b:電源連接線
103a、103b:打線
110:功能性晶粒
120:金屬晶粒
122:金屬層
122a、122b:打線
124:仿晶粒
130:封膠
140:黏膠

Claims (13)

  1. 一種具靜電放電防護之金屬晶粒的IC封裝結構，其包括：一印刷電路板，具有複數電源連接線及複數接地連接線；一功能性晶粒，具有一第一表面及相對於該第一表面的一第二表面以及在該第一表面上的複數導電性墊；其中該功能性晶粒的該第二表面接觸於該印刷電路板的一頂表面，一或多個該等導電性墊電氣耦接至該印刷電路板的一或多道該等電源連接線與該等接地連接線；一金屬晶粒，係位於該功能性晶粒的該第一表面並且電氣絕緣於該功能性晶粒，其中該金屬晶粒包含一金屬層及位於該金屬層下方的一仿晶粒，該仿晶粒接觸於該功能性晶粒的該第一表面，及該金屬層經由打線直接電氣耦接至該印刷電路板的一或多道該等電源連接線與該等接地連接線，俾利於提供封裝級靜電放電防護；以及一封膠，係包覆該金屬晶粒、該功能性晶粒及該印刷電路板的該頂表面。
  2. 如請求項1所述之具靜電放電防護之金屬晶粒的IC封裝結構，其中該金屬晶粒係以黏膠貼附於該功能性晶粒。
  3. 如請求項1所述之具靜電放電防護之金屬晶粒的IC封裝結構，其中該金屬層覆蓋該仿晶粒與其相接的一表面，並且佔據該功能性晶粒的該第一表面的該仿晶粒的面積小於或相等於該功能性晶粒的該第一表面的面積。
  4. 如請求項1所述之具靜電放電防護之金屬晶粒的IC封裝結構，其中該功能性晶粒包含具有一IC結構的一半導體基底。
  5. 如請求項4所述之具靜電放電防護之金屬晶粒的IC封裝結構，其中該仿晶粒的材質相同於該功能性晶粒的該半導體基底。
  6. 如請求項1所述之具靜電放電防護之金屬晶粒的IC封裝結構，其中該金屬層係以濺鍍方式沈積於該仿晶粒。
  7. 如請求項1所述之具靜電放電防護之金屬晶粒的IC封裝結構，其中該金屬層係一整面的金屬層或一圖案化金屬層。
  8. 如請求項1所述之具靜電放電防護之金屬晶粒的IC封裝結構，其中該金屬層的材質係選自下列任一者：銅、鋁及鎢。
  9. 如請求項1所述之具靜電放電防護之金屬晶粒的IC封裝結構，其中該功能性晶粒的一或多個該等導電性墊係經由打線電氣耦接至該印刷電路板的所述一或多道該等電源連接線與該等接地連接線。
  10. 一種具靜電放電防護之金屬晶粒的IC封裝結構的製造方法，其包括：提供一仿晶粒；形成一金屬層於該仿晶粒的一表面，以提供一金屬晶粒；安裝該金屬晶粒於一功能性晶粒上面，並且使該金屬層裸露出來，以令該金屬晶粒與該功能性晶粒電氣隔離；安裝該功能性晶粒於一印刷電路板的一頂表面，並且使該金屬層打線直接電氣連接至該印刷電路板的一或多道電源連接線與接地連接線；及形成一封膠，以包覆該金屬晶粒、該功能性晶粒及該印刷電路板的該頂表面。
  11. 如請求項10所述之具靜電放電防護之金屬晶粒的IC封裝結構的製造方法，其中該功能性晶粒包含具有一IC結構的一半導體基底。
  12. 如請求項11所述之具靜電放電防護之金屬晶粒的IC封裝結構的製造方法，其中該仿晶粒的材質相同於該功能性晶粒的該半導體基底。
  13. 如請求項10所述之具靜電放電防護之金屬晶粒的IC封裝結構的製造方法，其中該金屬層係以濺鍍方式沈積於該仿晶粒。
TW109107874A 2020-02-13 2020-03-10 具靜電放電防護之金屬晶粒的ic封裝結構 TWI749479B (zh)

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