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CN113257792A - 具静电放电防护的金属芯片的ic封装结构 - Google Patents

具静电放电防护的金属芯片的ic封装结构 Download PDF

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CN113257792A
CN113257792A CN202010234984.5A CN202010234984A CN113257792A CN 113257792 A CN113257792 A CN 113257792A CN 202010234984 A CN202010234984 A CN 202010234984A CN 113257792 A CN113257792 A CN 113257792A
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chip
metal
metal layer
functional
circuit board
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刘芳妏
吕增富
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明提供一种具静电放电防护的金属芯片的IC封装结构，包括：一具有电源连接线及接地连接线的印刷电路板；一功能性芯片；一金属芯片，附接于该功能性芯片并且电气绝缘于该功能性芯片，其中该金属芯片包含一金属层及位于该金属层下方的一仿芯片，该金属层电气耦接至该印刷电路板的一或多道所述电源连接线与所述接地连接线，用于提供封装级静电放电防护；以及一封胶，包覆该金属芯片，该功能性芯片及该印刷电路板支撑该金属芯片与该功能性芯片的表面。

Description

具静电放电防护的金属芯片的IC封装结构
技术领域
本发明关于一种集成电路(Integrated Circuit，IC)封装结构及其制造方法，特别是关于一种具有封装级静电放电(ESD)防护的封装结构及其制造方法。
背景技术
深次微米CMOS尺寸持续缩小与高速度技术的发展使得静电放电防护设计产生更大的挑战。在面临的诸多问题中，由于需要顾及传输速度，使得输入/输出接脚(I/O pins)的静电放电电路设计更形复杂。以两千伏特人体放电模式(Human-Body-Model，HBM)静电应力而言，其最大电流约1.3安培，而峰值五百伏特的元件充电模式(Charged-Device-Model，CDM)静电应力其最大电流却高达10安培。此种元件充电模式静电放电事件通常具有仅约0.2纳米(0.2ns)的快速上升时间。如此快速的暂时性静电放电脉冲使得元件充电模式静电放电事件成为造成先进工艺与封装失败的主因。深次微米CMOS集成电路的栅极氧化层愈来愈薄化使得元件充电模式静电放电防护更形重要。通过增加静电放电元件来提高输入/输出接脚的静电放电性能亦会增加输入/输出接脚的负载，此种作法无法满足高速度的要求。在静电放电测试中，集成电路封装元件经由一静电放电测试仪来判定此集成电路封装元件是否在指定的电气应力规范内。若静电放电失效发生，芯片需重新设计的工艺会相当昂贵。
美国专利第9,853,446B2号揭示一种嵌入IC封装衬底的第一静电放电防护部件。该第一静电放电防护部件是一种半导体元件。该第一静电放电防护部件耦接至一芯片的输入/输出垫。由于该第一静电放电防护部件相较于该芯片的内部静电放电防护部件具有更大尺寸，该第一静电放电防护部件提供更佳的静电放电防护能力。该第一静电放电防护部件可根据所期待的及/或预期的用途与该芯片分开设计。然而，该第一静电放电防护部件是一种半导体元件将会增加该芯片的输入/输出垫的负载并且使成本增加许多。
因此，业界需要一种集成电路封装，在不需要重新设计其内部芯片并且成本符合经济效益的前提下，可以满足其内部元件需求、可靠度要求及电气应力规范。
发明内容
本发明提供一种具静电放电防护的金属芯片的IC封装结构及其制造方法。本发明的实施例包含一半导体封装，其包含附接于一功能性芯片(function die)的一金属芯片，该金属芯片与该功能性芯片电气绝缘。该金属芯片电气耦接至安装该功能性芯片的一印刷电路板的一或多道电源连接线(power connections)及接地连接线(ground connections)进而提供相较于该功能性芯片电力汇流排(power bus)提供的静电放电途径具有更低电阻的静电放电途径。该金属芯片建构成对于本发明IC封装结构提供封装级静电放电防护并且可将静电直接传导至该印刷电路板的电源连接线及接地连接线，以提高元件充电模式静电放电性能。该金属芯片具有一金属层及位于该金属层下方的一仿芯片(dummy die)，该金属芯片可做为一独立部件，代替整合于该功能性芯片的作法，因此该金属芯片不会增加该功能性芯片的输入/输出接脚额外的负载。当该功能性芯片的静电放电性能不够好时，该功能性芯片无需重新被设计，取而代之的，将该金属芯片附加至该IC封装结构即可以有效地提高静电放电性能。
根据本发明的一实施例，本发明提供一种具静电放电防护的金属芯片的IC封装结构，其包括一印刷电路板，具有多个电源连接线及多个接地连接线；一功能性芯片，具有一第一表面及相对于该第一表面的一第二表面以及在该第一表面上的多个导电性垫；其中该功能性芯片的该第二表面接触于该印刷电路板的一顶表面，一或多个所述导电性垫电气耦接至该印刷电路板的一或多道所述电源连接线与所述接地连接线；一金属芯片，位于该功能性芯片的该第一表面并且电气绝缘于该功能性芯片，其中该金属芯片包含一金属层及位于该金属层下方的一仿芯片，该仿芯片接触于该功能性芯片的该第一表面，及该金属层电气耦接至该印刷电路板的一或多道所述电源连接线与所述接地连接线，用于提供封装级静电放电防护；以及一封胶，包覆该金属芯片，该功能性芯片及该印刷电路板的该顶表面。
在本发明的一实施方式中，该金属芯片以黏胶贴附于该功能性芯片。
在本发明的一实施方式中，该金属层覆盖该仿芯片与其相接的一表面，并且占据该功能性芯片的该第一表面的该仿芯片的面积小于或相等于该功能性芯片的该第一表面的面积。
在本发明的一实施方式中，该功能性芯片包含具有一IC结构的一半导体衬底。
在本发明的一实施方式中，该仿芯片的材质相同于该功能性芯片的该半导体衬底。
在本发明的一实施方式中，该金属层以溅射方式沉积于该仿芯片。
在本发明的一实施方式中，该金属层一整面的金属层(a comprehensive metallayer)或一图案化金属层。
在本发明的一实施方式中，该金属层的材质选自下列任一者：铜、铝及钨。
在本发明的一实施方式中，该金属芯片经由压焊电气耦接至该印刷电路板的所述一或多道所述电源连接线及所述接地连接线。
在本发明的一实施方式中，该金属芯片经由压焊电气耦接至该印刷电路板的所述一或多道所述电源连接线及所述接地连接线。
在本发明的一实施方式中，该功能性芯片的一或多个所述导电性垫经由压焊电气耦接至该印刷电路板的所述一或多道所述电源连接线与所述接地连接线。
根据本发明的一实施例，本发明提供一种具静电放电防护的金属芯片的IC封装结构的制造方法，其包括：提供一仿芯片；形成一金属层于该仿芯片的一表面，以提供一金属芯片；安装该金属芯片于一功能性芯片上面，并且使该金属层裸露出来，以令该金属芯片与该功能性芯片电气隔离；安装该功能性芯片于一印刷电路板的一顶表面，并且使该金属层电气连接至该印刷电路板的一或多道电源连接线与接地连接线；及形成一封胶，以包覆该金属芯片、该功能性芯片及该印刷电路板的该顶表面。
在本发明的一实施方式中，该金属层以溅射方式沉积于该仿芯片。
附图说明
图1是根据本发明一具体实施例的一种具静电放电防护的金属芯片的IC封装结构的俯视示意图。
图2是图1的具静电放电防护的金属芯片的IC封装结构沿X-X’线剖面示意图。
图3是根据本发明一具体实施例的一种具静电放电防护的金属芯片的IC封装结构的制造方法流程图。
附图标记：
10 具静电放电防护的金属芯片的IC封装结构
100 印刷电路板
101a、101b、101c、101d 电源连接线
102a、102b、102c、102d 接地连接线
103a、103b、103c、103d 压焊
104a、104b、104c、104d 压焊
110 功能性芯片
110a 第一表面
110b 第二表面
111a、111b、111c、111d 第一导电性垫
112a、112b、112c、112d 第二导电性垫
120 金属芯片
122 金属层
122a、122b、122c、122d 压焊
124a、124b、124c、124d 压焊
124 仿芯片
130 封胶
140 黏胶
301、302、303、304 步骤
具体实施方式
本发明将通过较佳实施例并参照附随图式予以说明。各图式互相对应的部件以相同的符号代表。请注意已知的电路、结构及技术并未详细的显示出来，以免模糊本揭露内容的各方面。在此将揭露各种实施例。然而需了解的是所揭露的实施例仅是作为举例说明，其仍可以其他各种形式呈现。除此之外，各种实施例中的例子是做为范例并非用以限制本发明。再者，图式并不一定符合真实结构的大小及尺寸比例，一些特征被放大以显示出特定部件(并且图式显示的任何尺寸、材质及相同的细节用于例示说明并非用来限制)。因此，在此揭露的特定结构与功能性细节不应解释成本发明的限制要件，而仅是用来教导熟悉相关技术领域的技术人员据以实施所揭露的实施例。
图1是根据本发明一具体实施例的一种具静电放电防护的金属芯片的IC封装结构10的俯视示意图。图2是图1的具静电放电防护的金属芯片的IC封装结构10沿其X-X’线剖面示意图。在此具体实施例中，该具静电放电防护的金属芯片的IC封装结构10包括一印刷电路板100、一功能性芯片(function die)110、一金属芯片(metal die)120及一封胶130。多个电源连接线(power connections)101a、101b、101c、101d与多个接地连接线(groundconnections)102a、102b、102c、102d设置于该印刷电路板100的一顶表面100a并且延伸通过该印刷电路板100内部。该功能性芯片110具有一第一表面110a及相对于该第一表面110a的一第二表面110b。该功能性芯片110通过其该第二表面110b接触该印刷电路板100的该顶表面100a而安置在该印刷电路板100上。多个第一导电性垫111a、111b、111c、111d与多个第二导电性垫112a、112b、112c、112d设置在该功能性芯片110的第一表面110a上。该功能性芯片110的第一导电性垫111a、111b、111c、111d例如经由各自的压焊(wire bonding)103a、103b、103c、103d分别电气耦接至所述电源连接线101a、101b、101c、101d，以提供来自该印刷电板100的电源至该功能性芯片110的电气途径。该功能性芯片110的第二导电性垫112a、112b、112c、112d例如经由各自的压焊(wire bonding)104a、104b、104c、104d分别电气耦接至所述接地连接线102a、102b、102c、102d，以提供来自该印刷电板100的接地信号(groundreference signals)至该功能性芯片110的电气途径。在一实施方式中，该功能性芯片110包括一具有IC结构的半导体衬底，例如是具IC结构的硅衬底。
该金属芯片120安置在该功能性芯片110的该第一表面110a上并且与该功能性芯片110电气绝缘。在一实施方式中，该金属芯片120以黏胶140贴附至该功能性芯片110。该金属芯片120包含一金属层122及位于该金属层122下方的一仿芯片(dummy die)124。该仿芯片124接触于该功能性芯片110的该第一表面110a。在一实施方式中，该仿芯片124具有与该功能性芯片110的该半导体衬底相同的材质。例如，该仿芯片124可以是一硅基材。该金属层122经由压焊122a、122b、122c、122d、124a、124b、124c、124d分别电气耦接该印刷电路板100的所述电源连接线101a、101b、101c、101d及所述接地连接线102a、102b、102c、102d。该金属芯片120建构以提供封装级的静电放电防护。该金属芯片120提供相较于该功能性芯片110的电力汇流排(power bus)提供的静电放电途径具有更低电阻的静电放电途径。例如，该金属芯片120将带负电的静电电荷传导至该印刷电路板100的所述电源连接线101a、101b、101c、101d，而该金属芯片120将带正电的静电电荷传导至该印刷电路板100的所述接地连接线102a、102b、102c、102d。该金属芯片120提供封装级静电放电防护，以提高本发明IC封装结构的元件充电模式(Charged-Device-Model，CDM)静电放电性能。
在一实施方式中，该金属层122覆盖该仿芯片124与其相接的表面，而该仿芯片124占据该功能性芯片110的该第一表面110a，并且该仿芯片124占据的面积小于或等于该功能性芯片110的该第一表面110a的面积。在一实施方式中，该金属层122是一整面的金属层(acomprehensive metal layer)或一图案化的金属层。在一实施方式中，该金属层122选自下列材质任一者：铜、铝、钨等。在一实施方式中，该金属层122可以是覆盖该仿芯片124与其相接的表面及该仿芯片124的侧面，而该仿芯片124以非导电性胶附接至该功能性芯片110。该封胶130包覆该金属芯片120、该功能性芯片110及该印刷电路板100的该顶表面100a。该封胶130可以是树脂材质(resin material)，例如环氧树脂(epoxy)及其类似物。
图3是根据本发明一具体实施例的一种具静电放电防护的金属芯片的IC封装结构的制造方法流程图。该制造方法可用以制造该具静电放电防护的金属芯片的IC封装结构10。为说明清楚起见，下文将参照图2来描述图3的步骤流程，但需注意的是，图3的制造方法并非仅用以制造该具静电放电防护的金属芯片的IC封装结构10。首先，在步骤301，提供仿芯片124。该仿芯片124可以是一半导体基材，例如是一硅基材。将该金属层122形成于该仿芯片124的一表面，以提供该金属芯片120。在一实施方式中，该金属层122以溅射方式沉积在该仿芯片124上。该金属层122的材质可以是铜、铝、钨等任一者。在步骤302，将该金属芯片120安装于该功能性芯片110上面，并且使该金属层122裸露出来，以令该金属芯片120与该功能性芯片110电气隔离。在一实施方式中，该金属芯片120以黏胶140贴附至该功能性芯片110。在步骤303，将该功能性芯片110安装于该印刷电路板100的顶表面100a，并且将该金属层122经由压焊分别电气耦接至该印刷电路板100的所述电源连接线101a、101b、101c、101d与所述接地连接线102a、102b、102c、102d。在步骤304，填充树脂，以形成包覆该金属芯片120、该功能性芯片110及该印刷电路板100的该顶表面110a的封胶130。
在一些实施方式中，上述步骤的顺序可以改变或修改。
以上所述仅为本发明的具体实施例而已，并非用以限定本发明的申请专利范围；凡其它未脱离本发明所揭示的精神下所完成的等效改变或修饰，均应包含在权利要求范围内。

Claims (14)

1.一种具静电放电防护的金属芯片的IC封装结构，其特征在于，包括：
一印刷电路板，具有多个电源连接线及多个接地连接线；
一功能性芯片，具有一第一表面及相对于该第一表面的一第二表面以及在该第一表面上的多个导电性垫；其中该功能性芯片的该第二表面接触于该印刷电路板的一顶表面，一或多个所述导电性垫电气耦接至该印刷电路板的一或多道所述电源连接线与所述接地连接线；
一金属芯片，位于该功能性芯片的该第一表面并且电气绝缘于该功能性芯片，其中该金属芯片包含一金属层及位于该金属层下方的一仿芯片，该仿芯片接触于该功能性芯片的该第一表面，及该金属层电气耦接至该印刷电路板的一或多道所述电源连接线与所述接地连接线，用于提供封装级静电放电防护；以及
一封胶，包覆该金属芯片，该功能性芯片及该印刷电路板的该顶表面。
2.如权利要求1所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该金属芯片以黏胶贴附于该功能性芯片。
3.如权利要求1所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该金属层覆盖该仿芯片与其相接的一表面，并且占据该功能性芯片的该第一表面的该仿芯片的面积小于或相等于该功能性芯片的该第一表面的面积。
4.如权利要求1所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该功能性芯片包含具有一IC结构的一半导体衬底。
5.如权利要求4所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该仿芯片的材质相同于该功能性芯片的该半导体衬底。
6.如权利要求1所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该金属层以溅射方式沉积于该仿芯片。
7.如权利要求1所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该金属层是一整面的金属层或一图案化金属层。
8.如权利要求1所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该金属层的材质选自下列任一者：铜、铝及钨。
9.如权利要求1所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该金属芯片经由压焊电气耦接至该印刷电路板的所述一或多道所述电源连接线及所述接地连接线。
10.如权利要求1所述的具静电放电防护的金属芯片的IC封装结构，其特征在于，该功能性芯片的一或多个所述导电性垫经由压焊电气耦接至该印刷电路板的所述一或多道所述电源连接线与所述接地连接线。
11.一种具静电放电防护的金属芯片的IC封装结构的制造方法，其特征在于，包括：
提供一仿芯片；
形成一金属层于该仿芯片的一表面，以提供一金属芯片；
安装该金属芯片于一功能性芯片上面，并且使该金属层裸露出来，以令该金属芯片与该功能性芯片电气隔离；
安装该功能性芯片于一印刷电路板的一顶表面，并且使该金属层电气连接至该印刷电路板的一或多道电源连接线与接地连接线；及
形成一封胶，以包覆该金属芯片、该功能性芯片及该印刷电路板的该顶表面。
12.如权利要求11所述的具静电放电防护的金属芯片的IC封装结构的制造方法，其特征在于，该功能性芯片包含具有一IC结构的一半导体衬底。
13.如权利要求12所述的具静电放电防护的金属芯片的IC封装结构的制造方法，其特征在于，该仿芯片的材质相同于该功能性芯片的该半导体衬底。
14.如权利要求11所述的具静电放电防护的金属芯片的IC封装结构的制造方法，其特征在于，该金属层以溅射方式沉积于该仿芯片。
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