TWI728742B - Antenna package, system of antenna package and method of manufacturing antenna package - Google Patents

Abstract

This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer; forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer; placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF; encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die. Each of the one or more antenna structures can be positioned over the one or more antenna regions.

Description

Antenna packaging, antenna packaging system and method for manufacturing antenna packaging

The present disclosure relates to an antenna packaging, an antenna packaging system, and a method for manufacturing an antenna packaging.

Microwave and millimeter (mm) waves occupy the frequency spectrum from 1 GHz to 30 GHz and from 30 GHz to 300 GHz, respectively. Printed circuit board (PCB) and complementary metal oxide semiconductor (CMOS) substrates can be used to integrate millimeter wave antennas with radio frequency (RF) integrated circuits (ICs). The complementary metal oxide semiconductor radio frequency chip may include a vertically embedded folded monopole antenna integrated into a low-temperature co-fired ceramic (LTCC) substrate carrier. However, the implementation of low-temperature co-fired ceramics may require an excessively large area, and the number of components (for example, inductors, capacitors, and baluns) included in the low-temperature co-fired ceramics may cause undesirable electromagnetic and substrate coupling interference performance.

According to some embodiments of the present disclosure, a method of manufacturing an antenna package includes the following operations. First, a dielectric layer is deposited on the carrier substrate. Next, a die attach film is formed on the dielectric layer. Then, one or more interposer via hole wall structures and one or more interposer via grating structures are formed on the dielectric layer. Next, the die is placed on the die attach film. Then, the encapsulated die, one or more interposer through-hole wall structures and one or more interposer through-hole grating structures are formed to form an encapsulated package, which includes one or more antenna regions. Then, an interconnection structure is formed on the encapsulation package, wherein the interconnection structure includes one or more metal wires coupled to the die and one or more interposer via wall structures.

According to some embodiments of the present disclosure, an antenna package includes a dielectric layer, a plurality of antenna area structures, a die, a molding compound, and an interconnection layer. Each of the antenna area structures includes one or more interposer via walls in contact with the dielectric layer, and one or more interposer via gratings in contact with the dielectric layer. The die is attached to the dielectric layer and adjacent to the antenna area structure. The molding compound is placed between the die and each of the antenna area structure. The interconnection layer is arranged on the die and the antenna area structure.

According to some embodiments of the present disclosure, an antenna packaging system includes a backside layer, one or more dies, multiple antenna area structures, a molding compound, and a metal layer. Each antenna area structure includes: via walls of the interposer for electrically coupling one or more dies, and for electrically coupling to one or more ground planes The surface of the interposer through-hole grating. The molding compound surrounds one or more dies and the antenna area structure. The metal layer is located on the molding compound.

100: package

105: RF transmission

120: First dorsal layer

130: second dorsal layer

142a: first through hole wall

142b: second through hole wall

142c: third through hole wall

142d: Fourth through hole wall

143: Conductor

144a: First interposer via grating

144b: The second interposer through-hole grating

144c: The third interposer through-hole grating

144d: The fourth interposer through-hole grating

150: die attach film

152: RF die

157a: first pad terminal

157b: second pad terminal

157c: third pad terminal

160: Seal layer

170: Interconnect structure

171: The first top focuses on the cloth layer

171a: First level conductor (RDL-1)

171b: The first level through hole (RDL-1 through hole)

171c: Dielectric layer

172: The second top focuses on the cloth layer

172a: Redistribution layer wiring

172b: second level through hole (RDL-2 through hole)

172c: Dielectric layer

173: The third top focuses on the cloth layer

173a: third level conductor (RDL-3)

173c: Dielectric layer

174,175,176: Metal under bump

180: Solder bump

200: method

205,210,215,220,225,230: Operation

235,240,245,250: Operation

300: carrier substrate

310: Light-to-heat conversion layer

320: protective layer

330: dorsal layer

600: photoresist layer

610, 620: Interposer through-hole opening

610a, 610b: via wall of interposer

620a, 620b: Interposer through-hole grating

630: Antenna area

700: Ti and copper seed layer stacking

800: copper layer

1000: grain

1010: die attach film

1100: molding compound

1300: polymer layer

1320: Metal wiring

1400: The second layer of cloth

1500: top polymer layer

1510: Metal layer contact under bump

1520, 1530, 1540: solder bumps

When read in conjunction with the accompanying drawings, the aspect of the present disclosure can be best understood from the following detailed description. It should be noted that according to the general practice in the industry, the various features are not drawn to scale. In fact, for clarity of description and discussion, the size of various features can be increased or decreased arbitrarily.

1A to 1B are diagrams of insulated substrate antennas incorporating electrical connectors according to some embodiments.

FIG. 2 is a flowchart of a method for forming an insulated substrate antenna according to some embodiments.

Figures 3 to 15 are diagrams of structures associated with a method for forming an insulated substrate antenna according to some embodiments.

FIG. 16 is a diagram illustrating the performance characteristics of an insulating substrate antenna according to some embodiments.

The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate the disclosure, and together with the description are further used to explain the principle of the disclosure and enable those skilled in the relevant art to make and use the disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes the features of components and arrangements Examples are given to simplify the various embodiments of this disclosure. Of course, these are only examples and are not intended to be limiting. In addition, the various embodiments of the present disclosure may repeat element symbols and/or letters in various examples. This repetition in itself does not indicate the relationship between the various embodiments and/or configurations discussed.

It should be noted that references to "one embodiment", "embodiment", "exemplary embodiment", "exemplary", etc. in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment It may not necessarily include this particular feature, structure, or characteristic. In addition, these phrases do not necessarily represent the same embodiment. In addition, when a specific feature, structure or characteristic is described in conjunction with an embodiment, whether it is explicitly described or not, it will be within the knowledge of those skilled in the art to realize the feature, structure or characteristic in combination with other embodiments.

It should be understood that the terms or terms in this text are for descriptive rather than restrictive purposes, so that the terms or terms in this specification will be interpreted by those familiar with (several) relevant skills in accordance with the teachings in this text.

In some embodiments, the terms "about" and "substantially" can indicate that the value of a given amount is within 5% of the target value (for example, ±1%, ±2%, ±3%, ±4%, and Within ±5%).

Overview

The components and methods described in this article are directed to an insulated substrate antenna. The insulated substrate antenna includes one or more transmitters and one or more ground planes arranged by through interposer vias (TIV). . One or more antennas are formed through vias in the interposer area. Compared with other CMOS RF chips, the embodiments described herein achieve better performance, smaller area, and higher integration.

The embodiment of the present disclosure relates to the design of an antenna package. The antenna package includes a radio frequency die and an insulating substrate with one or more antenna areas. The antenna package includes low-cost, high-efficiency vertical interposer through-hole walls (TIV-wall) and interposer through-hole gratings (TIV-gratings) to form an antenna area in an encapsulated package. The vertical interposer via antenna area enables, for example, to transmit and receive radio frequency signals laterally.

The antenna package (also referred to herein as "package") that includes the above-mentioned antenna area is advantageous and suitable for applications operating at high frequencies, such as 5G applications (e.g., greater than 5.8 GHz) and automotive radar (e.g., approximately 77GHz to about 120GHz). Such high-frequency applications can be aimed at, for example, radio frequency transceivers and portable and wearable Internet of things (IoT) and smart phone products.

In some embodiments, the antenna package includes a molding compound (MC) layer (also referred to herein as a dielectric layer or an insulating layer) above the radio frequency die, wherein the molding compound layer includes polyimide (PI) And has a low relative dielectric constant (k), for example, about 2.8 or between about 2.8 and about 3.0. The molding compound layer can reduce the coupling effect caused by radio frequency die components such as inductors, capacitors, and baluns.

In some embodiments, the insulator substrate may be formed of various materials, such as polyimide (PI), polybenzobisoxazole (PBO), molding compound, polymer, silicon dioxide (SiO ₂ ) , Silicon-on-glass (SOG), glass, ceramics, sapphire (Al ₂ O ₃ ) and other similar materials. In some embodiments, the insulator substrate may be manufactured to have a flexible thickness between about 200 μm and 2 mm. In addition, integrating the antenna package into a smaller three-dimensional integrated circuit (3D IC) package makes the components suitable for high-frequency 5G and automotive radar applications (for example, 5.8GHz, 28GHz, and 77GHz to 120GHz applications).

Insulating substrate with antenna area

Figures 1A to 1B illustrate the package 100 (also referred to herein as "insulated substrate antenna", "encapsulated package" or "antenna package"). The package 100 may include one or more IC dies (for example, radio frequency IC dies) and one or more antenna regions. An integrated fan-out (InFO) package can be integrated with the package 100, which includes one or more antenna regions coupled to one or more IC dies. For example, one or more antenna regions can be integrated with the IC die through an integrated fan-out redistribution structure. This integrated fan-out redistribution structure includes a metallization layer (for example, a redistribution layer or "RDL" structure). ), the metallization layer is coupled to the packaging molding compound through the IC die embedded therein. Some of the embodiments described below are in the context of InFO packaging. Based on the description herein, the embodiments of the present disclosure are applicable to other types of packages; these other types of packages are within the spirit and scope of multiple embodiments of the present disclosure.

FIG. 1A shows an exemplary top plan view of the package 100. The package 100 includes a die 152 that can be a radio frequency IC die. The die 152 is coupled to a first via wall 142a, a second via wall 142b, and a third via wall by a redistribution layer (RDL) wiring 172a 142c and the fourth through hole wall 142d. According to some embodiments, the first interposer via wall 142a to the fourth interposer via wall 142d may be coupled to the die 152 to act as a radio frequency transmitter.

The package 100 includes a first interposer via grating 144a to a fourth interposer via grating 144d. As shown here, in some embodiments, the first interposer via grating 144a to the fourth interposer via grating 144d may be arranged laterally (for example, in the x direction or in the y direction in Figure 1A), respectively Outside the first interposer via wall 142a to the fourth interposer via wall 142d. According to some embodiments, the first interposer via grating 144a to the fourth interposer via grating 144d may be coupled to one or more ground terminals to serve as a radio frequency ground plane. Each radio frequency ground plane acts as an electrical conductor to reflect and guide the radiation emitted from the first interposer via wall 142a to the fourth interposer via wall 142d. Therefore, the radio frequency transmission 105 can be guided by the radio frequency ground plane provided by the first interposer via grating 144a to the fourth interposer via grating 144d. Although radio frequency transmission is discussed herein, other types of signal transmission are within the spirit and scope of the embodiments of the present disclosure.

FIG. 1B illustrates the package 100 in a cross-sectional view. As shown in Figure 1B, the package 100 includes a first backside layer 120, a second backside layer 130, a first through hole wall 142a, a third through hole wall 142c, a first through hole grating 144a, and a third through hole. Grating 144c, die attach film 150, radio frequency die 152, first An RF die connector to the third RF die connector, the first pad to the third pad, the first pad terminal 157a to the third pad terminal 157c, and the sealing layer 160. The via walls 142a and 142c of the interposer respectively include a conductor 143. The interposer via gratings 144a and 144c each include a conductor 143. The interposer via walls 142b and 142d and the interposer via gratings 144b and 144c (not shown in the cross-sectional view of FIG. 1B) also include a conductor 143.

The interconnection structure 170 (also referred to as the RDL structure or the top-side RDL) is disposed on the encapsulation layer 160. The interconnect structure 170 includes a dielectric layer 171c and a first-level conductor 171a. The interconnect structure 170 further includes a dielectric layer 173c formed on the dielectric layer 171c and a third-level conductor 173a.

Referring to Figure 1B, a backside layer 120 is provided. The backside layer 120 is a dielectric layer, which may include a polymer. The backside layer 120 can serve as the final protective insulator of the package 100. This polymer can be, for example, polyimide (PI), polybenzoxazole (polybenzoxazole, PBO), benzocyclobutene (benzocyclobutene, BCB), ajinomoto buildup film (ajinomoto buildup film, ABF), resistance Solder resist film (SR) or other suitable materials. The backside layer 120 is a flat layer having a uniform thickness, wherein the thickness may be greater than about 2 μm (for example, between about 2 μm and about 40 μm). The top surface and bottom surface of the backside layer 120 are also flat.

Referring to FIG. 1B, a back layer 130 is provided on the back layer 120. The backside layer 130 is a dielectric layer, which may include a polymer. The backside layer 130 can serve as the final protective insulator of the package 100. This polymer can be for example Polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), Ajinomoto build-up film (ABF), solder mask (SR) or other suitable materials. The backside layer 130 is a flat layer having a uniform thickness, wherein the thickness may be greater than about 2 μm (for example, between about 2 μm and about 40 μm). The top and bottom surfaces of the backside layer 130 are also flat.

The interposer via walls 142a and 142d are disposed on the backside layer 130, thereby forming spaced apart first interposer via openings and second interposer via openings. The via walls 142a to 142d of the interposer may be electrically coupled to the die (such as the radio frequency die described below) for transmitting and receiving communication through the radio frequency signal. The interposer via walls 142a to 142d can be formed by first disposing a photoresist layer on the backside layer 130, and etching the photoresist layer to form spaced interposer via openings. A titanium and copper seed layer structure can be deposited on the photoresist layer, and a copper layer can be electroplated on the titanium and copper seed layer. The photoresist layer can then be removed, leaving the interposer via walls 142a to 142d. Although four walls are illustrated in Figure 1A (both are shown in cross section in Figure 1B), the number of via walls of the interposer is not limited to any specific number. The interposer via gratings 144a to 144d can be formed in a similar manner to the interposer via walls 142a to 142d. The interposer via grating is connected to one or more ground planes. Therefore, the antenna area structure is formed by each interval provided between the interposer via walls 142a to 142d and the interposer via gratings 144a and 144d.

Each antenna area can be filled with any one of a plurality of insulator materials compatible with the packaging process (for example, InFO packaging process) without being limited by the dielectric constant of the insulator. Some examples described below Among them, the insulator may have a low relative dielectric constant (ie, k; for example, about 2.8, or about 2.8 to about 3.0). In other embodiments, the insulator may have a relative dielectric constant specified by the manufacturing of the InFO package. Therefore, it is possible to use high-dielectric constant or low-dielectric constant materials to implement the antenna packages of the embodiments of the present disclosure robustly in the packaging (for example, InFO packaging) process.

The die 152 (for example, a radio frequency die such as a radio frequency IC die) is placed on the backside layer 130. A die-attach-film (DAF) 150 may be used to adhere the die 152 to the backside layer 130. In a non-limiting example, the die 152 may include a semiconductor substrate (for example, a silicon substrate) having a back surface in contact with the die attach film 150. A portion of the die 152 (such as the top portion) may include conductive pillars (for example, formed of copper, other metals, or alloys including one or more metals), and these conductive pillars electrically connect the die 152 to other conductive elements And interconnection structure.

The package 100 includes fan-out wiring between the input/output (I/O) pins on the die and the package I/O pins. These package I/O pins can form interconnections on the die Layer (e.g., redistribution layer (RDL)). The die is laterally surrounded by a medium (such as molding compound, encapsulant, epoxy, or the like). The interconnection layer may extend laterally beyond the periphery of the die. The interconnection layer includes a patternable dielectric material, and conductive patterns and conductive vias can be formed in the patternable dielectric material. Compared with other fan-out structures used in die packaging technology, packages such as InFO packages can provide significantly thinner packages, along with tighter redistribution wiring pitches (for example, 10 μm). InFO packages can provide advantages over other packages, such as flip chip ball grid array (FC-BGA) packages, because passive components can be formed over the periphery of the IC die (for example, over the molding compound) (For example, inductors and capacitors), used to reduce substrate loss and improve electrical performance. InFO packaging can lead to a compact die size, which can lead to improved thermal performance and lower operating temperature under the same power budget. In some embodiments, with the improved thermal performance, for the same temperature profile as the FC-BGA package, a faster circuit operating speed can be achieved.

As shown in FIG. 1B, the redistribution layer (RDL) structure 170 includes three interconnection (also referred to herein as top-side redistribution (RDL)) layers 171, 172, and 173. In other embodiments, a different number of re-distribution layers may be included. Each interconnection layer includes redistribution layers and vias that are features of metal conductors, and these metal conductor features provide electrical interconnections through and within the redistribution layer structure 170. In some embodiments, the redistribution layer wiring and vias may include copper. In the first interconnection layer 171, a first-level conductor (RDL-1) 171a and a first-level via (RDL-1 via) 171b provide interconnection. In the first top heavy layer interconnection layer 171, the dielectric layer 171c is disposed on the first level conductor 171a. In the second top-side redistribution layer 172, the redistribution layer wiring 172a and the second-level via (RDL-2 via) 172b provide interconnection. In the second top-side redistribution layer 172, the dielectric layer 172c is disposed on the redistribution layer wiring 172a. In the third top weighted layer 173, the third level conductor (RDL-3) 173a and under ball metal (UBM) 174, 175, and 176 provide interconnection. The solder bump 180 is formed on the convex The under-block metal layers 174 to 176 are above. In the third top weighted layer 173, the dielectric layer 173c is disposed on the third-level conductor 173a. The ground plane may be electrically connected to one or more solder bumps 180.

The die attach film (DAF) 150 may be used to adhere the die 152 to the backside layer 130. The die 152 may include a semiconductor substrate (for example, a silicon substrate), and the back surface of the semiconductor substrate is in contact with the die attach film 150. The die 152 includes pad terminals 157a to 157c (for example, copper pillars) formed as top portions of the die 152, and these top portions electrically connect the die 152 to other conductive elements and interconnect structures.

Manufacturing process of insulating substrate with antenna area

The method 200 will be described with reference to FIGS. 3 to 15. Figures 3 to 15 are for illustration purposes only and are not drawn to scale. In addition, Figures 3 to 15 may not reflect the actual structure, features, or actual geometric shapes of the layers. For the purpose of illustration and clarity, some structures, layers, or geometric shapes may have been deliberately added or omitted.

Referring to FIG. 2, the exemplary manufacturing method 200 starts with operation 205, where a carrier substrate 300 (such as a glass carrier substrate) having a light to heat convention layer (LTHC) 310 disposed thereon is provided, such as Shown in Figure 3. In some embodiments, the carrier substrate 300 provides mechanical support for structural elements that are attached or manufactured in subsequent operations of the method 200. The light-to-heat conversion layer 310 is an adhesive layer that can be cured by ultraviolet (UV) light to form a temporary bond between the polymer layer and the carrier substrate 300. Once the packaging is completed (e.g., InFO sealing Install), the temporary bond can be broken to release the polymer layer from the carrier substrate 300. By way of example and not limitation, irradiating the light-to-heat conversion layer 310 with a focused laser beam through the back side of the carrier substrate 300 can generate sufficient heat to decompose the light-to-heat conversion layer 310 and release the carrier substrate 300 from the polymer layer. In order to successfully release, the carrier substrate 300 is required to be transparent so that the light source (for example, laser) that can irradiate and decompose the light-to-heat conversion layer 310 can penetrate.

Referring to FIG. 2, the method 200 continues to operation 210, where a protective layer 320 is formed on the light-to-heat conversion layer 310, as shown in FIG. By way of example and not limitation, the protective layer 320 may include polyimide (PI), polybenzoxazole (PBO), or another suitable polymer material. In some embodiments, the protective layer 320 (also referred to herein as the "polymer layer 320") is a stress relief coating used as a protective layer or a "buffer coating" before forming the radio frequency region structure. In some embodiments, the protective layer 320 may be deposited and hardened by a spin coating process followed by a curing process.

Referring to FIG. 2, the method 200 continues with operation 215 and the process of forming the backside layer, as shown in FIG. 5. By way of example and not limitation, the backside layer 330 may include polyimide (PI), polybenzoxazole (PBO), or another suitable polymer material. In some embodiments, the backside layer 330 (herein also referred to as the "polymer layer 330") is a radiation suppression layer that allows the backside radiation to be restored to the radio frequency region structure and be constructed constructively to form The beam directed laterally. In some embodiments, the backside layer 330 may be deposited and hardened by a spin coating process followed by a curing process.

Referring to FIG. 2, the method 200 continues with operation 220 and the process of forming a through interposer (TIV) on the backside layer 330. In some embodiments, one or more of the interposer vias can be used to define the surface area of the corresponding interposer via wall, while one or more interposer vias can be used to define the surface area of the corresponding interposer via grating . By way of example and not limitation, photolithography and etching operations may be used to form the interposer vias in operation 220. For example, referring to FIG. 6, at operation 220, a photoresist layer 600 having a thickness of about 180 μm to about 250 μm may be spin-coated on the backside layer 330. The photoresist layer 600 can then be patterned to form via openings 610 and 620 of the interposer, as shown in FIG. 6.

In some embodiments, the interposer via opening 610 is used to define the surface area of the via wall, and the interposer via opening 620 is used to form an interposer via grating. The interposer via opening 610 may be designed to have a different size from the interposer via opening 620. For example, the via opening 610 of the interposer may have a width of 10 μm and a length of 50,000 μm to form a striped sheet structure, and the via opening of the interposer may have a width of 10 μm and a length of 10 μm to form a grating sheet structure. In some embodiments, the via opening 610 of the interposer may have a width of 20 μm and a length of 90,000 μm that are different from the corresponding width and length of the via opening 620 of the interposer, as shown in FIG. 6. In other embodiments, the via opening 610 of the interposer may have the same width and length of 100 μm as the via opening 620 of the interposer.

Referring to FIGS. 2 and 7, the method 200 continues to operation 225, where a titanium and copper seed layer stack 700 is deposited on the patterned photoresist layer 600 (for example, by a PVD process) to cover the openings 610 and The side wall and bottom surface of 620. In some embodiments, a seed layer stack 700 is deposited on the photoresist layer 600, as shown in FIG. In some embodiments, the titanium layer may be about 1000 Å thick, and the copper seed layer may be about 5000 Å thick.

Referring to FIGS. 2 and 8, the method 200 continues to operation 230, where a copper layer 800 is electroplated on the titanium and copper seed layer stack 700 to fill the openings 610 and 620 and form corresponding interposer via walls 610a and 610b and Interposer via gratings 620a and 620b. In some embodiments, the copper layer 800 thus deposited can be grown on the photoresist layer 600 on the seed layer stack 700. The copper layer 800 can be subsequently planarized and polished by a chemical mechanical planarization (CMP) process to remove the portion of the copper layer 800 above the top surface of the photoresist layer 600. In some embodiments and during the copper CMP process, the seed layer stack 700 is also removed from the top surface of the photoresist layer 600, as shown in FIG. 8. In this stage of the manufacturing process, the thickness of the photoresist layer 600 (which in some embodiments may range from about 100 μm to about 1000 μm) defines the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b The height.

Referring to the method 200 in Figure 2, at operation 235, after forming the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b, the photoresist layer 600 can be removed by a wet etching process, such as Shown in Figure 9. According to some embodiments, it is different from the one shown in Figure 6 above with reference to Compared with the interposer via gratings 620a and 620b described in the ports 610 and 620, the interposer via walls 610a and 610b have different widths. For example, the interposer via walls 610a and 610b may have a width of about 10 μm to about 1000 μm, and the interposer via gratings 620a and 620b may have a width of about 10 μm to 100 μm. The interposer via walls 610a and 610b and the interposer via gratings 620a and 620b provide an antenna area structure between the backside layer 330 and the InFO package in the antenna package.

Referring to FIG. 2, the method 200 continues with the operation 240 and the process of placing (for example, attaching) the die 1000 on the protective layer 320, as shown in FIG. 10. In some embodiments, the die 1000 may have, for example, a radio frequency communication function, such as a radio frequency integrated circuit (RF IC) die. The die 1000 may have other or additional functions. The die 1000 may have been pre-fabricated using a wafer manufacturing process, and the die 1000 may include a transistor and multiple interconnection layers for performing its functions (for example, radio frequency communication). In some embodiments, a portion of the die 1000 (such as the top portion) may include conductive pillars (for example, formed of copper, other metals, or alloys including one or more metals), and these conductive pillars connect the die 1000 It is electrically connected to other conductive elements and interconnection structures.

In some embodiments, the die attach film (DAF) 1010 acts as a glue layer and is inserted between the die 1000 and the backside layer 330. By way of example and not limitation, the die attach film 1010 may have a thickness between about 10 μm and about 20 μm. In some embodiments, the die attach film 1010 is a dielectric material. By way of example and not limitation, the height of the die 1000 can communicate with the interposer. The heights of the hole walls 610a and 610b and the interposer via gratings 620a and 620b are equal. If the die 1000 is higher than the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b, it can be recessed to the same height as the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b . According to some embodiments, a plurality of dies may be attached to the polymer layer 330 during operation 240. In order to avoid the formation of parasitic capacitance between the via hole of the interposer and the die 1000, a minimum spacing S of about 20 μm to 30 μm may be appropriate. If a material with a sufficiently low relative dielectric constant (for example, lower than about 2.8) can be used to isolate the interposer via and the die 1000, the spacing S can be adjusted to be less than about 20 μm.

Referring to FIGS. 2 and 11, the method 200 continues operation 245 and disposes a molding compound (MC) 1100 on the polymer layer 320 to surround the die 1000, the interposer via walls 610a and 610b, and the interposer via grating 620a and 620b manufacturing process. By way of example and not limitation, the molding compound 1100 may be spin-coated on the polymer layer 320. According to some embodiments, the molding compound 1100 is an epoxy-based material, which is solid at room temperature and liquid when heated at a temperature higher than, for example, 250°C. In some embodiments, the molding compound 1100 is melted before the molding compound 1100 is spin-coated on the backside layer 330. By way of example and not limitation, the spin-coated molding compound may have a thickness between about 230 μm and about 300 μm. This means that the molding compound 1100 thus coated may have a covering layer of about 50 μm. For example, it can be used in die 1000, via walls 610a and 610b of the interposer. And the top surface of the interposer via grating 620a and 620b extends about 50 μm.

According to some embodiments, the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b can be embedded in a molding compound 1100 with a low relative permittivity (for example, about 2.8) to form an antenna area. This example is not restrictive, and the antenna area 630 may be provided and filled with any one of a plurality of insulator materials compatible with the packaging process (for example, InFO packaging process) without being limited by the dielectric constant of the insulator. According to some embodiments of the present disclosure, the antenna area structure (for example, the antenna area 630, which includes the interposer via walls 610a and 610b, the interposer via gratings 620a and 620b, and the molding compound 1100) can improve the performance of the InFO package. The reflection coefficient (S11 parameter) of the insulated substrate antenna structure, especially in high-frequency applications with antenna efficiency of 5.8GHz and higher. The antenna area structure also helps to reduce improper coupling of the antenna to nearby circuits, and prevents undesired noise from the circuit from reaching the antenna. In some embodiments, the arrangement of the interposer via gratings 620a and 620b extends laterally beyond the interposer via walls 610a and 610b, which achieves improved grounding and return loss.

After the molding compound 1100 is coated on the carrier substrate 300, the molding compound 1100 may be allowed to cool and harden. Once the molding compound 1100 is hardened, the molding compound 1100 can be partially ground to remove about 98% of the 50 μm cover layer, as shown in Figure 12. The grinding process makes the top surface of the molding compound 1100 rough. According to some embodiments, CMP can be used subsequently Process to planarize, polish and remove the remaining part of the molding compound 1100 (for example, about 1 μm, which is about 2% of the remaining part of the 50 μm cover layer), until the die 1000, the interposer via walls 610a and 610b, and the interposer The top surfaces of the through-layer via gratings 620a and 620b are exposed. In some embodiments, the molding compound 1100 provides structural support and electrical isolation for the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b. Because the molding compound 1100 melts at a temperature higher than about 250°C, the thermal budget of any subsequent manufacturing operations should be limited to about 250°C. If a molding compound with a higher temperature tolerance is used, the thermal budget of subsequent manufacturing operations can be increased without other thermal budget constraints.

Referring to FIG. 2, the method 200 continues to operation 250 to form one or more redistribution layers to provide electrical connections for the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b. During operation 250, electrical connections with other components and via vias in the interposer may be formed. For example, during operation 250, the electrical connection between the die 1000 and the via walls 610a and 610b of the interposer can also be completed.

By way of example and not limitation, each additional redistribution layer may include a new polymer layer. For example, referring to FIG. 13, a polymer layer 1300 (which is similar to the polymer layer 320) is disposed on the molding compound 1100. In some embodiments, the polymer layer 1300 is a low-k dielectric material having a dielectric constant of about 2.8 and a thickness of about 4.5 μm. The polymer layer 1300 can then be patterned to form openings therein, and the re-distribution layer metal wiring will be formed in these openings. For example, in Figure 13, there can be A first redistribution layer is formed on the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b. The alignment of the first redistribution layer and the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b can be achieved by one or more photolithography and etching operations. By way of example and not limitation, the photoresist layer may be spin-coated on the polymer layer 1300. The photoresist layer can be patterned so that openings aligned with the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b can be formed in the photoresist layer. The subsequent etching process can remove the portion of the polymer layer 1300 that is not masked by the photoresist to form substantially aligned with the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b Open up. Once the openings in the polymer layer 1300 have been formed, the photoresist layer can be removed, and the blanket metal stack can be deposited and patterned to form the metal wiring 1320 of the first redistribution layer.

The metal wiring 1320 may include a metal stack of electroplated copper top layer, copper seed crystal middle layer, and titanium bottom layer. By way of example and not limitation, the titanium bottom layer and the copper seed crystal intermediate layer can be deposited to a thickness of about 100 nm and 500 nm, respectively, by a PVD process. The electroplated copper top layer may have a thickness of about 7 μm or more. In some embodiments, the metal stack may partially fill the openings in the polymer layer 1300, as shown in FIG. 15.

The above operations can be continuously repeated to form the second re-distribution layer 1400, as shown in FIG. 14. The number of redistribution levels provided herein is illustrative and should not be considered as limiting. Therefore, fewer or additional levels of redistribution can be formed depending on the InFO package design. With the help of By way of example and not limitation, four or more redistribution layers may be formed on the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b. With reference to Figure 15, and once all the redistribution layers have been formed, place the top polymer layer 1500 on the topmost redistribution layer (for example, the second redistribution layer 1400 in Figure 14), and then pattern it . According to some embodiments, after metal deposition, an under bump metallurgy (UBM) contact 1510 is formed by a patterning operation. The under-bump metal layer contact 1510 forms the interface between the redistribution layer 1400 and the solder bumps 1520, 1530, and 1540. In some embodiments, the under-bump metal layer contact 1510 may include a metal stack of an electroplated copper top layer, a copper seed intermediate layer, and a titanium bottom layer. Alternatively, the under-bump metal layer contact 1510 may include alloys, such as titanium (Ti) and copper (Cu), titanium (Ti)-tungsten (W) and copper (Cu), aluminum (Al)-nickel (Ni) -Vanadium (V) and copper (Cu), or chromium (Cr) and copper (Cu). The solder bumps 1520, 1530, and 1540 may be part of a ball grid array (BGA), and may be metal alloys that may contain tin (Sn), silver (Ag), and copper (Cu), or may contain lead (Pb) and Made of tin (Sn) metal alloy.

In some embodiments, the carrier substrate 300 can be detached (released) from the polymer layer 320. For example, irradiating the light-to-heat conversion layer 310 with a focused laser beam through the back side of the glass carrier substrate 300 can generate enough heat to decompose the light-to-heat conversion layer 310 and release the carrier substrate 300 from the polymer layer 320. In some embodiments, the polymer layer 320 serves as the backside protective layer of the antenna package.

In some embodiments, the solder bumps 1520 and 1540 (which can be electrically connected to the interposer via gratings 620a and 620b) can be connected to an external ground connection. The solder bump 1530 (which is electrically connected to the die 1000) can be electrically coupled to an external IC, which provides input and power signals to the die 1000 through the under-bump metal layer contact 1510 and the metal wiring 1320. In addition, the number of solder bumps shown in Figure 15 is not limitative. Therefore, the additional solder bumps are within the spirit and scope of the present disclosure.

According to some embodiments, solder bumps (such as solder bumps 1520, 1530, and 1540) may electrically connect the InFO package to one or more external power sources or to ground connections. The external power source is, for example, a power source that is not integrated into the InFO package. For example, an InFO package with die 1000 can be attached to a die or printed circuit board (PCB) with solder bump receivers via solder bumps 1520, 1530, and 1540. Die 1000 can be used for internal or external components of the InFO package.

As described above, the antenna area structure according to some embodiments of the present disclosure can improve the reflection coefficient (S11 parameter) of the integrated block antenna in the InFO package, especially when the antenna efficiency is high at 5.8 GHz and higher frequencies. Frequency application. FIG. 16 is a graph of the S11 parameter (reflection coefficient) of the insulated substrate antenna structure with the antenna area 630 filled with the insulator shown in FIG. 15. The S11 value is generated by the simulation of an embodiment of the insulated substrate antenna structure shown in FIG. 15. As shown in the graph, the antenna effectively radiates frequencies of 5.8 GHz and above, including frequencies of 120 GHz and above. Antenna with antenna area according to an embodiment of the present disclosure The package has radio frequency characteristics suitable for meeting the specifications of the fourth generation (for example, about 5.8 GHz) and the fifth generation (for example, about 38 GHz) of high frequency radio frequency transceivers in mobile communication applications. As described herein, the antenna package, system and forming method thereof as described herein include a die and an antenna area structure. The antenna area structure may include one or more interposer via (TIV) wall structures and one or more interposer via grating structures on the backside layer. Encapsulate the die and antenna area structure by molding compound. This antenna package obtains the benefits of propagation signal transmission (including high-frequency transverse radio frequency transmission), as well as improved grounding and return loss.

A method of manufacturing an antenna package includes depositing a dielectric layer on a carrier substrate; forming a die attach film on the dielectric layer; forming one or more interposer via wall structures and one or more on the dielectric layer Interposer through-hole grating structure; placing die on die attach film; sealing die, one or more interposer through-hole wall structures, and one or more interposer through-hole grating structure to form an encapsulated package , The encapsulated package includes one or more antenna regions; and an interconnect structure is formed on the encapsulated package, wherein the interconnect structure includes one of the via wall structures coupled to the die and one or more interposers or Multiple metal wiring.

In some embodiments, the above-mentioned method of manufacturing an antenna package further includes forming a second interconnect structure on the interconnect structure. In some embodiments, the above method of manufacturing an antenna package further includes: forming a third interconnection structure on the second interconnection structure; attaching a plurality of solder bumps to the third interconnection structure; attaching a printed circuit board Connect to the solder bumps; and remove the carrier substrate. In some embodiments, the step of forming a dielectric layer includes forming a polybenzodioxazole (PBO) protective layer. In some embodiments, the step of forming one or more interposer via hole wall structures and one or more interposer via grating structures on the dielectric layer includes: forming a photoresist layer on the dielectric layer; etching light The resist layer forms spaced first interposer through hole openings and second interposer through hole openings; depositing a titanium and copper seed layer structure on the photoresist layer; electroplating a copper layer on the titanium and copper seed layer; and Remove the photoresist layer. In some embodiments, the dielectric layer includes polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), Ajinomoto build-up film (ABF), solder mask ( SR) or a combination thereof. In some embodiments, forming the interconnect structure includes positioning an interconnect layer over at least one of the one or more antenna regions.

An antenna package includes a dielectric layer and an antenna area structure, wherein each of the antenna area structures includes: one or more via walls in contact with the dielectric layer; one or more via walls in contact with the dielectric layer Layer via grating; die attached to the dielectric layer and adjacent to the antenna area structure; molding compound placed between the die and each of the antenna area structure; and placed on the die and antenna area structure Interconnect layer.

In some embodiments, the antenna package further includes a second interconnection layer and a plurality of solder bumps, wherein the second interconnection layer is used to electrically connect the interconnection layer and the solder bumps are used to electrically connect the second interconnection layer . In some embodiments, each of the one or more via walls of the interposer has a depth of about 120 μm to about 150 μm. In some embodiments, each of these antenna area structures has a thickness of about 200 μm to about 2 mm. In some embodiments, the molding compound has a relative dielectric constant of about 2.8 to about 3.0. In some In an embodiment, the dielectric layer includes polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), Ajinomoto build-up film (ABF), solder mask (SR) or Its combination. In some embodiments, these antenna area structures include a first antenna area structure having a first interposer via wall and a first interposer via grating, and a second interposer via wall and a second interposer The second antenna area structure of the through-hole grating.

An antenna packaging system includes a backside layer, one or more dies, and an antenna area structure, wherein each antenna area structure includes: an interlayer via wall for electrically coupling one or more dies; and an electrical coupling Connected to one or more ground plane via via gratings; molding compound surrounding one or more dies and antenna area structure; and a metal layer on the molding compound.

to sum up

In some embodiments, the molding compound has a relative dielectric constant of about 2.8 to about 3.0. In some embodiments, the via wall of the interposer has a depth of about 120 μm to about 150 μm. In some embodiments, the antenna packaging system further includes a protective layer, and the protective layer includes polybenzoxazole (PBO). In some embodiments, the backside layer includes polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), Ajinomoto buildup film (ABF), solder mask ( SR) or a combination thereof.

The foregoing disclosure summarizes the features of several embodiments, so that those skilled in the art can better understand the various embodiments of the present disclosure. Those who are familiar with the art should understand that they can easily use the various embodiments of the present disclosure as designs or modifications to achieve the same as the embodiments introduced herein. Purpose and/or the basis of other processes and structures to achieve the same advantages. Those who are familiar with the art should also realize that these equivalent structures do not depart from the spirit and scope of the various embodiments of the present disclosure, and they can be used herein without departing from the spirit and scope of the various embodiments of the present disclosure. Make various changes, substitutions and alterations.

100: package

105: RF transmission

142a: first through hole wall

142b: second through hole wall

142c: third through hole wall

142d: Fourth through hole wall

143: Conductor

144a: First interposer via grating

144b: The second interposer through-hole grating

144c: The third interposer through-hole grating

144d: The fourth interposer through-hole grating

152: RF die

172a: Redistribution layer wiring

Claims (10)

A method of manufacturing an antenna package includes: depositing a dielectric layer on a carrier substrate; forming a die attach film on the dielectric layer; forming one or more interposer through-hole wall structures and one or more An interposer via grating structure on the dielectric layer; placing a die on the die attach film; encapsulating the die, the one or more interposer via wall structures and the one or more The interposer through-hole grating structure is used to form an encapsulated package that includes one or more antenna regions; and an interconnection structure is formed on the encapsulated package, wherein the interconnection structure includes coupling to One or more metal wires of the die and the one or more via wall structures of the interposer. The method according to claim 1, further comprising forming a second interconnect structure on the interconnect structure. The method according to claim 2, further comprising: forming a third interconnection structure on the second interconnection structure; attaching a plurality of solder bumps to the third interconnection structure; attaching a printed circuit board Connecting to the solder bumps; and removing the carrier substrate. The method according to claim 1, wherein the step of forming the one or more interposer via hole wall structures and the one or more interposer via grating structures on the dielectric layer includes: forming a photoresist layer On the dielectric layer; Etching the photoresist layer to form a first interposer via opening and a second interposer via opening; depositing a titanium and copper seed layer structure on the photoresist layer; electroplating a copper layer on the photoresist layer On the titanium and copper seed layer; and removing the photoresist layer. The method of claim 1, wherein forming the interconnect structure includes positioning the interconnect layer over at least one of the one or more antenna regions. An antenna package includes: a dielectric layer; a plurality of antenna area structures, wherein each of the antenna area structures includes: one or more interposer through-hole walls, the one or more interposer through-hole walls Contacting the dielectric layer; and one or more interposer via gratings, the one or more interposer via gratings contacting the dielectric layer; a die attached to the dielectric layer and adjacent The antenna area structures; a molding compound disposed between the die and each of the antenna area structures; and an interconnection layer disposed on the die and the antennas Regional structure. The antenna package according to claim 6, wherein the interconnection layer It includes a plurality of contacts for electrically connecting the die. The antenna package according to claim 6, further comprising: a second interconnection layer for electrically connecting the interconnection layer; and a plurality of solder bumps, the solder bumps for electrical connection Connect the second interconnection layer. The antenna package according to claim 6, wherein the antenna area structures include a first antenna area structure having a first interposer via wall and a first interposer via grating, and a second interposer Layer through hole walls and a second interposer through hole grating and a second antenna area structure. An antenna packaging system includes: a backside layer; one or more dies; a plurality of antenna area structures, wherein each of the antenna area structures includes: an interposer through-hole wall, the interposer through-hole wall is used for electrical coupling Connected to the one or more dies; and an interposer via grating for electrically coupling to one or more ground planes; a molding compound that surrounds the one or more dies And the antenna area structures; and a metal layer on the molding compound.

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