TW201901864A - Composite antenna substrate and semiconductor package module - Google Patents

Abstract

A composite antenna substrate and semiconductor package module includes: a fan-out semiconductor package including a semiconductor chip, an encapsulant encapsulating at least portions of the semiconductor chip, and a connection member including a redistribution layer electrically connected to connection pads; and an antenna substrate including an antenna member including antenna patterns, ground patterns, and feed lines, and a wiring member disposed below the antenna member and including wiring layers including feeding patterns electrically connected to the feed lines.

Description

Composite antenna substrate and semiconductor package module

The disclosure relates to a composite antenna substrate and a semiconductor package module. [ Cross-Reference to Related Applications ]

This application claims Korean Patent Application No. 10-2017-0062550, which was filed in the Korea Intellectual Property Office on May 19, 2017, and Korean Patent Application No. 10, which was filed in the Korea Intellectual Property Office on September 15, 2017. The benefit of priority to the benefit of the present application is hereby incorporated by reference in its entirety.

Applications using millimeter waves of 10 megahertz or more are widely used in motion sensor products that detect motion to increase user interface (I/F) convenience, and to reserve space. Inside the intruder for the identification of safe motion monitoring sensor products, 24 megahertz and 77 megahertz radar systems for near and far field detection of automobiles, and fifth generation (fifth Generation, 5G) mobile communication or 60 megahertz communication. In the case of using the above millimeter wave product, when the signal is transmitted from the radio frequency integrated circuit (RFIC) to the antenna or from the antenna to the radio frequency integrated circuit, the signal should be transmitted such that the signal is lost. minimize. Conventionally, in order to achieve this, the RF integrated circuit and the antenna are connected to each other by a coaxial cable to minimize signal attenuation, which is inefficient in terms of space and cost.

In the recent 60 megahertz communication system, materials such as low temperature co-fired ceramic (LTCC) were used to design a 60 megahertz antenna and then 60 megahertz. The antenna is attached to the RF integrated circuit to significantly reduce the distance between the components. In addition, in some radar systems for automobiles, the RF integrated circuit is mounted on a printed circuit board (PCB). The antenna pattern is formed on the main printed circuit board and connected to the main printed circuit board or mounted as a separate antenna module on the main printed circuit board. However, in this manner, it is difficult to sufficiently prevent line-to-line loss between the components.

Recently, with the development of packaging technology, a method of forming an antenna in a radio frequency integrated circuit package has been developed, and in some cases has been formed on a redistribution layer (RDL) of a radio frequency integrated circuit package. The way the antenna pattern is. However, in this way, there are several design constraints in ensuring the radiation performance of the antenna, or there is a possibility that a performance error will occur. Therefore, there is a need for a stable RF integrated circuit and antenna integrated package design technique that can have a certain degree of design flexibility and significantly reduce design errors.

The aspect of the disclosure can provide a composite antenna substrate and a semiconductor package module, wherein the signal path between the antenna and the semiconductor chip can be designed to have the shortest distance, ensure omnidirectional coverage characteristics, and the antenna Receive sensitivity can be improved.

According to the aspect of the present disclosure, a semiconductor package including a semiconductor wafer and an antenna substrate including an antenna can be compositely modularized.

According to the disclosed aspect, a composite antenna substrate and a semiconductor package module may include: a fan-out type semiconductor package including a semiconductor wafer, an encapsulant, and a connecting member, the semiconductor wafer having an active surface and opposite to the active surface a non-active surface, the active surface is provided with a connection pad, the encapsulation envelops at least part of the semiconductor wafer, the connection member is disposed on the semiconductor wafer and includes an electrical connection to the connection a repeating layer of the pad; and an antenna substrate including an antenna member and a wiring member disposed under the antenna member, the antenna member including an insulating layer, a first pattern layer, a second pattern layer, and a through hole, the first The pattern layer is disposed on the upper surface of the insulating layer and includes an antenna pattern, the second pattern layer is disposed on a lower surface of the insulating pattern and includes a ground pattern, the through hole penetrating the insulating layer and including electricity Connected to the feed line of the antenna pattern, and the wiring member includes a wiring layer including a feed pattern electrically connected to the feed line, The fan-out semiconductor package substrate with the antenna coupled to each other, such that the connecting member to the wiring member face each other.

According to another aspect of the disclosure, a composite antenna substrate and a semiconductor package module may include: a fan-out type semiconductor package including a core member, a semiconductor wafer, an encapsulant, and a connecting member, the core member having a through hole, The semiconductor wafer is disposed in the through hole and has an active surface and an inactive surface opposite to the active surface, the active surface is provided with a connection pad, and the envelope encapsulates at least a portion of the semiconductor wafer The connecting member is disposed on the semiconductor wafer, the core member and the connecting member respectively comprise a core wiring layer and a redistribution layer electrically connected to the connection pad; and an antenna substrate including an antenna member and a wiring a member, wherein a first pattern layer including an antenna pattern is disposed on the insulating layer, a second pattern layer including a ground pattern is disposed under the insulating layer, and a through hole is formed in the insulating layer, the through hole penetrating The insulating layer further includes a feed line electrically connected to the antenna pattern, and the wiring member is disposed under the antenna member and includes wiring The wiring layer includes a feed pattern electrically connected to the feed line, wherein the antenna substrate is stacked on the fan-out type semiconductor package, and the antenna substrate and the fan-out type semiconductor package are electrically The sexual connection structures are connected to each other.

Hereinafter, various exemplary embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the shapes, dimensions, and the like of the various components may be exaggerated or reduced for clarity.

The expression "coupled" conceptually includes a situation in which two components are integrated into each other and a form in which two components are stacked together using an intermediate.

The term "exemplary embodiment" as used herein is not intended to refer to the same exemplary embodiments, but rather to the particular features or characteristics that are different from the specific features or characteristics of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be capable of being implemented in an overall or partial combination with each other. For example, an element that is set forth in a particular exemplary embodiment is not illustrated in another exemplary embodiment, unless the contrary or contradictive description is provided in another exemplary embodiment. It can be understood as a description related to another exemplary embodiment.

In the description, the meaning of the "connection" of a component to another component includes an indirect connection via a third component and a direct connection between the two components. In addition, "electrical connection" conceptually includes physical connections and physical disconnections. For example, an "electrical connection" includes a signal connection, although the connection is physically disconnected. It will be understood that when the elements are referred to as "first" and "second", the elements are not so limited. The use of such phrases may be used only for the purpose of distinguishing the elements from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the scope of the invention as set forth herein. Similarly, the second element may also be referred to as a first element.

Herein, the upper portion, the lower portion, the upper side, the lower side, the upper surface, the lower surface, and the like are used based on the drawings. For example, the first connecting member is disposed at a level higher than the level of the redistribution layer. However, the scope of patent application is not limited to this. In addition, the vertical direction means the upward direction and the downward direction, and the horizontal direction means a direction perpendicular to the upward direction and the downward direction. In this case, the vertical cross section means a case taken along a plane in the vertical direction, and an example of the vertical cross section may be a cross-sectional view shown in the drawing. In addition, the horizontal cross section means a case of being taken along a plane in the horizontal direction, and an example of the horizontal cross section may be a plan view shown in the drawing. Electronic device

FIG. 1 is a block diagram showing an example of an electronic device system.

Referring to FIG. 1 , the electronic device 1000 can accommodate the motherboard 1010 . The motherboard 1010 can include a wafer related component 1020, a network related component 1030, other components 1040, etc. that are physically or electrically connected to the motherboard 1010. The components can be connected to other components as will be described below to form various signal lines 1090.

The wafer related component 1020 may include: a memory chip such as a volatile memory (such as a dynamic random access memory (DRAM)), and a non-volatile memory (such as a read only memory (read only memory). ROM)), flash memory, etc.; application processor chips, such as, for example, a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, graphics processing unit (graphics) Processing unit (GPU)), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc.; and logic chip, such as an analog-to-digital converter (ADC), Application-specific integrated circuit (ASIC) or the like. However, wafer related component 1020 is not limited thereto, but may include other types of wafer related components. Additionally, wafer related components 1020 can be combined with each other.

The network related component 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), global interworking microwave Worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access +(high speed downlink packet access +, HSDPA+), high speed uplink packet access + (HSUPA+), enhanced data GSM environment (enhanced data GSM environment, EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiplexing Code division multiple acce Ss, CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G, and after the agreement Any other wireless agreement and cable agreement. However, network related component 1030 is not limited thereto, but may also include a variety of other wireless standards or protocols or wired standards or protocols. Additionally, network related components 1030 can be combined with one another with the wafer related components 1020 set forth above.

Other components 1040 can include, but are not limited to, high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (low) Temperature co-fired ceramic (LTCC), electromagnetic interference (EMI) filter, multilayer ceramic capacitor (MLCC), etc. However, other components 1040 are not limited thereto, but may also include passive components and the like for various other purposes. Additionally, other components 1040 can be combined with one another in conjunction with wafer related component 1020 or network related component 1030 as set forth above.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may be physically connected or electrically connected to the motherboard 1010, or other components that may not be physically connected or electrically connected to the motherboard 1010. The other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (figure Not shown), compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (eg A hard disk drive (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown) Wait. However, the other components are not limited thereto, but may be other components that may include various uses depending on the type of the electronic device 1000 or the like.

The electronic device 1000 can be, for example, a smart phone, a personal digital assistant (PDA), a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, Notebook PC, portable Internet PC (netbook PC), TV, video game machine, smart watch, car components, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

2 is a perspective schematic view showing an example of an electronic device.

Referring to FIG. 2, the electronic device can be, for example, a smart phone 1100. In the smart phone 1100, a radio frequency integrated circuit (RFIC) can be used in a semiconductor package form, and the antenna can be used in the form of a substrate or a module. The RF integrated circuit and the antenna can be electrically connected to each other in the smart phone 1100, and thus the radiation R of the antenna signal in various directions is possible. A semiconductor package including a radio frequency integrated circuit and a substrate or module including the antenna can be used in various forms in an electronic device such as a smart phone. Semiconductor package

In general, many sophisticated circuits are integrated into a semiconductor wafer. However, the semiconductor wafer itself cannot function as a completed semiconductor product and may be damaged by external physical or chemical influences. Therefore, the semiconductor wafer cannot be used alone, but it can be packaged in an electronic device or the like and used in a package state in an electronic device or the like.

Here, since there is a difference in circuit width in terms of electrical connection between the semiconductor wafer and the main board of the electronic device, a semiconductor package is required. In detail, the size of the connection pads of the semiconductor wafer and the spacing between the connection pads of the semiconductor wafer are extremely precise, but the size of the component mounting pads of the main board used in the electronic device and the interval between the component mounting pads of the main board are described. Significantly larger than the size and spacing of the connection pads of the semiconductor wafer. Therefore, it may be difficult to mount the semiconductor wafer directly on the main board, and a packaging technique for buffering the difference in circuit width between the semiconductor wafer and the main board may be required.

Depending on the structure and purpose of the semiconductor package, the semiconductor package fabricated by the package technology can be classified into a fan-in type semiconductor package or a fan-out type semiconductor package.

A fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail below with reference to the drawings. Fan-in semiconductor package

3A and 3B are schematic cross-sectional views showing a state of a fan-in type semiconductor package before and after packaging.

4 is a schematic cross-sectional view showing a packaging process of a fan-in type semiconductor package.

Referring to FIGS. 3 and 4, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state, and the semiconductor wafer 2220 includes: a body 2221 including, but not limited to, germanium (Si), germanium ( Ge), gallium arsenide (GaAs), etc.; a connection pad 2222 formed on one surface of the body 2221 and including, for example, a conductive material such as aluminum (Al); and a passivation layer 2223 such as an oxide film or nitrogen A chemical film or the like is formed on one surface of the body 2221 and covers at least a portion of the connection pad 2222. In this case, since the connection pad 2222 is significantly small, it is difficult to mount the integrated circuit (IC) on a printed circuit board (PCB) and a motherboard or the like of the electronic device.

Thus, depending on the size of the semiconductor wafer 2220, a connecting member 2240 is formed on the semiconductor wafer 2220 to rewire the connection pads 2222. The connecting member 2240 can be formed by forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as, for example, a photo-imaging dielectric (PID) resin, to form a via hole for opening the connection pad 2222. The hole 2243h is followed by the formation of the wiring pattern 2242 and the through hole 2243. Next, a passivation layer 2250 protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an under bump metal layer 2260 or the like may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 can be manufactured by a series of processes.

As described above, the fan-in type semiconductor package may have a package form in which all connection pads (for example, input/output (I/O) terminals) of the semiconductor wafer are disposed in the semiconductor wafer, and may have excellent electric power. Sexual characteristics and production at low cost. Therefore, many components mounted in smart phones have been manufactured in the form of fan-in type semiconductor packages. In particular, a number of components have been developed that are installed in smart phones for fast signal transmission while having a compact size.

However, since all of the input/output terminals in the fan-in type semiconductor package need to be disposed inside the semiconductor wafer, the space limitation of the fan-in type semiconductor package is large. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input/output terminals or a semiconductor wafer having a compact size. In addition, due to the above problems, the fan-in type semiconductor package may not be directly mounted and used on the main board of the electronic device. The reason is that the size of the input/output terminal of the semiconductor wafer and the semiconductor wafer even in the case where the size of the input/output terminal of the semiconductor wafer and the interval between the respective input/output terminals of the semiconductor wafer are increased by the rewiring process The spacing between the various input/output terminals may still be insufficient for the fan-in type semiconductor package to be directly mounted on the motherboard of the electronic device.

5 is a schematic cross-sectional view showing a state in which a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view showing a state in which a fan-in type semiconductor package is embedded in an interposer and finally mounted on a main board of an electronic device.

Referring to FIGS. 5 and 6, in the fan-in type semiconductor package 2200, the connection pads 2222 (ie, input/output terminals) of the semiconductor wafer 2220 can be re-routed via the interposer substrate 2301, and the fan-in type semiconductor package 2200 can be It is finally mounted on the main board 2500 of the electronic device in a state of being mounted on the interposer substrate 2301. In this case, the solder balls 2270 and the like may be fixed by the underfill resin 2280 or the like, and the outer side surface of the semiconductor wafer 2220 may be covered with the molding material 2290 or the like. Alternatively, the fan-in type semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input/output terminals) of the semiconductor wafer 2220 may be embedded in the interposer substrate 2302 in the fan-in type semiconductor package 2200. The rewiring is performed by the interposer substrate 2302, and the fan-in type semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device.

As described above, it may be difficult to mount and use a fan-in type semiconductor package directly on the main board of the electronic device. Therefore, the fan-in type semiconductor package can be mounted on a separate interposer substrate and then mounted on the main board of the electronic device by a packaging process, or the fan-in type semiconductor package can be embedded in the interposer substrate in the fan-in type semiconductor package. Install and use on the motherboard of the electronic device. Fan-out type semiconductor package

Fig. 7 is a schematic cross-sectional view showing a fan-out type semiconductor package.

Referring to FIG. 7 , in the fan-out type semiconductor package 2100 , for example, the outer side surface of the semiconductor wafer 2120 is protected by the encapsulant 2130 , and the connection pad 2122 of the semiconductor wafer 2120 is directed to the semiconductor wafer 2120 by the connecting member 2140 . Rewiring outside. In this case, the passivation layer 2150 is further formed on the connection member 2140, and the under bump metal layer 2160 is further formed in the opening of the passivation layer 2150. Solder balls 2170 are further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connecting member 2140 includes an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via hole 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which input/output terminals of the semiconductor wafer are re-wired by a connection member formed on the semiconductor wafer and disposed outside the semiconductor wafer. As described above, in the fan-in type semiconductor package, all of the input/output terminals of the semiconductor wafer need to be disposed in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls need to be reduced, so that the standardized ball layout may not be used in the fan-in type semiconductor package. On the other hand, the fan-out type semiconductor package has a form in which input/output terminals of a semiconductor wafer are re-wired by a connection member formed on a semiconductor wafer and disposed outside the semiconductor wafer as described above. Therefore, even in the case where the size of the semiconductor wafer is reduced, the standardized ball layout can be used in the fan-out type semiconductor package as well, so that the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer. As described below.

8 is a schematic cross-sectional view showing a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to FIG. 8, the fan-out type semiconductor package 2100 is mounted on the main board 2500 of the electronic device by solder balls 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the connection member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to the fan-out area outside the size of the semiconductor wafer 2120, thereby making The standardized ball layout can be used in the fan-out type semiconductor package 2100 as well. Therefore, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate interposer or the like.

As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer, the fan-out type semiconductor package can be thinner than the thickness of the fan-in type semiconductor package using the interposer substrate. Implemented below. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out type semiconductor package has excellent thermal characteristics and electrical characteristics, which makes the fan-out type semiconductor package particularly suitable for use in mobile products. Therefore, the fan-out type semiconductor package can be implemented in a more compact form than the general stacked package (POP) type using a printed circuit board (PCB), and can solve problems caused by the occurrence of warpage.

The fan-out type semiconductor package means a packaging technique for mounting a semiconductor wafer on a main board or the like of an electronic device as described above and protecting the semiconductor wafer from external influences, and it is printed with a printed circuit board (PCB) such as an interposer substrate or the like. The difference in concept is that the printed circuit board has a different specification, purpose, and the like from the fan-out type semiconductor package, and a fan-in type semiconductor package is embedded therein. Composite antenna substrate and semiconductor package module

9 is a schematic cross-sectional view showing an example of a composite antenna substrate and a semiconductor package module.

10 is a schematic plan view taken along line I-I' of the composite antenna substrate and the semiconductor package module of FIG. 9.

Referring to FIGS. 9 and 10, the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments of the present disclosure may have a form in which the fan-out type semiconductor package 100A and the antenna substrate 200A are coupled to each other. More specifically, the composite antenna substrate and the semiconductor package module 300A may have a form in which the fan-out type semiconductor package 100A and the antenna substrate 200A are integrated with each other.

The fan-out type semiconductor package 100A includes a core member 110 having a through hole 110H, and a semiconductor wafer 120 disposed in the through hole 110H and having an active surface and an inactive surface opposite to the active surface, wherein the active surface is disposed The connection pad 120P; the passive component 125 is disposed adjacent to the semiconductor wafer 120 in the through hole 110H. The fan-out type semiconductor package 100A further includes an encapsulant 130 encapsulating at least a portion of the core member 110, at least a portion of the semiconductor wafer 120, and at least a portion of the passive component 125. The connection member 140 is disposed on the active surface of the semiconductor wafer 120. The back side wiring layer 132 is disposed on the inactive surface of the semiconductor wafer 120 and the core member 110. The passivation layer 150 is disposed under the encapsulation 130. The under bump metal layer 160 is connected to the back side wiring layer 132, and the electrical connection structure 170 is connected to the under bump metal layer. The core member 110 includes a core wiring layer 112a and a core wiring layer 112b electrically connected to the connection pad 120P, and the connection member 140 includes a redistribution layer 142 electrically connected to the connection pad 120P. In an embodiment, the semiconductor wafer 120 can be configured to face upward toward the antenna substrate 200A.

The antenna substrate 200A includes an antenna member 210, wherein a first pattern layer 212a including an antenna pattern 212aA is disposed on an upper surface of the insulating layer 211, and a second pattern layer 212b including a ground pattern 212bG is disposed on a lower surface of the insulating layer, And a through hole 213 is formed in the insulating layer 211. The through hole 213 penetrates through the insulating layer 211 and includes a feed line 213F electrically connected to the antenna pattern 212aA. The antenna substrate 200A further includes a wiring member 220 disposed under the antenna member 210 and including a wiring layer 222 including a feed pattern 222F electrically connected to the feed line 213F. The passivation layer 230 is disposed on the antenna member 210 and covers the first wiring layer 212a. In an embodiment, the antenna member 210 may be thicker than the wiring member 220.

The wiring member 220 of the antenna substrate 200A is in contact with the connection member 140 of the fan-out type semiconductor package 100A, and is integrated with each other without using a separate electrical connection structure or the like. The expression "coupled" conceptually includes a situation in which two components are integrated into each other and a form in which two components are stacked together using an intermediate.

In the case where the RF integrated circuit and the antenna are formed as a composite module, in order to determine the resonant frequency and bandwidth of the antenna, it is necessary to consider how to implement the antenna, the ground plane, the dielectric material, the feeder, and the like. For example, the distance between the antenna and the ground plane (ie, the thickness of the air layer or the thickness of the dielectric material) has a sensitive effect on the characteristics of the antenna, and the distance needs to be kept constant and managed to ensure the antenna. Stable radiation characteristics.

In the case of the related art, the manner in which the antenna is formed on the redistribution layer of the semiconductor package and the ground plane is formed on the main board has been utilized. In this case, the thickness or distance between the antenna and the ground plane requires a certain height to be ensured by the solder balls thus encapsulated. Therefore, when the motherboard is mounted on the package, the thickness difference is caused by the height of the solder ball collapse. In addition, in this case, a dielectric material is used as the material of the air layer, and thus the size of the antenna is increased. In addition, in this case, a flux or foreign matter can be inserted into the space between the antenna and the ground plane, thus significantly affecting the characteristics of the antenna. In addition, in such a case, when heat is generated in the radio frequency integrated circuit, it is difficult to secure a sufficient heat dissipation path, and therefore, there is a limitation in utilizing such a method in a product using a large amount of electric power.

On the other hand, the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiment may have a structure in which the fan-out type semiconductor package 100A (wherein the semiconductor wafer 120 such as a radio frequency integrated circuit is packaged in a face-up form) It is integrated with the antenna substrate 200A including the antenna pattern 212aA such as a dipole antenna or a bulk antenna. In this case, the antenna member 210 can be introduced into the antenna substrate 200A. The antenna member 210 may include an antenna pattern 212aA and a ground pattern 212bG respectively formed on opposite surfaces of the insulating layer 211, and includes a feed line 213F that is implemented to pass through the through hole 213 or the like penetrating the insulating layer 211. Therefore, regardless of changes in the external environment, the distance between the antenna and the ground plane can be stably ensured in a single composite module to maintain the radiation characteristics of the antenna, and in addition, the signal path between the antenna and the semiconductor wafer can be significantly shortened. To ensure stable radio frequency (RF) characteristics.

Further, the size of the antenna can be reduced by appropriately using the dielectric constant (Dk) of the insulating layer 211 of the antenna member 210 and the dielectric constant (Dk) of the dielectric layer 111 of the core member 110 to simplify the composite antenna substrate and The overall structure of the semiconductor package module further increases space efficiency and reduces cost. In addition, it is also possible to prevent deterioration of the performance of the antenna due to the influence of foreign matter in the space between the antenna and the ground plane. In addition, the rigidity of the composite antenna substrate and the semiconductor package module 300A can be improved by introducing the core member 110, and the core member 110 can provide an electrical connection path to be effectively provided in the composite antenna substrate and the semiconductor package module. The signal path is connected to the electrical connection structure 170 of the motherboard or the like. The passive component 125 can be embedded in the fan-out type semiconductor package 100A together with the semiconductor wafer 120 to significantly reduce loss of signals, power, and the like.

The composite antenna substrate and the components of the semiconductor package module 300A according to an exemplary embodiment will be explained in more detail below with reference to the drawings.

First, the fan-out type semiconductor package 100A includes a core member 110 having a through hole 110H, and a semiconductor wafer 120 disposed in the through hole 110H and having an active surface and an inactive surface opposite to the active surface, the active surface A connection pad 120P is provided. The fan-out type semiconductor package 100A further includes: a passive component 125 disposed adjacent to the semiconductor wafer 120 in the through hole 110H; and an encapsulation body 130 encapsulating at least a portion of the core member 110, at least a portion of the semiconductor wafer 120, and the passive component 125 At least part. The connection member 140 is disposed on the active surface of the semiconductor wafer 120. The back side wiring layer 132 is disposed on the inactive surface of the semiconductor wafer 120 and the core member 110. The passivation layer 150 is disposed under the encapsulation 130. The under bump metal layer 160 is connected to the back side wiring layer 132, and the electrical connection structure 170 is connected to the under bump metal layer, as described above. The core member 110 includes a core wiring layer 112a and a core wiring layer 112b electrically connected to the connection pad 120P, and the connection member 140 includes a redistribution layer 142 electrically connected to the connection pad 120P.

The core member 110 may include a core wiring layer 112a and a core wiring layer 112b to thereby reduce the number of layers of the connection member 140. If necessary, a suitable material may be selected for the core member 110 to increase the rigidity of the fan-out type semiconductor package 100A depending on certain materials, and to ensure thickness uniformity of the envelope body 130. An electrical path can be provided in the composite antenna substrate and the semiconductor package module 300A by the core wiring layer 112a and the core wiring layer 112b of the core member 110 and the core via 113. The core member 110 may have a through hole 110H. The semiconductor wafer 120 and the passive component 125 may be disposed side by side in the through hole 110H to be spaced apart from the core member 110 by a predetermined distance. The side surface of the semiconductor wafer 120 and the side surface of the passive component 125 may be surrounded by the core member 110. However, this form is merely an example, and the present embodiment can be variously modified to have other forms, and the core member 110 can perform another function in this form.

The core member 110 may include: a dielectric layer 111; a first core wiring layer 112a disposed on an upper surface of the dielectric layer 111; a second core wiring layer 112b disposed on a lower surface of the dielectric layer 111; The hole 113 penetrates the dielectric layer 111 and connects the first core wiring layer 112a and the second core wiring layer 112b to each other. The thickness of the first core wiring layer 112a and the second core wiring layer 112b of the core member 110 may be greater than the thickness of the redistribution layer 142 of the connection member 140. Since the thickness of the core member 110 can be similar to or greater than the thickness of the semiconductor wafer 120 or the like, the first core wiring layer 112a and the second core wiring layer 112b having a large size can be formed by the substrate process in accordance with the specifications of the core member 110. On the other hand, the redistribution layer 142 of the connection member 140 can be formed in a small size by a semiconductor process to achieve thinness.

The material of the dielectric layer 111 is not particularly limited. For example, an insulating material can be used as the material of the dielectric layer 111. In this case, the insulating material may be a thermosetting resin such as an epoxy resin; a thermoplastic resin such as a polyimide resin; and a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler such as glass fiber (or glass cloth, or Resins in core materials such as glass fiber cloth, such as prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT) )Wait. Alternatively, a photosensitive dielectric resin can be used as the insulating material. For example, depending on the characteristics of the desired material, a general copper foil laminate (CCL) with low dissipation factor (Df) and low dielectric constant or low dissipation factor and high can be used. A dielectric constant glass or ceramic-based insulating material is used as the material of the dielectric layer 111.

The core wiring layer 112a and the core wiring layer 112b can be used to rewire the connection pads 120P of the semiconductor wafer 120. In addition, when the fan-out type semiconductor package 100A is electrically connected to other components disposed on the fan-out type semiconductor package 100A and under the fan-out type semiconductor package 100A, the core wiring layer 112a and the core wiring layer 112b can be used as a connection pattern. The material of each of the core wiring layer 112a and the core wiring layer 112b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni). ), lead (Pb), titanium (Ti), or an alloy thereof. The core wiring layer 112a and the core wiring layer 112b perform various functions depending on the design of their corresponding layers. For example, the core wiring layer 112a and the core wiring layer 112b may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power supply (PWR) pattern, and the like, such as a data signal. In addition, the core wiring layer 112a and the core wiring layer 112b may include via pads or the like.

The core via 113 electrically connects the core wiring layer 112a and the core wiring layer 112b formed on different layers to each other, thereby forming an electrical path in the core member 110. The material of each of the core vias 113 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb). ), titanium (Ti), or an alloy thereof. Each of the core vias 113 may be completely filled with a conductive material, or a conductive material may be formed along the walls of the corresponding via holes. In addition, each of the core through holes 113 may have any known shape such as an hourglass shape, a cylindrical shape, or the like. The core via 113 may also include a via for the signal and a via for grounding, and the like.

The metal layer 115 may be further disposed on the wall of the through hole 110H of the core member 110 as necessary. A metal layer 115 may be formed on the entire wall of the through hole 110H to surround the semiconductor wafer 120. Therefore, the heat dissipation characteristics can be improved, and the electromagnetic wave blocking effect can be achieved. The material of the metal layer 115 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti). Or its alloy. The metal layer 115 may be electrically connected to the ground pattern of the first core wiring layer 112a and/or the second core wiring layer 112b to thereby function as a ground plane.

The semiconductor wafer 120 may be an integrated circuit (IC) in a bare state in which hundreds to millions or more of components are integrated into a single wafer. The integrated circuit (IC) can be, for example, a radio frequency integrated circuit (RFIC). That is, the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments may be a package in which the RF integrated circuit and the millimeter wave/5G antenna are integrated with each other. The semiconductor wafer 120 may include a body on which various circuits are formed, and the connection pad 120P may be formed on an active surface of the body. The body can be formed, for example, on the basis of an active wafer. In this case, bismuth (Si), germanium (Ge), gallium arsenide (GaAs), or the like can be used as a basic material of the body. The connection pad 120P can electrically connect the semiconductor wafer 120 to other components, and the material of each of the connection pads 120P can be a conductive material such as aluminum (Al), but is not limited thereto. The active surface of the semiconductor wafer 120 refers to the surface on which the connection pads 120P are disposed on the semiconductor wafer 120, and the inactive surface of the semiconductor wafer 120 refers to the surface of the semiconductor wafer 120 opposite the active surface. Although not shown in the drawings, a passivation layer (not shown) may be formed on the active side of the semiconductor wafer 120, the passivation layer having an opening exposing at least a portion of the connection pad 120P, and consisting of an oxide layer A nitride layer or the like is formed. The semiconductor wafer 120 can be configured to face up and thus have the shortest signal path to the antenna.

The passive component 125 may be disposed in the through hole 110H alongside the semiconductor wafer 120. Passive component 125 can be a known passive component such as a capacitor, inductor, or the like. As a non-limiting example, passive component 125 can be a capacitor. The passive component 125 can be electrically connected to the semiconductor wafer 120 by the connecting member 140. In addition, the passive component 125 can also be electrically connected to the antenna substrate 200A through the connecting member 140. The number of passive components 125 is not particularly limited.

The encapsulant 130 can be configured to protect the semiconductor wafer 120, the passive component 125, etc., and provide an insulating region. The encapsulation form of the encapsulant 130 is not particularly limited, but may be in the form of at least a portion of the encapsulation 130 surrounding the semiconductor wafer 120 and at least a portion of the passive component 125. For example, the encapsulant 130 may cover the lower surface of the core member 110, cover the side surface and the inactive surface of the semiconductor wafer 120, and cover the side surface and the lower surface of the passive component 125. In addition, the encapsulation 130 may fill a space in the through hole 110H. A certain material of the encapsulant 130 is not particularly limited, but may be, for example, a photoimgable encapsulant (PIE). Alternatively, if necessary, an insulating material such as a film can be used, for example, ajinomoto.

The back side wiring layer 132 is used for rewiring the connection pad 120P of the semiconductor wafer 120, and the material of the back side wiring layer 132 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin ( Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The back side wiring layer 132 performs various functions depending on the design of the corresponding layer. For example, the back side wiring layer 132 may include a ground pattern, a signal pattern, and the like. In addition, the back side wiring layer 132 may include a via pad, an electrical connection structure pad, or the like.

The back side via hole 133 electrically connects the back side wiring layer 132, the second core wiring layer 112b, and the like formed on the different layers to each other. In addition, the back side via 133 may be connected to the metal layer 122 formed on the inactive surface of the semiconductor wafer 120 as necessary, thus serving as a heat dissipation via. The material of each of the back side vias 133 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead ( Pb), titanium (Ti), or an alloy thereof. Each of the back side through holes 133 may be completely filled with a conductive material, or a conductive material may be formed along the walls of the respective back side through holes. In addition, each of the back side through holes 133 may have any known shape such as a tapered shape, a cylindrical shape, or the like.

The connection member 140 rewires the connection pads 120P of the semiconductor wafer 120. The tens to hundreds of connection pads 120P of the semiconductor wafer 120 having various functions can be re-routed by the connection member 140. In addition, the connection member 140 may be connected to the wiring member 220 to thereby provide a connection path such that the fan-out type semiconductor package 100A and the antenna substrate 200A may be integrated with each other. The connection member 140 may include an insulating layer 141, a redistribution layer 142 disposed on the insulating layer 141, and a via hole 143 penetrating the insulating layer 141 and connected to the redistribution layer 142. The connecting member 140 may be formed of a single layer, or may be formed of a plurality of layers having a number of layers as shown in the drawings.

The material of each of the insulating layers 141 may be an insulating material. In this case, a photosensitive insulating material such as a photosensitive dielectric resin can also be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has a photosensitive property, the insulating layer 141 may be formed to have a reduced thickness, and the fine pitch of the via holes 143 may be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layer 141 is a plurality of layers, the materials of the insulating layer 141 may be the same as each other, and may be different from each other as necessary. When the insulating layer 141 is a plurality of layers, the insulating layers 141 may be integrated with each other according to a process, so that the boundary between the insulating layers may also be inconspicuous.

The redistribution layer 142 can be used to substantially rewire the connection pads 120P. The material of each of the redistribution layers 142 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb). ), titanium (Ti), or an alloy thereof. The redistribution layer 142 performs various functions depending on the design of its corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power supply (PWR) pattern, and the like, such as a data signal. In addition, the redistribution layer 142 may include a via pad, a connection terminal pad, or the like. The redistribution layer 142 may include a feed pattern electrically connected to the feed line 223F.

The via hole 143 electrically connects the redistribution layer 142, the connection pad 120P, and the like formed on the different layers, thereby forming an electrical path in the fan-out type semiconductor package 100A. The material of each of the via holes 143 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb). , titanium (Ti), or an alloy thereof. Each of the through holes 143 may be completely filled with a conductive material, or a conductive material may be formed along the walls of the respective through holes. In addition, each of the through holes 143 may have any shape known in the related art, such as a tapered shape, a cylindrical shape, or the like. The via 143 may include a feed line electrically connected to the feed line 223F.

The passivation layer 150 can protect the backside wiring layer 132 from external physical or chemical damage. The passivation layer 150 may include an insulating resin and an inorganic filler, but may not include glass fibers. For example, the passivation layer 150 may be formed of a film made of Ajinomoto. However, the passivation layer 150 is not limited thereto, but may be formed of a photosensitive imaging dielectric, a solder resist, or the like.

The under bump metal layer 160 can improve the connection reliability of the electrical connection structure 170 to improve the board level reliability of the fan-out type semiconductor package 100A. The under bump metal layer 160 may be connected to various pads of the electrical connection structure of the backside wiring layer 132 exposed through the openings of the encapsulant 130 and/or the passivation layer 150. The under bump metal layer 160 may be formed in the opening of the encapsulant 130 by a known metallization method using a known conductive material such as a metal, but is not limited thereto.

The electrical connection structure 170 may be additionally configured to physically connect or electrically connect the fan-out type semiconductor package 100A externally. For example, the fan-out type semiconductor package 100A can be mounted on the main board of the electronic device by using the electrical connection structure 170. Each of the electrical connection structures 170 may be formed of a conductive material such as solder. However, this is merely an example, and the material of each of the electrical connection structures 170 is not limited thereto. Each of the electrical connection structures 170 can be a land, a ball, a pin, or the like. The electrical connection structure 170 may be formed in a multilayer structure or a single layer structure. When the electrical connection structure 170 is formed in a multilayer structure, the electrical connection structure 170 may include a copper (Cu) pillar and solder. When the electrical connection structure 170 is formed in a single layer structure, the electrical connection structure 170 may include tin-silver solder or copper (Cu). However, this is merely an example, and the electrical connection structure 170 is not limited thereto. The number, spacing, configuration, and the like of the electrical connection structures 170 are not particularly limited, and can be sufficiently modified by those skilled in the art to look at specific details of the design. For example, the electrical connection structure 170 may be set to the number of tens to thousands according to the number of the connection pads 120P, or may be set to the number of tens to thousands or more or tens to thousands or more. A small amount.

At least one of the electrical connection structures 170 can be disposed in the fan-out area. The fan-out area is an area other than the area in which the semiconductor wafer 120 is disposed. Fan-out packages offer superior reliability compared to fan-in packages, implement multiple input/output (I/O) terminals, and facilitate three-dimensional (3D) interconnects. In addition, the fan-out package can be manufactured to have a small thickness and can have a price compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like. Competitiveness.

Next, the antenna substrate 200A may include: an antenna member 210, wherein the first pattern layer 212a including the antenna pattern 212aA is disposed on the upper surface of the insulating layer 211, and the second pattern layer 212b including the ground pattern 212bG is disposed under the insulating layer On the surface, a through hole 213 is formed in the insulating layer 211. The through hole 213 penetrates the insulating layer 211 and includes a feed line 213F electrically connected to the antenna pattern 212aA. The wiring member 220 is disposed under the antenna member 210 and includes a wiring layer 222. The wiring layer 222 includes a feed pattern 222F electrically connected to the feed line 213F; and a passivation layer 230 disposed on the antenna member 210 and covering the first wiring layer 212a. The antenna member 210 may be thicker than the wiring member 220. The wiring member 220 and the connecting member 140 can be in contact with each other without using a separate electrical connection structure or the like. The antenna substrate 200A may have an asymmetrical structure with respect to the antenna member 210.

The antenna member 210 as a region capable of implementing the millimeter wave/5G antenna may include: an insulating layer 211; a first pattern layer 212a formed on an upper surface of the insulating layer; and a second pattern layer 212b formed on a lower surface of the insulating layer 211 And a through hole 213 penetrating the insulating layer 211 and electrically connecting the first pattern layer 212a and the second pattern layer 212b to each other. In the antenna member 210, the first pattern layer 212a may include an antenna pattern 212aA, the second pattern layer 212b may include a ground pattern 212bG, and the insulating layer 211 may be disposed between the first pattern layer 212a and the second pattern layer 212b. Therefore, regardless of changes in the external environment, the distance between the antenna and the ground plane can be stably ensured in a single composite module to maintain the radiation characteristics of the antenna. In addition, the size of the antenna can be reduced by appropriately using the dielectric constant (Dk) of the insulating layer 211 to simplify the overall structure of the composite antenna substrate and the semiconductor package module, thereby improving space efficiency and reducing cost. For example, the dielectric constant (Dk) of the insulating layer 211 of the antenna member 210 may be greater than the dielectric constant (Dk) of the dielectric layer 111 of the core member 110. The dielectric constant (Dk) of the insulating layer 211 of the antenna member 210 may be greater than the dielectric constant of the composite antenna substrate and another insulating layer or dielectric layer in the semiconductor package module 300A.

An insulating material can be used as the material of the insulating layer 211. In this case, the insulating material may be a thermosetting resin such as an epoxy resin; a thermoplastic resin such as a polyimide resin; a reinforcing material such as glass fiber (or glass cloth or glass fiber cloth) and/or an inorganic filler, and The material of the thermosetting resin and the thermoplastic resin, for example, a prepreg, a scented constitutive film, FR-R, bismaleimide triazine, or the like. For example, depending on the desired properties of the insulating material, a general copper foil laminate with a low dissipation factor and a low dielectric constant or a glass or ceramic insulating material with a low dissipation factor and a high dielectric constant can be used as the insulation. The material of layer 211. When a glass or ceramic material having a high dielectric constant and a low dissipation factor is used as the material of the insulating layer 211, the antenna can be formed in a smaller size. The thickness of the insulating layer 211 is freely changed by the visual impedance matching characteristic.

The first wiring layer 212a may include an antenna pattern 212aA that substantially implements a millimeter wave/5G antenna, and may include other ground patterns 212aG and the like. The antenna pattern 212aA may be a dipole antenna, a block antenna, or the like. The antenna pattern 212aA may be surrounded by a ground pattern, but is not limited thereto. The material of the first wiring layer 212a may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium ( Ti), or an alloy thereof.

The second wiring layer 212b may include a ground pattern 212bG for the antenna pattern 212aA, and may include other signal patterns or the like. The ground pattern 212bG may have the form of a ground plane. The material of the second wiring layer 212b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium ( Ti), or an alloy thereof.

The through hole 213 electrically connects the first wiring layer 212a and the second wiring layer 212b formed on different layers to each other, thereby forming an electrical path in the antenna member 210. The via 213 may include a feed line 213F and may include other ground vias 213G and the like. The feed line 213F is electrically connected to the antenna pattern 212aA. The ground via 213G can densely surround the feed line 213F. The material of each of the vias 213 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb). , titanium (Ti), or an alloy thereof. Each of the through holes 213 may be completely filled with a conductive material, or as shown in the drawings, a conductive material may be formed along the walls of the respective through hole. Additionally, each of the through holes 213 may have any known vertical cross-sectional shape, such as a tapered shape, a cylindrical shape, or the like.

The wiring member 220 may include: an insulating layer 221; a wiring layer 222 formed on the insulating layer 221; and a via hole 223 penetrating the insulating layer 221 and electrically connecting the wiring layers 222 formed on different layers to each other or the wiring layer 222 Electrically connected to the pattern layer or redistribution layer of another component. The wiring member 220 may have a larger number of wiring layers or only one wiring layer.

The material of each of the insulating layers 221 may be an insulating material. In this case, a film of ajinomoto, a photosensitive imaging medium, or the like can be used as the insulating material. When the number of the insulating layers 221 is plural, the boundary between the insulating layers 221 may not be obvious, but is not necessarily limited thereto.

The wiring layer 222 may include a feed pattern 222F electrically connected to the feed line 213F, and may include other ground patterns 222G and the like. The material of each of the wiring layers 222 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb). , titanium (Ti), or an alloy thereof.

The via hole 223 may electrically connect the wiring layers 222 formed on the different layers to each other or electrically connect the wiring layer 222 to the pattern layer or the redistribution layer of the other member to provide an electrical via. The via 223 may include a feed line 223F electrically connected to the feed pattern 222F. The material of each of the vias 223 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb). , titanium (Ti), or an alloy thereof.

The passivation layer 230 can protect the antenna member 210 from external physical or chemical damage. The passivation layer 230 may include an insulating resin and an inorganic filler, but may not include glass fibers. For example, the passivation layer 230 may be formed of a film made of Ajinomoto. However, the passivation layer 230 is not limited thereto, but may be formed of a photosensitive imaging dielectric, a solder resist, or the like.

11A and 11B are schematic views showing various examples of the composite antenna substrate of FIG. 9 and the antenna substrate of the semiconductor package module.

Referring to FIGS. 11A and 11B, the antenna substrate 200A may have a form including a plurality of dipole antennas 210DA and a plurality of block antennas 210PA. Alternatively, the antenna substrate 200A may have a form in which it includes a larger number of block antennas 210PA. That is, the antenna substrate 200A is visually designed to include various types of antennas.

FIG. 12 is a schematic view showing an application of the block antenna of the composite antenna substrate of FIG. 9 and the antenna substrate of the semiconductor package module.

Referring to FIG. 12, the block antenna 210PA may have a form in which the antenna pattern 212bA and the feed line 213F are surrounded by the densely formed ground vias 213G. An insulating material such as the passivation layer 230 may be further disposed between the antenna pattern 212bA and the ground via 213G. The feed line 213F is electrically connected to the feed pattern 223F. Therefore, the feed line 213F can be electrically connected to the connection pad 120P.

FIG. 13 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 13 , the composite antenna substrate and the semiconductor package module 300B according to another exemplary embodiment of the present disclosure may have a form in which the antenna substrate 200B and the semiconductor package 100B are integrated with each other. In this case, in the semiconductor package 100B, the core member 110 may include a first dielectric layer 111a, a contact connecting member 140, a first core wiring layer 112a, a contact connecting member 140, and embedded in the first dielectric layer 111a. The second core wiring layer 112b is disposed on the other surface of the first dielectric layer 111a opposite to one surface of the first dielectric layer 111a in which the first core wiring layer 112a is embedded; the second dielectric layer 111b And disposed on the first dielectric layer 111a and covering the second core wiring layer 112b; and the third core wiring layer 112c is disposed on the second dielectric layer 111b. The first core wiring layer 112a, the second core wiring layer 112b, and the third core wiring layer 112c may be electrically connected to the connection pad 120P. The first core wiring layer 112a and the second core wiring layer 112b and the second core wiring layer 112b and the third core wiring layer 112c may pass through the first core via holes respectively penetrating the first dielectric layer 111a and the second dielectric layer 111b The 113a and the second core vias 113b are electrically connected to each other. Meanwhile, at least one of the first core wiring layer 112a, the second core wiring layer 112b, and the third core wiring layer 112c may include a filter pattern (not shown) electrically connected to the antenna pattern 212aA. In this case, a material having a high dielectric constant can be used as the insulating material of the antenna member 210 to miniaturize the antenna, and a material having a low dielectric constant can be used as the insulating material of the core member 110 to significantly reduce the filtering. Loss of the device. However, the insulating material of the antenna member 210 and the insulating material of the core member 110 are not limited thereto.

When the first core wiring layer 112a is embedded in the first dielectric layer 111a, the step due to the thickness of the first core wiring layer 112a can be remarkably reduced, and the insulation distance of the connecting member 140 can thus be made constant . That is, the distance from the first redistribution layer 142a of the connection member 140 to the lower surface of the first dielectric layer 111a is between the distance from the first redistribution layer 142a of the connection member 140 to the connection pad 120P of the semiconductor wafer 120. The difference may be smaller than the thickness of the first core wiring layer 112a. Therefore, the high-density wiring design of the connecting member 140 can be easily achieved.

The distance between the redistribution layer 142 of the connection member 140 and the first core wiring layer 112a of the core member 110 may be greater than the distance between the redistribution layer 142 of the connection member 140 and the connection pad 120P of the semiconductor wafer 120. The reason is that the first core wiring layer 112a can be recessed in the first dielectric layer 111a. As described above, when the first core wiring layer 112a is recessed in the first dielectric layer 111a, thereby causing a step between the upper surface of the first dielectric layer 111a and the upper surface of the first core wiring layer 112a, it can be prevented. The material of the encapsulant 130 penetrates to contaminate the first core wiring layer 112a. The second core wiring layer 112b of the core member 110 may be disposed at a level between the active surface and the inactive surface of the semiconductor wafer 120. The core member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the second core wiring layer 112b formed in the core member 110 can be disposed at a level between the active surface and the inactive surface of the semiconductor wafer 120.

The thickness of the core wiring layer 112a, the core wiring layer 112b, and the core wiring layer 112c of the core member 110 may be greater than the thickness of the redistribution layer 142 of the connection member 140. Since the thickness of the core member 110 may be equal to or larger than the thickness of the semiconductor wafer 120, the core wiring layer 112a having a large size, the core wiring layer 112b, and the core wiring layer 112c may be formed in accordance with the specifications of the core member 110. On the other hand, the redistribution layer 142 of the connection member 140 may be formed to have a size relatively smaller than that of the core wiring layer 112a, the core wiring layer 112b, and the core wiring layer 112c to achieve thinness.

The material of each of the dielectric layer 111a and the dielectric layer 111b is not particularly limited. For example, an insulating material may be used as the material of each of the dielectric layer 111a and the dielectric layer 111b. In this case, the insulating material may be a thermosetting resin such as an epoxy resin; a thermoplastic resin such as a polyimide resin; a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler; or a thermosetting resin or a thermoplastic resin. A resin which is immersed in a core material such as glass fiber (or glass cloth, or glass fiber cloth) together with an inorganic filler, for example, a prepreg, a savory constitutive film, FR-4, bismaleimide triazine, or the like. Alternatively, a photosensitive dielectric resin can be used as the insulating material.

The core wiring layer 112a, the core wiring layer 112b, and the core wiring layer 112c can be used to rewire the connection pads 120P of the semiconductor wafer 120. The material of each of the core wiring layer 112a, the core wiring layer 112b, and the core wiring layer 112c may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au). ), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The core wiring layer 112a, the core wiring layer 112b, and the core wiring layer 112c perform various functions depending on the design of their corresponding layers. For example, the core wiring layer 112a, the core wiring layer 112b, and the core wiring layer 112c may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power supply (PWR) pattern, and the like, such as a data signal. In addition, the core wiring layer 112a, the core wiring layer 112b, and the core wiring layer 112c may include a signal via pad, a ground via pad, and the like.

The core via 113a and the core via 113b electrically connect the core wiring layer 112a, the core wiring layer 112b, and the core wiring layer 112c formed on different layers, thereby forming an electrical path in the core member 110. The material of each of the core via 113a and the core via 113b may be a conductive material. Each of the core via 113a and the core via 113b may be completely filled with a conductive material, or a conductive material may be formed along the walls of the respective via holes. In addition, each of the core through hole 113a and the core through hole 113b may have any shape known in the related art, such as a tapered shape, a cylindrical shape, or the like. When the holes of the first core via 113a are formed, some of the pads of the first core wiring layer 112a may serve as a stopper, and thus, it may be advantageous for each of the first core vias 113a to have a lower A process of a tapered shape having a width greater than the width of the upper surface. In this case, the first core via 113a may be integrated with the pad pattern of the second core wiring layer 112b. In addition, when the holes of the second core via 113b are formed, some of the pads of the second core wiring layer 112b may serve as termination elements, and thus, it may be advantageous for each of the second core vias 113b to have a lower surface A process of a tapered shape having a width greater than the width of the upper surface. In this case, the second core via 113b may be integrated with the pad pattern of the third core wiring layer 112c.

Descriptions of other configurations may overlap with the descriptions set forth above with respect to the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments, and thus are omitted.

14 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 14 , the composite antenna substrate and the semiconductor package module 300C according to another exemplary embodiment of the present disclosure may have a form in which the antenna substrate 200C and the semiconductor package 100C are integrated with each other. In this case, in the semiconductor package 100C, the core member 110 may include a first dielectric layer 111a; the first core wiring layer 112a and the second core wiring layer 112b are respectively disposed on the opposite sides of the first dielectric layer 111a. On the surface, the second dielectric layer 111b is disposed on the first dielectric layer 111a and covers the first core wiring layer 112a; the third core wiring layer 112c is disposed on the second dielectric layer 111b; and the third dielectric layer 111c is disposed on the first dielectric layer 111a and covers the second core wiring layer 112b; and the fourth core wiring layer 112d is disposed on the third dielectric layer 111c. The first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may be electrically connected to the connection pad 120P. Since the core member 110 can include a large number of core wiring layers 112a, 112b, 112c, and 112d, the connecting member 140 can be further simplified. Therefore, the problem of a decrease in yield due to a defect occurring in the process of forming the connecting member 140 can be suppressed. At the same time, the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may penetrate through the first dielectric layer 111a, the second dielectric layer 111b, and the third dielectric layer respectively. The first core via 113a, the second core via 113b, and the third core via 113c of the electrical layer 111c are electrically connected to each other. Meanwhile, at least one of the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may include a filter pattern electrically connected to the antenna pattern 212aA (in the figure) Not shown). In this case, a material having a high dielectric constant can be used as the insulating material of the antenna member 210 to miniaturize the antenna, and a material having a low dielectric constant can be used as the insulating material of the core member 110 to significantly reduce the filtering. Loss of the device. However, the insulating material of the antenna member 210 and the insulating material of the core member 110 are not limited thereto.

The thickness of the first dielectric layer 111a may be greater than the thickness of the second dielectric layer 111b and the third dielectric layer 111c. The first dielectric layer 111a may be substantially thick to maintain rigidity, and the second dielectric layer 111b and the third dielectric layer 111c may be introduced to form a larger number of core wiring layers 112c and 112d. The insulating material included in the first dielectric layer 111a may be different from the insulating material of the second dielectric layer 111b and the third dielectric layer 111c. For example, the first dielectric layer 111a may be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second dielectric layer 111b and the third dielectric layer 111c may be a paste containing a filler and an insulating resin. The element constitutes a film or a photosensitive imaging dielectric film. However, the material of the first dielectric layer 111a and the materials of the second dielectric layer 111b and the third dielectric layer 111c are not limited thereto. Similarly, the diameter of the first core via 113a penetrating through the first dielectric layer 111a may be larger than the diameter of the second core via 113b penetrating through the second dielectric layer 111b and the third core pass through the third dielectric layer 111c. The diameter of the hole 113c.

The distance between the redistribution layer 142 of the connection member 140 and the third core wiring layer 112a of the core member 110 may be smaller than the distance between the redistribution layer 142 of the connection member 140 and the connection pad 120P of the semiconductor wafer 120. The reason is that the third core wiring layer 112c can be configured in a protruding form on the second dielectric layer 111b, and thus will contact the connecting member 140. The first core wiring layer 112a and the second core wiring layer 112b of the core member 110 may be disposed at a level between the active surface and the inactive surface of the semiconductor wafer 120. The core member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first core wiring layer 112a and the second core wiring layer 112b formed in the core member 110 may be disposed at a level between the active surface and the inactive surface of the semiconductor wafer 120.

The thickness of the core wiring layer 112a, the core wiring layer 112b, the core wiring layer 112c, and the core wiring layer 112d of the core member 110 may be greater than the thickness of the redistribution layer 142 of the connection member 140. Since the thickness of the core member 110 may be equal to or larger than the thickness of the semiconductor wafer 120, the core wiring layer 112a, the core wiring layer 112b, the core wiring layer 112c, and the core wiring layer 112d may also be formed to have a large size. On the other hand, the redistribution layer 142 of the connection member 140 may be formed to have a relatively small size to achieve thinness.

The description of the other configurations may overlap with the above descriptions set forth in the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments, and thus may be omitted.

15 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 15 , the composite antenna substrate and the semiconductor package module 300D according to another exemplary embodiment of the present disclosure may have a form in which the antenna substrate 200D and the semiconductor package 100D are integrated with each other. In this case, in the antenna substrate 200D, the wiring layer 222 of the wiring member 220 may include the filter pattern 222R. The filter pattern 222R can be electrically connected to the feed line 213F, the feed pattern 222F, and the like. The filter pattern 222R may be a microstrip line, a strip line, or the like, but is not limited thereto. The filter patterns 222R may be appropriately formed on the respective layers of the wiring member 220. A material having a high dielectric constant (Er1) property may be used as the insulating material of the antenna member 210 to reduce the size of the antenna, and a material having a low dielectric constant (Er12) property may be used as the insulating material of the wiring member 220 to be remarkable Reduce the loss of the filter. The ground pattern 212bG of the antenna member 210 and/or the ground pattern 222G of the wiring member 220 may provide a ground plane for the filter pattern 222R.

The description of the other configurations may overlap with the above descriptions set forth in the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments, and thus may be omitted. Meanwhile, the form of the core member 110 illustrated in the composite antenna substrate and the semiconductor package module 300B or 300C according to another exemplary embodiment may also be applied to the composite antenna substrate and the semiconductor package module according to another exemplary embodiment. 300D.

16 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 16 , the composite antenna substrate and the semiconductor package module 300E according to another exemplary embodiment of the present disclosure may have a form in which the antenna substrate 200E and the semiconductor package 100E are integrated with each other. In this case, in the semiconductor package 100E, the core member 110 may further include a third wiring layer 112c embedded in the dielectric layer 111 and electrically connect the third wiring layer 112c to the first wiring layer 112a and the second The second core via 113b and the third core via 113c of the wiring layer 112b. The third wiring layer 112c may include a filter pattern 112cR. The filter pattern 112cR may be electrically connected to the feed line 213F, the feed pattern 222F, and the like. The filter pattern 112cR may be a microstrip line, a strip line, or the like, but is not limited thereto. The ground pattern of the first wiring layer 112a and the second wiring layer 112b of the core member 210 may provide a ground plane for the filter pattern 112cR. The semiconductor wafer 120 can be configured in a face down form. When the semiconductor wafer 120 is configured in a face-down form, the active surface of the semiconductor wafer 120 can become close to the motherboard with a high heat dissipation effect on the motherboard. In some cases, the metal layer 122 formed on the inactive surface of the semiconductor wafer 120 may be replaced with a die attach film.

The description of the other configurations may overlap with the above descriptions set forth in the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments, and thus may be omitted. Meanwhile, the form of the core member 110 illustrated in the composite antenna substrate and the semiconductor package module 300B or 300C according to another exemplary embodiment may also be applied to the composite antenna substrate and the semiconductor package module according to another exemplary embodiment. 300E. In this case, the wiring layer of the core member disposed in the semiconductor package may include a filter pattern.

17 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 17, a composite antenna substrate and a semiconductor package module 300F according to another exemplary embodiment of the present disclosure may have a form in which an antenna substrate 200F and a semiconductor package 100F are integrated with each other. Meanwhile, in the composite antenna substrate and the semiconductor package module 300F according to another exemplary embodiment, the antenna substrate 200F may be first formed, and the semiconductor package 100F may be formed by using a bump 120B such as solder to laminate the semiconductor The wafer 120 is mounted on the wiring member 220 of the antenna substrate 200F, and the semiconductor wafer 120 is encapsulated by the encapsulant 130, and the back side alignment layer 132, the back side via hole 133, and the like are further formed. That is, the composite antenna substrate and the semiconductor package module 300F in which the antenna substrate 200F and the semiconductor package 100F are integrated with each other can be manufactured by a chip-last method. Therefore, the connection member 140 of the semiconductor package 100F can be integrated in the wiring member 220 of the antenna substrate 200F. That is, as shown in FIG. 17, a part of the wiring member 220 can be used as the connecting member 140. That is, the wiring member 220 may include the connection member 140. Meanwhile, in this case, the semiconductor package 100F may not include the core member 110, and the electrical connection path between the upper portion and the lower portion of the semiconductor package 100F may be provided through the through via 117 of the envelope 130.

The description of the other configurations may overlap with the above descriptions set forth in the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments, and thus may be omitted.

18 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 18, the composite antenna substrate and the semiconductor package module 300G according to another exemplary embodiment of the present disclosure may have a form in which the antenna substrate 200G and the semiconductor package 100G are integrated with each other. Meanwhile, in the composite antenna substrate and the semiconductor package module 300G according to another exemplary embodiment, the semiconductor wafer 120 of the semiconductor package 100G may be configured in a face-down form. In this case, the inactive surface of the semiconductor wafer 120 can be attached to the wiring member 220 of the antenna substrate 200G by the die attach film 128. When the semiconductor wafer 120 is configured in a face-down form, the active surface of the semiconductor wafer 120 can become close to the motherboard with a high heat dissipation effect on the motherboard. Further in this case, the connection member 140 of the semiconductor package 100G may be integrated in the wiring member 220 of the antenna substrate 200G. That is, as shown in FIG. 18, a part of the wiring member 220 can be used as the connecting member 140. That is, the wiring member 220 may include the connection member 140. Meanwhile, in this case, the semiconductor package 100G may not include the core member 110, and the electrical connection path between the upper portion and the lower portion of the semiconductor package 100G may be provided by the through via 117 passing through the encapsulant 130. .

The description of the other configurations may overlap with the above descriptions set forth in the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments, and thus may be omitted.

19 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 19, in a composite antenna substrate and a semiconductor package module 300H according to another exemplary embodiment of the present disclosure, the antenna substrate 200H and the semiconductor package 100H may be coupled to each other in a stacked package (PoP) form. In this case, the antenna substrate 200H may further include the second wiring member 240, and the second wiring member 240 is disposed under the first wiring member 220 and includes the insulating layer 241, the wiring layer 242, and the through hole 243. The passivation layers 190 and 250 may be disposed on the connection member 140 and the second wiring member 240, respectively. The connecting member 140 of the semiconductor package 100H and the second wiring member 240 of the antenna substrate 200H may be electrically connected to each other by an electrical connection structure 180 such as a solder ball.

The description of the other configurations may overlap with the above descriptions set forth in the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiments, and thus may be omitted.

20 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 20, a composite antenna substrate and a semiconductor package module according to another exemplary embodiment of the present disclosure, as in the above-described composite antenna substrate and semiconductor package module 300B according to another exemplary embodiment. In the semiconductor package 100I of the group 300I, the core member 110 may include: a first dielectric layer 111a, a contact connecting member 140; a first core wiring layer 112a contacting the connecting member 140 and embedded in the first dielectric layer 111a; The core wiring layer 112b is disposed on the other surface of the first dielectric layer 111a opposite to one surface of the first dielectric layer 111a in which the first core wiring layer 112a is embedded; the second dielectric layer 111b is disposed on the first surface A dielectric layer 111a covers the second core wiring layer 112b; and a third core wiring layer 112c is disposed on the second dielectric layer 111b. The first core wiring layer 112a, the second core wiring layer 112b, and the third core wiring layer 112c may be electrically connected to the connection pad 120P. The first core wiring layer 112a and the second core wiring layer 112b and the second core wiring layer 112b and the third core wiring layer 112c may pass through the first core via holes respectively penetrating the first dielectric layer 111a and the second dielectric layer 111b The 113a and the second core vias 113b are electrically connected to each other. Meanwhile, at least one of the first core wiring layer 112a, the second core wiring layer 112b, and the third core wiring layer 112c may include a filter pattern (not shown) electrically connected to the antenna pattern 212aA. In this case, a material having a high dielectric constant can be used as the insulating material of the antenna member 210 to miniaturize the antenna, and a material having a low dielectric constant can be used as the insulating material of the core member 110 to significantly reduce the filtering. Loss of the device. However, the insulating material of the antenna member 210 and the insulating material of the core member 110 are not limited thereto.

The description of the other configurations overlaps with the above-described descriptions of the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiment, and the composite antenna substrate and the semiconductor package module 300B or 300H according to another exemplary embodiment, and thus Was omitted.

21 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 21, the composite antenna substrate and the semiconductor package of the semiconductor package module 300J according to another exemplary embodiment, as in the above-described composite antenna substrate and semiconductor package module 300C according to another exemplary embodiment. In 100J, the core member 110 may include a first dielectric layer 111a; the first core wiring layer 112a and the second core wiring layer 112b are respectively disposed on opposite surfaces of the first dielectric layer 111a; and the second dielectric layer 111b The first dielectric layer 111a is disposed on the first dielectric layer 111a, the third core wiring layer 112c is disposed on the second dielectric layer 111b, and the third dielectric layer 111c is disposed on the first dielectric layer. The second core wiring layer 112b is covered on the 111a and the fourth core wiring layer 112d is disposed on the third dielectric layer 111c. The first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may be electrically connected to the connection pad 120P. Since the core member 110 can include a large number of core wiring layers 112a, 112b, 112c, and 112d, the connecting member 140 can be further simplified. Therefore, the problem of a decrease in yield due to a defect occurring in the process of forming the connecting member 140 can be suppressed. At the same time, the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may penetrate through the first dielectric layer 111a, the second dielectric layer 111b, and the third dielectric layer respectively. The first core via 113a, the second core via 113b, and the third core via 113c of the electrical layer 111c are electrically connected to each other. Meanwhile, at least one of the first core wiring layer 112a, the second core wiring layer 112b, the third core wiring layer 112c, and the fourth core wiring layer 112d may include a filter pattern electrically connected to the antenna pattern 212aA (in the figure) Not shown). In this case, a material having a high dielectric constant can be used as the insulating material of the antenna member 210 to miniaturize the antenna, and a material having a low dielectric constant can be used as the insulating material of the core member 110 to significantly reduce the filtering. Loss of the device. However, the insulating material of the antenna member 210 and the insulating material of the core member 110 are not limited thereto.

The description of the other configurations overlaps with the above-described descriptions of the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiment, and the composite antenna substrate and the semiconductor package module 300C or 300H according to another exemplary embodiment, and thus Was omitted.

22 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 22, a composite antenna substrate and a semiconductor package module according to another exemplary embodiment of the present disclosure are as in the above-described composite antenna substrate and semiconductor package module 300D according to another exemplary embodiment. In the group 300K antenna substrate 200K, the wiring layer 222 of the wiring member 220 may include the filter pattern 222R. The filter pattern 222R can be electrically connected to the feed line 213F, the feed pattern 222F, and the like. The filter pattern 222R may be a microstrip line, a strip line, or the like, but is not limited thereto. The ground pattern 212bG of the antenna member 210 and/or the ground pattern 222G of the wiring member 220 may provide a ground plane for the filter pattern 222R.

The description of the other configurations overlaps with the above-described descriptions of the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiment, and the composite antenna substrate and the semiconductor package module 300D or 300H according to another exemplary embodiment, and thus Was omitted. Meanwhile, the form of the core member 110 illustrated in the composite antenna substrate and the semiconductor package module 300I or 300J according to another exemplary embodiment may also be applied to the composite antenna substrate and the semiconductor package module according to another exemplary embodiment. 300K.

23 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Referring to FIG. 23, in a composite antenna substrate and a semiconductor package module 300L according to another exemplary embodiment of the present disclosure, the semiconductor wafer 120 may be configured in a face-down form. When the semiconductor wafer 120 is configured in a face-down form, the active surface of the semiconductor wafer 120 can become close to the motherboard with a high heat dissipation effect on the motherboard. The connection member 140 may be disposed on the active surface of the semiconductor wafer 120 , and the back side redistribution layer 132 and the back side via 133 may be disposed on the inactive surface of the semiconductor wafer 120 . In some cases, the metal layer 122 formed on the inactive surface of the semiconductor wafer 120 may be replaced with a die attach film.

The description of other configurations may overlap with the above-described descriptions of the composite antenna substrate and the semiconductor package module 300A according to the exemplary embodiment and the composite antenna substrate and the semiconductor package module 300H according to another exemplary embodiment, and thus Omitted. Meanwhile, the form of the core member 110 illustrated in the composite antenna substrate and the semiconductor package module 300I or 300J according to another exemplary embodiment may also be applied to the composite antenna substrate and the semiconductor package module according to another exemplary embodiment. 300L.

As described above, according to the exemplary embodiments of the present disclosure, a composite antenna substrate and a semiconductor package module can be provided, wherein the signal path between the antenna and the semiconductor wafer can be designed to have the shortest distance to ensure omnidirectional coverage. Characteristics, and the receiving sensitivity of the antenna can be improved.

While the exemplified embodiments have been shown and described, it will be apparent to those skilled in the art that modifications can be made without departing from the scope of the invention as defined by the appended claims And variants.

100A, 2100‧‧‧ Fan-out semiconductor package

100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J‧‧‧ semiconductor packaging

110‧‧‧ core components

110H‧‧‧through hole

111‧‧‧Dielectric layer

111a‧‧‧ dielectric layer

111b‧‧‧ dielectric layer

111c‧‧‧ dielectric layer

112a‧‧‧core wiring layer

112b‧‧‧core wiring layer

112c‧‧‧ core wiring layer

112cR, 222R‧‧‧ filter pattern

112d‧‧‧core wiring layer

113‧‧‧core through hole

113a‧‧‧core through hole

113b‧‧‧core through hole

113c‧‧‧core through hole

115, 122‧‧‧ metal layer

117‧‧‧through through hole

120, 2120, 2220‧‧‧ semiconductor wafer

120B‧‧‧Bumps

120P, 2122, 2222‧‧‧ connection pads

125‧‧‧ Passive components

128‧‧‧ die attach film

130, 2130‧‧‧ Encapsulation

132‧‧‧ Back side wiring layer

133‧‧‧Back side through hole

140, 2140, 2240‧‧‧ connecting members

141, 211, 221, 241, 2141, 2241‧ ‧ insulation

142, 2142‧‧‧Rewiring layer

142a‧‧‧First redistribution layer

143, 213, 223, 243, 2143, 2243‧‧‧ through holes

150, 190, 230, 250, 2150, 2223, 2250‧‧‧ passivation layer

160, 2160, 2260‧‧‧ under bump metal layer

170, 180‧‧‧Electrical connection structure

200A, 200B, 200C, 200D, 200E, 200F, 200G, 200H, 200K‧‧‧ antenna substrates

210‧‧‧Antenna components

210DA‧‧‧ dipole antenna

210PA‧‧‧block antenna

212a‧‧‧First pattern layer

212aA, 212bA‧‧‧ antenna pattern

212aG, 212bG, 222G‧‧‧ grounding pattern

212b‧‧‧Second pattern layer

213F, 223F‧‧‧ feeder

213G‧‧‧ grounding through hole

220‧‧‧Wiring components

222, 242‧‧‧ wiring layers

222F‧‧‧Feed pattern

240‧‧‧Wiring components

300A, 300B, 300C, 300D, 300E, 300F, 300G, 300H, 300I, 300J, 300K‧‧‧ composite antenna substrate and semiconductor package module

1000‧‧‧Electronic devices

1010, 2500‧‧‧ motherboard

1020‧‧‧ wafer related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050‧‧‧ camera module

1060‧‧‧Antenna

1070‧‧‧Display device

1080‧‧‧Battery

1090‧‧‧Signal line

1100‧‧‧Smart Phone

2121, 2221‧‧‧ ontology

2170, 2270‧‧‧ solder balls

2200‧‧‧Fan-in semiconductor package

2242‧‧‧Wiring pattern

2243h‧‧‧through hole

2251‧‧‧ openings

2280‧‧‧ underfill resin

2290‧‧‧Molded materials

2301, 2302‧‧‧Intermediate substrate

I-I'‧‧‧ line

R‧‧‧radiation

The above and other aspects, features and advantages of the present disclosure will be more apparent from the following description. FIG. 1 is a block diagram showing an example of an electronic device system. 2 is a perspective schematic view showing an example of an electronic device. 3A and 3B are schematic cross-sectional views showing a state of a fan-in type semiconductor package before and after packaging. 4 is a schematic cross-sectional view showing a packaging process of a fan-in type semiconductor package. 5 is a schematic cross-sectional view showing a state in which a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device. 6 is a schematic cross-sectional view showing a state in which a fan-in type semiconductor package is embedded in an interposer and finally mounted on a main board of an electronic device. Fig. 7 is a schematic cross-sectional view showing a fan-out type semiconductor package. 8 is a schematic cross-sectional view showing a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device. 9 is a schematic cross-sectional view showing an example of a composite antenna substrate and a semiconductor package module. 10 is a schematic plan view taken along line I-I' of the composite antenna substrate and the semiconductor package module of FIG. 9. 11A and 11B are schematic views showing various examples of the composite antenna substrate of FIG. 9 and the antenna substrate of the semiconductor package module. 12 is a schematic view showing an application of a patch antenna of the composite antenna substrate of FIG. 9 and the antenna substrate of the semiconductor package module. FIG. 13 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 14 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 15 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 16 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 17 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 18 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 19 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 20 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 21 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 22 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module. 23 is a schematic cross-sectional view showing another example of a composite antenna substrate and a semiconductor package module.

Claims (22)

A composite antenna substrate and a semiconductor package module, comprising: a fan-out type semiconductor package, comprising: a semiconductor wafer having an active surface and an inactive surface opposite to the active surface, the active surface being provided with a connection pad, encapsulating And enclosing at least a portion of the semiconductor wafer, and a connecting member disposed on the semiconductor wafer and including a redistribution layer electrically connected to the connection pad; and an antenna substrate comprising: an antenna member and disposed on a wiring member under the antenna member, the antenna member includes an insulating layer, a first pattern layer, a second pattern layer, and a via hole, wherein the first pattern layer is disposed on the first surface of the insulating layer and includes an antenna a pattern, the second pattern layer is disposed on a second surface of the insulating layer opposite to the first surface and includes a ground pattern, the through hole penetrating the insulating layer and electrically connected to the antenna a patterned feed line, and the wiring member includes a wiring layer, the wiring layer including a feed pattern electrically connected to the feed line, wherein the fan-out type semiconductor Package and the antenna substrate coupled to each other, such that the connecting member to the wiring member facing each other. The composite antenna substrate and the semiconductor package module of claim 1, wherein the semiconductor wafer comprises a radio frequency integrated circuit (RFIC). The composite antenna substrate and the semiconductor package module of claim 1, wherein the antenna pattern comprises at least one of a dipole antenna and a bulk antenna. The composite antenna substrate and the semiconductor package module according to claim 3, wherein the block antenna and the feed line connected to the block antenna are grounded through the insulating layer of the antenna member. The through hole is surrounded. The composite antenna substrate and the semiconductor package module of claim 1, wherein the semiconductor wafer is configured in a face-up manner such that the active surface faces the wiring member. The composite antenna substrate and the semiconductor package module according to claim 1, wherein the wiring layer of the wiring member includes a filter pattern electrically connected to the feed line. The composite antenna substrate and the semiconductor package module according to claim 1, wherein the antenna substrate is integrated with the fan-out type semiconductor package. The composite antenna substrate and the semiconductor package module according to claim 7, wherein the connecting member is in contact with the wiring member and integrated with each other. The composite antenna substrate and the semiconductor package module according to claim 8, wherein the redistribution layer of the connection member and the wiring layer of the wiring member are mutually connected by a through hole of the wiring member Electrical connection. The composite antenna substrate and the semiconductor package module according to claim 7, wherein the connecting member is integrated in the wiring member. The composite antenna substrate and the semiconductor package module of claim 10, wherein the fan-out type semiconductor package further comprises a through via, the through via penetrating through the encapsulant and electrically connected to the The wiring layer of the wiring member is described. The composite antenna substrate and the semiconductor package module according to claim 10, wherein the semiconductor wafer is disposed on the wiring member by bumps. The composite antenna substrate and the semiconductor package module according to claim 10, wherein the semiconductor wafer is configured in a face-down manner such that the inactive surface faces the wiring member, and the semiconductor The inactive surface of the wafer is bonded to the wiring member by a die attach film. The composite antenna substrate and the semiconductor package module according to claim 1, wherein the antenna substrate is disposed on the fan-out type semiconductor package, and the antenna substrate and the fan-out type semiconductor package are The electrical connection structures are connected to each other. The composite antenna substrate and the semiconductor package module of claim 1, wherein the fan-out type semiconductor package further includes a core member having a through hole, wherein the semiconductor wafer is disposed in the core member, and The core member includes at least one core wiring layer electrically connected to the connection pad. The composite antenna substrate and the semiconductor package module of claim 15, wherein the fan-out type semiconductor package further comprises a passive component, wherein the passive component is disposed in the through hole adjacent to the semiconductor wafer and The redistribution layer of the connecting member is electrically connected to the connection pad. The composite antenna substrate and the semiconductor package module of claim 15, wherein the core wiring layer of the core member comprises a filter pattern electrically connected to the feed line. The composite antenna substrate and the semiconductor package module of claim 15, wherein the core member comprises a first dielectric layer contacting the connection member, the first core wiring layer, contacting the connection member and embedding In the first dielectric layer, a second core wiring layer is disposed opposite to a second surface of the first dielectric layer on which the first core wiring layer is disposed. a first surface, and a first core via extending through the first dielectric layer and electrically connecting the first core wiring layer and the second core wiring layer to each other, and the first core wiring layer And the second core wiring layer is electrically connected to the connection pad. The composite antenna substrate and the semiconductor package module of claim 18, wherein the core member further includes a second dielectric layer disposed on the first dielectric layer and covering the second core wiring a third core wiring layer disposed on the first surface of the second dielectric layer opposite to the second surface of the second dielectric layer on which the second core wiring layer is disposed, and a second core via, electrically extending the second core wiring layer and the third core wiring layer, and electrically connecting the third core wiring layer to the connection pad. The composite antenna substrate and the semiconductor package module according to claim 15, wherein the core member includes a first dielectric layer, a first core wiring layer and a second core wiring layer, respectively disposed on the first On the opposite surface of the dielectric layer, and the first core via, penetrating the first dielectric layer and electrically connecting the first core wiring layer and the second core wiring layer to each other, and the A core wiring layer and the second core wiring layer are electrically connected to the connection pad. The composite antenna substrate and the semiconductor package module of claim 20, wherein the core member further includes a second dielectric layer disposed on the first dielectric layer and covering the first core wiring a third dielectric layer disposed on the first dielectric layer and covering the second core wiring layer, and a fourth dielectric layer disposed on the third dielectric layer, the second core via Through the second dielectric layer and electrically connecting the first core wiring layer and the third core wiring layer to each other, and a third core via, penetrating the third dielectric layer and The second core wiring layer and the fourth core wiring layer are electrically connected to each other, and the third core wiring layer and the fourth core wiring layer are electrically connected to the connection pad. A composite antenna substrate and a semiconductor package module, comprising: a fan-out type semiconductor package, comprising: a core member having a through hole, a semiconductor wafer disposed in the through hole and having an active surface and a non-optical surface opposite to the active surface An active surface, the active surface is provided with a connection pad, an encapsulation, encapsulating at least a portion of the semiconductor wafer, and a connection member disposed on the semiconductor wafer, the core member including an electrical connection to the Connecting a core wiring layer of the pad and the connection member includes a redistribution layer electrically connected to the connection pad; and the antenna substrate includes: an antenna member, wherein the first pattern layer including the antenna pattern is disposed on the insulation layer, including a second pattern layer of the ground pattern is disposed under the insulating layer, and a through hole is formed in the insulating layer, the through hole penetrating the insulating layer and including a feed line electrically connected to the antenna pattern, and a wiring member disposed under the antenna member and including a wiring layer, the wiring layer including a feed pattern electrically connected to the feed line Wherein the antenna substrate is disposed on the fan-out type semiconductor package, and the antenna substrate and the fan-out type semiconductor package by electrically connecting structure connected to each other.