[go: up one dir, main page]

TWI695474B - 具有抗焊墊剝離結構的半導體裝置以及相關方法 - Google Patents

具有抗焊墊剝離結構的半導體裝置以及相關方法 Download PDF

Info

Publication number
TWI695474B
TWI695474B TW105133467A TW105133467A TWI695474B TW I695474 B TWI695474 B TW I695474B TW 105133467 A TW105133467 A TW 105133467A TW 105133467 A TW105133467 A TW 105133467A TW I695474 B TWI695474 B TW I695474B
Authority
TW
Taiwan
Prior art keywords
pad
tsv
grooves
layer
dielectric layer
Prior art date
Application number
TW105133467A
Other languages
English (en)
Other versions
TW201725679A (zh
Inventor
鄭志楷
謝政傑
黃詩雯
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201725679A publication Critical patent/TW201725679A/zh
Application granted granted Critical
Publication of TWI695474B publication Critical patent/TWI695474B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/022—Protective coating, i.e. protective bond-through coating
    • H01L2224/0221—Shape of the protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05094—Disposition of the additional element of a plurality of vias at the center of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08052—Shape in top view
    • H01L2224/08054—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08057—Shape in side view
    • H01L2224/08059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32113—Disposition the whole layer connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露揭示一種具有一抗銲墊剝離結構之半導體裝置。該半導體裝置包含：一半導體基板，其包含一貫穿基板通路(TSV)；一介電層，其位於該半導體基板上且其中包含複數個凹槽；及一銲墊，其位於該半導體基板上方以覆蓋該介電層之一部分且延伸至該等凹槽；其中該銲墊延伸至該複數個凹槽，且該銲墊與導電層之間的複數個接觸點侷限於該等凹槽中，且當自一俯視觀點觀看時，該等接觸點中之每一者至少部分地在該TSV之一邊界之外。

Description

具有抗焊墊剝離結構的半導體裝置以及相關方法
本揭露係相關於一種半導體裝置，尤指一種具有抗焊墊剝離結構的半導體裝置以及相關方法。
一半導體裝置之導電銲墊用作半導體裝置之內部電路與半導體裝置外側之外部電路之間的連接界面。在現代半導體裝置封裝技術中，在於一晶圓上形成一半導體裝置之後，晶圓必須經切割成晶粒。隨後，實施一晶粒接合程序，後續接著一導線接合程序以將半導體裝置之外部電路及導電銲墊與金屬導線電連接。隨後，實施一模製操作以完成整個半導體裝置封裝程序。 典型導電銲墊通常呈矩形或方形形狀。因此，一高位準應力可尤其在接合程序(或焊接程序)期間在導電銲墊之隅角處發生。該應力可致使導電銲墊剝離且進一步損壞導電銲墊下方之半導體裝置。
本揭露的目的係在於改良銲墊與下方導電層之間的電接合及機械接合之穩定性。 本揭露之某些實施例提供一種具有一抗銲墊剝離結構之半導體裝置。該半導體裝置包含：一半導體基板，其包含一貫穿基板通路(TSV)；一介電層，其位於該半導體基板上且其中包含複數個凹槽；及一銲墊，其位於該半導體基板上方以覆蓋該介電層之一部分且延伸至該等凹槽；其中自一俯視觀點來看，該銲墊完全覆蓋該TSV，且該銲墊之每一邊緣與該等凹槽之最外邊緣之間的一距離大於一所規定長度。
以下揭示內容提供用於實施本揭露之不同構件之諸多不同實施例或實例。下文闡述組件及配置之特定實例以簡化本揭露。當然，此等實例僅係實例且並非意欲係限制性的。舉例而言，在以下闡述中，一第一構件在一第二構件上方或第二構件上之形成可包含其中第一構件與第二構件直接接觸地形成之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間，使得第一構件與第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係出於簡便及清晰之目的，且本身並不指示所論述之各種實施例及/或組態之間的一關係。 此外，為便於闡述，可在本文中使用空間相對術語(諸如，「下面」、「下方」、「下部」、「上方」、「上部」及諸如此類)來闡述一個元件或構件與另一(些)元件或構件之關係，如在各圖中所圖解說明。該等空間相對術語意欲囊括除各圖中所繪示之定向之外的使用或操作中之裝置之不同定向。設備可以其他方式定向(旋轉90度或以其他定向)且因此可同樣地解釋本文中所使用之空間相對描述符。 儘管陳述本揭露之寬廣範疇之數值範圍及參數係近似值，但在特定實例中儘可能精確地報告所陳述之數值。然而，任何數值固有地含有必然由存在於各別測試量測中之標準誤差所引起之誤差。此外，如本文中所使用，術語「約」通常意指在一給定值或範圍的10％、5％、1％或0.5％內。另一選擇係，術語「約」意指在由熟習此項技術者考慮時在一可接受平均值標準誤差內。除在操作/工作實例中之外或除非以其他方式明確規定，本文中所揭示之所有數值範圍、量、值及百分比(諸如材料之數量、持續時間、溫度、操作條件、量之比率及其諸如此類)應在所有實例中被理解為藉由術語「約」而修改。因此，除非指示相反情況，否則本揭露及所附申請專利範圍中所陳述之數值參數係可視需要變化的近似值。最低限度地，每一數值參數應至少根據所報告有效數字的數目且藉由應用普通捨入技術來理解。範圍可在本文中表達為自一個端點至另一端點或在兩個端點之間。本文中所揭示之所有範圍皆包含端點，除非以其他方式規定。 圖1至圖5係用於圖解說明根據本揭露之一例示性實施例之用於製作具有一抗銲墊剝離結構之一半導體裝置之一流程之剖面示意圖。首先，參考圖1，提供其中形成一主動電路結構之一半導體基板100。基板100可包含一塊體矽基板。另一選擇係，基板100可由以下各項構成：一基礎半導體，諸如一結晶結構中之矽或鍺；一複合半導體，諸如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；或其組合。在某些實施例中，基板可包含一絕緣體上矽(SOI)基板。SOI基板係使用氧植入分離(SIMOX)、晶圓接合及/或其他適合方法而製作。 應瞭解，為簡化圖式，僅在圖1中繪示呈一矩形形狀之主動電路結構之導電層102，且並未展示主動電路結構中之所有裝置。熟習此項技術者應確認，主動電路結構包含(舉例而言)複數個半導體組件及複數個半導體金屬互連件。在本揭露中，導電層102表示半導體基板100中之主動電路結構中之一層。導電層102自半導體基板之一頂部表面100a暴露。導電層102提供一表面102a作為用於與半導體基板100外部之一組件進行任何連接之一電接觸端子。在某些實施例中，導電層102處於主動電路結構之一最上部層級中。 導電層102較佳地由銅(Cu)構成且具有約5千埃 (KA)至10 KA之一厚度。導電層102形成於一貫穿基板通路(TSV) 103上方且電連接至該貫穿基板通路(TSV)。TSV 103縱向通過半導體基板100。在此實施例中，TSV由一銅材料或具有優越導電性之其他材料組成。一般而言，一TSV係完全通過一矽晶圓或晶粒之一垂直電連接，亦即一通路。與諸如封裝堆疊(package-on-package)之替代方案相比，一TSV出於至少數個原因係用作用以形成3D封裝及3D積體電路之導線接合及覆晶之一替代方案的一高效能互連技術。該等原因中之一者係由於通路之密度可經設計為高於導線或球柵接合方式之接點密度。此外，該等原因中之一者係藉由通路之連接之導電路徑可經設計為短於導線或球柵接合方式。在含有兩個或兩個以上晶片(積體電路)之一TSV 3D封裝(系統級封裝、晶片堆疊MCM等)中，含有TSV之一基板用於在一封裝中將多個晶片連接在一起。一3D積體電路(3D IC)係藉由堆疊矽晶圓及/或晶粒且將其垂直互連使得其表現為一單個裝置而建立之一單個積體電路。藉由使用TSV技術，3D IC可獲取融入一小「佔用面積」中之大量功能性。堆疊中之不同裝置可係異質的，例如將CMOS邏輯、DRAM及III-V材料組合至一單個IC中。另外，穿過裝置之關鍵電路徑可被大幅度縮短，從而產生一較快操作速度。 TSV 103具有兩個端，其中一端103a自基板100之一外部表面100b暴露。外部表面100b與表面100a相對。所暴露端103a經設計以連接至基板100外部之一組件或電路。另一端103b (其與端103a相對)與導電層102接觸。TSV 103及導電層102形成在基板100內部且穿過基板100之一導電路徑。因此，可達成表面100a上方之任何電路或表面100b下方之任何電路之間的一電通信。以在一3D封裝中形成一互連。 參考圖2，一介電層104藉由任何適合程序形成於半導體基板100及導電層102上。介電層104可由一介電材料構成，諸如二氧化矽、氮化矽、氮氧化矽、高介電係數介電材料、其他適合介電材料及/或其組合。高介電係數介電材料之實例包含HfO2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、二氧化鉿-氧化鋁(HfO2 —A12 O3 )合金、其他適合高介電係數介電材料及/或其組合。然而，此並非本揭露之一限制。 如在圖3中所展示，凹槽106及108形成於介電層104中。凹槽106及108形成於介電層104中。每一凹槽具有實質上沿著TSV 103之縱向方向量測之一深度h。由於在製造操作期間之某些偏差，因此不同凹槽之間可存在一稍微變化。然而，每一凹槽具有足夠較大以暴露表面102a之至少一部分之一對應深度h。TSV 103具有放置於上方之至少一個凹槽(在本實施例中為兩個凹槽)，但該凹槽與下伏TSV部分重疊。將凹槽106作為一實例，凹槽106在TSV 103上方但具有在TSV 103之一側壁103e上方橫向擠出之一表面106a。在另一側上，凹槽106之表面106b上覆於TSV 103上且橫向地在側壁103e之邊界內。凹槽108以類似於凹槽106之一方式定位於TSV 103之一相對側壁103f上方。 結合圖6仍參考圖3，圖6係根據本揭露之一例示性實施例之圖3之一示意性俯視圖。圖3係沿著圖6之線6-6截取之半導體之一剖面示意圖。如在圖6中所展示，凹槽106、108及凹槽110至120係實質上四邊形形狀，且TSV 103之一邊界113係大致圓形。凹槽中之導電層102被暴露(陰影部分)。邊界113以一虛線繪示，此乃因其由導電層102覆蓋。具體而言，凹槽106、108、110及112經形成以與TSV 103之側壁之一部分重疊。凹槽114至120形成於TSV 103之邊界113外部且當自俯視圖觀看時不與TSV 103重疊。因此，經部分重疊凹槽(諸如106或108)及非重疊凹槽(諸如114或120)兩者皆不完全形成於邊界113內部。 形成凹槽106至120之方法係(舉例而言)在圖2之介電層104上形成一經圖案化光阻劑層(未展示)。經圖案化光阻劑層之圖案暴露介電層104之表面之八個實質上四邊形形狀之區域。然後，將經圖案化光阻劑層用作一遮罩來蝕刻所暴露介電層104。蝕刻在導電層102處停止且執行凹槽106至120之成形。 請注意，本揭露並不意欲限於本文中所展示之實例。在某些其他實施例中，圖6之凹槽106至120可呈其他類型之形狀。舉例而言，凹槽106至120之一形狀可係多邊形。在另一實例中，凹槽106至120之一形狀可係圓形或橢圓形。 參考圖4，一銲墊122形成於半導體基板100上方以電連接導電層102。銲墊122覆蓋介電層104之一部分且延伸至凹槽106至120 (由於剖面觀點，因此圖4中僅繪示凹槽106及108)。銲墊122可與導電層102及TSV 103完全或部分地重疊。在此實施例中，當自一俯視觀點觀看時，銲墊122完全覆蓋TSV 103之區。請注意，銲墊122可完全或至少部分地填充凹槽106至120。在此實施例中，舉例而言，銲墊122係一厚銲墊，且銲墊122具有約20 KA (千埃)至約40 KA之一厚度。銲墊122可包含由(舉例而言)鋁(AL)構成之一金屬層。形成銲墊122之方法係(舉例而言)在半導體基板100上方形成一鋁金屬層(未展示)以覆蓋整個介電層104且填滿凹槽106至120。然後，在鋁金屬層上形成一經圖案化光阻劑層(未展示)以使大致在對應導電層102上方之所要位置上方之鋁金屬層暴露。此後，將經圖案化光阻劑層用作一遮罩來蝕刻所暴露鋁金屬層，因此完成成形。 形成於凹槽106至120中之銲墊122之部分提供用以透過凹槽106至120中之銲墊122之部分電連接至導電層102之一接點。銲墊122、導電層102及TSV 103共同形成用以在放置於表面100a上方或表面100b下方之組件之間傳達電通信之一導電路徑。導電路徑係一經堆疊結構且相對位置之配置可根據經堆疊層之間的應力相互作用而係各種。舉例而言，如同在圖4中，銲墊122經配置以不完全與導電層102接觸。銲墊122與導電層102之間的接觸點侷限於凹槽106及108中。除導電銲墊122之外，導電層102之一部分亦與介電層104接觸。換言之，導電層102之頂部表面102a同時與導電銲墊122之導電材料及介電層104之介電材料接觸。 將在本揭露中提及之另一相關性係銲墊122與TSV 103之間的相對位置。即使銲墊122不與TSV 103接觸，然而，自一俯視觀點來看，銲墊122與TSV 103之間的相對位置亦係將在本揭露中考慮之一因素。由於在圖6中凹槽106及108並不完全駐留於TSV 103之邊界內，因此自圖4中之俯視觀點來看，銲墊122與導電層102之間的接觸點亦不完全駐留於TSV 103之邊界內。因此，在某些實施例中，銲墊122在TSV 103上方且完全覆蓋TSV 103，其中一經插置導電層102係銲墊122與TSV 103之間的一連接。然而，銲墊122與導電層102之間的接觸點中沒有一者係完全在TSV 103之邊界內部。換言之，自俯視觀點來看，銲墊122與導電層102之間的一完全內部接觸點係在銲墊122與TSV 103之間的重疊區之外。 參考圖4A，在某些實施例中，可在基板100與介電層104之間區分另一介電層104a。介電層104a可由一介電材料構成，諸如二氧化矽、氮化矽、氮氧化矽、高介電係數或低介電係數介電材料、其他適合介電材料及/或其組合。導電層102由介電層104a環繞。針對某些其他實施例，可為簡單起見省略介電層104與介電層104a之間的分界線。 參考圖5，一保護層124經形成以覆蓋介電層104之表面以及銲墊122之側壁122a及122b之一部分。保護層124可由絕緣材料組成。保護層係由任何適合材料構成，包含二氧化矽、藍寶石、其他適合絕緣材料及/或其組合。一例示性保護層可包含一埋入式氧化物層(BOX)。保護層係藉由任何適合程序形成，諸如植入(例如，SIMOX)、氧化、沈積及/或其他適合程序。請注意，本揭露並不意欲限於本文中所展示之實例。保護層124覆蓋銲墊122之邊緣，因此增強銲墊122之接合，尤其針對銲墊122之隅角之接合。一旦已沈積保護層124，便可在後續操作中實施以下導線接合操作以藉由形成焊接導線(未展示)而將外部電路與銲墊122電連接。後續操作進一步包含一模製操作以完成半導體裝置封裝程序。由於後續導線接合及模製操作為熟習此項技術者所知曉，且本揭露聚焦於導線接合及模製操作之前的操作及結構，因此為簡明起見本文中將不闡述關於後續操作之細節。 應注意，不同於其中整個銲墊觸碰且電連接至內部電路之習用技術，在本揭露之方法中，僅形成於開口中之銲墊之一部分用於將整個銲墊電連接至內部電路。請結合圖7參考圖5。圖7係根據本揭露之一例示性實施例之圖5之一示意性俯視圖。相對而言，圖5係沿著圖7之線7-7截取之半導體之一剖面示意圖。如在圖7中所展示，凹槽中沒有一者位於TSV 103內部，此係由於TSV 103之一中心區域正上方之位置承載由深TSV 103及厚銲墊122之結構誘發之一極其高應力。為防止此一應力影響銲墊122與導電層102之間的整個連接性，本揭露之所有凹槽106至120皆經定位遠離TSV 103之中心區域且至少到達跨越TSV 103之側壁之位置，如在圖7中所展示。 具體而言，自圖7之俯視圖觀看，不多於約50％之一開口面積與TSV 103之佔用面積重疊。在此實施例中，針對凹槽106、108、110及112中之每一者，小於約50％之面積與TSV 103重疊。以此方式，可避免將由深TSV 103及厚銲墊122誘發之高應力轉移至厚銲墊122，其中可有效地避免銲墊122之剝離。 另外，在後續導線接合操作中，銲墊122之隅角一般而言在佈線之後由於向上張力而承載一高應力。高應力有可能沿著銲墊122而自銲墊122之邊緣轉移至凹槽106至120。來自銲墊122之邊緣之應力可致使凹槽106至120中之連接部分自導電層102剝離，並造成銲墊剝離之一高風險(此被稱為脫層)且進一步損壞銲墊122下方之主動電路結構。在此實施例中，揭示厚銲墊122之邊緣與凹槽106至120之最外側之間的一較長距離以解決上文所提及問題。具體而言，厚銲墊122之每一邊緣與凹槽106至120之最外邊緣之間的一距離L大於約2 μm，如在圖7中所展示。在某些實施例中，距離L對厚銲墊122之厚度之一比率可自約0.2至約2。 當在圖7之實例中應用相同拉伸應力測試條件時，可觀察到，與先前技術半導體裝置相比，一鋁銲墊之剝離可在圖7之例示性半導體裝置中顯著減少。因此，可使用圖7之例示性半導體裝置改良鋁銲墊與下伏導電層之間的電接合及機械接合之穩定性。因此，與先前技術半導體裝置相比，圖7之例示性半導體裝置改良了可靠性。 此外，與習用技術之方法相比，本揭露之程序並不複雜。實際上，本揭露中並不需要額外操作或遮罩。如下圖解說明用於防止本揭露之一實施例之銲墊剝離之結構。 圖8至圖12係用於圖解說明根據本揭露之另一實施例之用於製作具有一抗銲墊剝離結構之一半導體裝置之一流程之剖面示意圖。在圖8中，提供其中形成一主動電路結構之一半導體基板800。基板800由與基板100相同或類似之材料組成。應瞭解，為簡化圖式，僅在圖8中繪示呈一矩形形狀之主動電路結構之導電層802，且並未展示主動電路結構中之所有裝置。熟習此項技術者應確認，主動電路結構包含(舉例而言)複數個半導體組件及複數個半導體金屬互連件。在本揭露中，導電層802表示半導體基板800中之主動電路結構中之一層。導電層802自半導體基板之一頂部表面800a暴露。導電層802提供一表面802a作為用於與半導體基板800外部之一組件進行任何連接之一電接觸端子。在某些實施例中，導電層802處於主動電路結構之一最上部層級中。 導電層802較佳地由銅構成且具有約5 KA至10 KA之一厚度。導電層802形成於TSV 801及803上方且電連接至TSV 801及803。TSV 801及803縱向通過半導體基板800。在此實施例中，TSV由具有優越導電性之一銅材料組成。TSV 801之一端801a及TSV 803之一端803a自基板800之一外部表面800b暴露。外部表面800b與表面800a相對。所暴露端801a及803a經設計以連接至基板800外部之一或多個組件或電路。TSV 801之另一端801b及TSV 803之另一端803b (其分別與端801a及803a相對)與導電層802接觸。TSV 801及803以及導電層802形成在基板800內部且穿過基板800之一導電路徑。因此，可達成表面800a上方之任何電路或表面800b下方之任何電路之間的一電通信。以在一3D封裝中形成一互連。 參考圖9，一介電層804藉由任何適合程序形成於半導體基板800及導電層802上。介電層804可由一介電材料構成，諸如二氧化矽、氮化矽、氮氧化矽、高介電係數介電材料、其他適合介電材料及/或其組合。 凹槽806至814形成於介電層804中，如在圖10中所展示。凹槽806、808、812及814形成於介電層804中。每一凹槽具有實質上沿著TSV 801及803之縱向方向量測之一深度h。由於在製造操作期間之某些偏差，因此不同凹槽之間可存在一稍微變化。然而，每一凹槽具有足夠較大以暴露表面802a之至少一部分之一對應深度h。TSV 801及803中之每一者具有放置於上方之至少一個凹槽(在本實施例中針對每一TSV為兩個凹槽)，但該凹槽與對應下伏TSV部分重疊。將凹槽806作為一實例，凹槽806在TSV 801上方但具有在TSV 801之一側壁801e上方橫向擠出之一表面806a。在另一側上，凹槽806之表面806b上覆於TSV 801上且橫向地在側壁801e之邊界內。凹槽808以類似於凹槽806之一方式定位於TSV 801之一相對側壁801f上方。此外，凹槽812及814以類似於凹槽806及808之一方式定位於TSV 803之兩個側壁上方。 結合圖13仍參考圖10，圖13係根據本揭露之另一實施例之圖10之一示意性俯視圖。圖10係沿著圖13之線13-13截取之半導體之一剖面示意圖。如在圖13中所展示，凹槽806至842係實質上四邊形形狀，且TSV 801之一邊界811及TSV 803之一邊界813係大致圓形。凹槽中之導電層802被暴露(陰影部分)。邊界811及813以一虛線繪示，此乃因其由導電層802覆蓋。具體而言，凹槽806、808、812、814、818、826、832及840經形成以與TSV 801及803之側壁之一部分重疊。凹槽810、816、820、822、824、828、830、834、836、838及842形成於TSV 801及803之邊界811及813外部且當自俯視圖觀看時不與TSV 801及803重疊。因此，經部分重疊凹槽(諸如806或812)及非重疊凹槽(諸如816或842)兩者皆不完全形成於邊界811及813內部。 形成凹槽806至842之方法係(舉例而言)藉由在圖9之介電層804上形成一經圖案化光阻劑層(未展示)。經圖案化光阻劑層之圖案暴露介電層804之表面之八個實質上四邊形形狀之區域。然後，將經圖案化光阻劑層用作一遮罩來蝕刻所暴露介電層804。蝕刻在導電層802處停止且執行凹槽806至842之成形。在某些其他實施例中，圖13之凹槽806至842可呈其他類型之形狀。舉例而言，凹槽806至842之一形狀可係多邊形。在另一實例中，凹槽806至842之一形狀可係圓形或橢圓形。 參考圖11，一銲墊844形成於半導體基板800上方以電連接導電層802。銲墊844覆蓋介電層804且延伸至凹槽806至842 (由於剖面觀點因此圖11中僅繪示凹槽806至814)。銲墊844可與導電層802以及TSV 801及803完全或部分地重疊。在此實施例中，當自一俯視觀點觀看時，銲墊844完全覆蓋TSV 801及803之區。請注意，銲墊844可完全或至少部分地填滿凹槽806至814。在此實施例中，舉例而言，銲墊844係一厚銲墊，且銲墊844具有約20 KA至約40 KA之一厚度。銲墊844可包含由(舉例而言)鋁構成之一金屬層。形成銲墊844之方法係(舉例而言)藉由在半導體基板800上方形成一鋁金屬層(未展示)以覆蓋整個介電層804且填滿凹槽806至842。然後，在鋁金屬層上形成一經圖案化光阻劑層(未展示)以使大致在對應導電層802上方之所要位置上方之鋁金屬層暴露。此後，將經圖案化光阻劑層用作一遮罩來蝕刻所暴露鋁金屬層，因此完成成形。 形成於凹槽806至842中之銲墊844之部分提供用以透過凹槽806至842中之銲墊844之部分電連接至導電層802之一功能。 參考圖12，一保護層846經形成以覆蓋介電層804之表面以及銲墊844之側壁844a及844b之一部分。保護層846可由絕緣材料組成。保護層係由任何適合材料構成，包含二氧化矽、藍寶石、其他適合絕緣材料及/或其組合。一例示性保護層可包含一埋入式氧化物層(BOX)。保護層係藉由任何適合程序形成，諸如植入(例如，SIMOX)、氧化、沈積及/或其他適合程序。請注意，本揭露並不意欲限於本文中所展示之實例。保護層846覆蓋銲墊844之邊緣，因此增強銲墊844之接合，尤其針對銲墊844之隅角之接合。一旦已沈積保護層846，便可在後續操作中實施以下導線接合操作以藉由形成焊接導線(未展示)而將外部電路與銲墊844電連接。 請結合圖14參考圖12。圖14係根據本揭露之另一實施例之圖12之一示意性俯視圖。相對而言，圖12係沿著圖14之線14-14截取之半導體之一剖面示意圖。如在圖14中所展示，凹槽中沒有一者位於TSV 801及803內部，此係由於TSV 801及803之一中心區域正上方之位置承載由深TSV 801及803以及厚銲墊844之結構誘發之一極其高應力。為防止此一應力影響銲墊844與導電層802之間的整個連接性，本揭露之所有凹槽806至842皆經定位遠離TSV 801及803之中心區域且至少到達跨越TSV 801及803之側壁之位置，如在圖14中所展示。 類似於圖7，針對凹槽806、808、812、814、818、826、832及840中之每一者，小於約50％之面積與TSV 801及803重疊。以此方式，可避免將由深TSV 801及803以及厚銲墊844誘發之高應力轉移至厚銲墊844，其中可有效地避免銲墊844之剝離。另外，厚銲墊844之邊緣之最外側與凹槽806、814、816、818、820、822、824、826、828、830、832、834、836、838、840及842之最外側之間的一距離L大於約2 μm，如在圖14中所展示。在某些實施例中，距離L對厚銲墊844之厚度之一比率可係自約0.2至約2。 與在圖5中所展示之單個TSV對一個銲墊結構相比，雙TSV對一個銲墊結構具有一額外拉伸應力，該額外拉伸應力形成於位於靠近銲墊844之較寬長度之TSV 801及803之邊緣上方的凹槽(亦即圖14之凹槽818、826、832及840)處之銲墊部分上方。圖15係根據本揭露之再一實施例之圖12之一示意性俯視圖。如自圖15可見，將位於靠近銲墊844之較寬長度之TSV 801及803之邊緣上方之凹槽移除以避免額外拉伸應力之影響。當在圖15之實例中應用相同拉伸應力測試條件時，可觀察到，一鋁銲墊之剝離與圖14相比進一步減少。因此，可在一個銲墊結構放置於一TSV列上方時使用圖15之半導體裝置進一步改良鋁銲墊與下伏導電層之間的電接合及機械接合之穩定性。 本揭露之某些實施例提供一種具有一抗銲墊剝離結構之半導體裝置。該半導體裝置包含：一半導體基板，其包含一貫穿基板通路(TSV)；一介電層，其位於該半導體基板上且其中包含複數個凹槽；及一銲墊，其位於該半導體基板上方以覆蓋該介電層之一部分且延伸至該等凹槽；其中自一俯視觀點來看，該銲墊完全覆蓋該TSV，且該銲墊之每一邊緣與該等凹槽之最外邊緣之間的一距離大於一所規定長度。 前文概述數項實施例之特徵，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解，其可易於將本揭露用作用於設計或修改用於實施相同目的及/或達成本文中所引入之實施例之相同優點之其他程序及結構之一基礎。熟習此項技術者亦應認識到，此等等效構造並不脫離本揭露之精神及範疇，且其可在不脫離本揭露之精神及範疇之情況下在本文中作出各種改變、替代及更改。
100‧‧‧半導體基板/基板100a‧‧‧頂部表面/表面100b‧‧‧外部表面/表面102‧‧‧導電層/經插置導電層102a‧‧‧表面/頂部表面103‧‧‧貫穿基板通路/深貫穿基板通路103a‧‧‧端/所暴露端103b‧‧‧端103e‧‧‧側壁103f‧‧‧相對側壁104‧‧‧介電層/所暴露介電層104a‧‧‧介電層106‧‧‧凹槽/經部分重疊凹槽106a‧‧‧表面106b‧‧‧表面108‧‧‧凹槽/經部分重疊凹槽110‧‧‧凹槽112‧‧‧凹槽113‧‧‧邊界114‧‧‧凹槽/非重疊凹槽116‧‧‧凹槽118‧‧‧凹槽120‧‧‧凹槽/非重疊凹槽122‧‧‧銲墊/導電銲墊/厚銲墊122a‧‧‧側壁122b‧‧‧側壁124‧‧‧保護層800‧‧‧半導體基板/基板800a‧‧‧頂部表面/表面800b‧‧‧外部表面/表面801‧‧‧貫穿基板通路/深貫穿基板通路801a‧‧‧端/所暴露端801b‧‧‧端801e‧‧‧側壁801f‧‧‧相對側壁802‧‧‧導電層802a‧‧‧表面803‧‧‧貫穿基板通路/深貫穿基板通路803a‧‧‧所暴露端/端803b‧‧‧端804‧‧‧介電層/所暴露介電層806‧‧‧凹槽/經部分重疊凹槽806a‧‧‧表面806b‧‧‧表面808‧‧‧凹槽810‧‧‧凹槽811‧‧‧邊界812‧‧‧凹槽/經部分重疊凹槽813‧‧‧邊界814‧‧‧凹槽816‧‧‧凹槽/非重疊凹槽818‧‧‧凹槽820‧‧‧凹槽822‧‧‧凹槽824‧‧‧凹槽826‧‧‧凹槽828‧‧‧凹槽830‧‧‧凹槽832‧‧‧凹槽834‧‧‧凹槽836‧‧‧凹槽838‧‧‧凹槽840‧‧‧凹槽842‧‧‧凹槽/非重疊凹槽844‧‧‧銲墊/厚銲墊844a‧‧‧側壁844b‧‧‧側壁846‧‧‧保護層6-6‧‧‧線7-7‧‧‧線13-13‧‧‧線14-14‧‧‧線h‧‧‧深度/對應深度L‧‧‧距離
當藉助附圖閱讀時，自以下詳細說明最佳地理解本揭露之態樣。應注意，根據工業中之標準實踐，各種構件未按比例繪製。實際上，為論述清晰起見，可任意地增加或減小各種特徵之尺寸。 圖1至圖5係用於圖解說明根據本揭露之一例示性實施例之用於製作具有一抗銲墊剝離結構之一半導體裝置之一流程之剖面示意圖； 圖6係根據本揭露之一例示性實施例之圖3之一示意性俯視圖； 圖7係根據本揭露之一例示性實施例之圖5之一示意性俯視圖； 圖8至圖12係用於圖解說明根據本揭露之另一實施例之用於製作具有一抗銲墊剝離結構之一半導體裝置之一流程之剖面示意圖； 圖13係根據本揭露之另一實施例之圖10之一示意性俯視圖； 圖14係根據本揭露之另一實施例之圖12之一示意性俯視圖；且 圖15係根據本揭露之再一實施例之圖12之一示意性俯視圖。
100‧‧‧半導體基板/基板
102‧‧‧導電層/經插置導電層
103‧‧‧貫穿基板通路/深貫穿基板通路
104‧‧‧介電層/所暴露介電層
106‧‧‧凹槽/經部分重疊凹槽
108‧‧‧凹槽/經部分重疊凹槽
122‧‧‧銲墊/導電銲墊/厚銲墊
122a‧‧‧側壁
122b‧‧‧側壁
124‧‧‧保護層

Claims (10)

  1. 一種具有一抗銲墊剝離結構之半導體裝置，其包括：一半導體基板，其包括包含一導電部分之一貫穿基板通路(TSV)；一介電層，其位於該半導體基板上且在其中包括複數個凹槽；及一銲墊，其位於該半導體基板上方以覆蓋該介電層之一部分且延伸至該等凹槽，其中自一俯視觀點來看，該銲墊完全覆蓋該TSV，且該銲墊之一邊緣與該等凹槽之最外邊緣之間的一距離大於一所規定長度；其中該複數個該等凹槽之一複數部分具有與該TSV之該導電部分之彼平面邊界部分地重疊之平面邊界；且針對與該TSV之該導電部分部分地重疊之該等凹槽，一重疊比率小於該凹槽之一面積之一所規定比率。
  2. 如請求項1之半導體裝置，其進一步包括：一導電層，其位於該TSV上；其中該銲墊穿過該等凹槽延伸至該導電層，使得該銲墊電連接至該TSV。
  3. 如請求項1之半導體裝置，其進一步包括：一保護層，其位於該介電層上以覆蓋該銲墊之一側壁之至少一部分。
  4. 一種半導體裝置，其包括：一半導體基板，其包括一貫穿基板通路(TSV)；一導電層，其位於該TSV上；一介電層，其位於該半導體基板上且在其中界定複數個凹槽，該介電層位於該導電層上方；及一銲墊，其位於該半導體基板上面以覆蓋該介電層之一部分；其中該銲墊延伸至該複數個凹槽中，複數個接點侷限於該銲墊與該導電層之間的該等凹槽中，且當自一俯視觀點觀看時，該等接點中之每一者之一平面輪廓至少部分地與該TSV之彼平面輪廓偏移。
  5. 如請求項4之半導體裝置，其中該銲墊及該導電層包括不同金屬。
  6. 如請求項4之半導體裝置，其中該銲墊透過該等接點及該導電層電連接至該TSV。
  7. 如請求項4之半導體裝置，其中當自該俯視觀點觀看時，該等凹槽之至少一部分與該等TSV部分地重疊。
  8. 一種用於製作具有一抗銲墊剝離結構之一半導體裝置之方法，其包括：提供包括一貫穿基板通路(TSV)之一半導體基板，該TSV包含一導電部分；在該半導體基板上形成一介電層； 在該介電層中形成複數個貫穿孔；及在該半導體基板上面形成一銲墊以覆蓋該介電層之至少一部分且填充該等貫穿孔；其中該銲墊之至少一部分與該TSV重疊，該等貫穿孔中之多於一者具有與該TSV之該導電部分之彼平面輪廓至少部分地重疊之平面輪廓，且自一俯視觀點來看，該等貫穿孔中之每一者之該平面輪廓至少部分地在該TSV之該導電部分之彼平面輪廓之外。
  9. 如請求項8之方法，其進一步包括：在該TSV上形成一導電層；其中該銲墊延伸至該導電層且穿過該介電層，使得該銲墊電連接至該TSV。
  10. 如請求項8之方法，其進一步包括：在該介電層上形成一保護層以覆蓋該銲墊之側壁之至少一部分。
TW105133467A 2015-10-19 2016-10-17 具有抗焊墊剝離結構的半導體裝置以及相關方法 TWI695474B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/886,521 US9711478B2 (en) 2015-10-19 2015-10-19 Semiconductor device with an anti-pad peeling structure and associated method
US14/886,521 2015-10-19

Publications (2)

Publication Number Publication Date
TW201725679A TW201725679A (zh) 2017-07-16
TWI695474B true TWI695474B (zh) 2020-06-01

Family

ID=58524311

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105133467A TWI695474B (zh) 2015-10-19 2016-10-17 具有抗焊墊剝離結構的半導體裝置以及相關方法

Country Status (3)

Country Link
US (1) US9711478B2 (zh)
CN (1) CN106992163A (zh)
TW (1) TWI695474B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11024560B2 (en) * 2019-09-26 2021-06-01 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
CN117995817A (zh) * 2022-10-27 2024-05-07 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060180938A1 (en) * 2005-02-14 2006-08-17 Fujitsu Limited Semiconductor device, method of manufacturing the same, capacitor structure, and method of manufacturing the same
US20100270686A1 (en) * 2006-11-08 2010-10-28 Rohm Co., Ltd. Semiconductor device
US20130181347A1 (en) * 2009-05-08 2013-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump Pad Structure
US20130313722A1 (en) * 2012-05-22 2013-11-28 Samsung Electronics Co., Ltd. Through-silicon via (tsv) semiconductor devices having via pad inlays

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6838769B1 (en) * 1999-12-16 2005-01-04 Agere Systems Inc. Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
US6417087B1 (en) * 1999-12-16 2002-07-09 Agere Systems Guardian Corp. Process for forming a dual damascene bond pad structure over active circuitry
US20030020163A1 (en) * 2001-07-25 2003-01-30 Cheng-Yu Hung Bonding pad structure for copper/low-k dielectric material BEOL process
US6734090B2 (en) * 2002-02-20 2004-05-11 International Business Machines Corporation Method of making an edge seal for a semiconductor device
KR100804392B1 (ko) * 2005-12-02 2008-02-15 주식회사 네패스 반도체 패키지 및 그 제조 방법
US20080122105A1 (en) * 2006-07-13 2008-05-29 Ping-Chang Wu Structure for preventing pad peeling and method of fabricating the same
JP2008305938A (ja) * 2007-06-07 2008-12-18 Toshiba Corp 半導体装置および半導体装置の製造方法
US7622737B2 (en) * 2007-07-11 2009-11-24 International Business Machines Corporation Test structures for electrically detecting back end of the line failures and methods of making and using the same
JP5411434B2 (ja) * 2008-02-22 2014-02-12 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置とその製造方法
US7859122B2 (en) * 2008-04-14 2010-12-28 International Business Machines Corporation Final via structures for bond pad-solder ball interconnections
JP2010045134A (ja) * 2008-08-11 2010-02-25 Shinko Electric Ind Co Ltd 多層配線基板、半導体パッケージ及び製造方法
US8723325B2 (en) * 2009-05-06 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of forming a pad structure having enhanced reliability
US9123544B2 (en) * 2011-10-21 2015-09-01 Infineon Technologies Ag Semiconductor device and method
US8803316B2 (en) * 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8981533B2 (en) * 2012-09-13 2015-03-17 Semiconductor Components Industries, Llc Electronic device including a via and a conductive structure, a process of forming the same, and an interposer
US9349665B2 (en) * 2013-01-18 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging of semiconductor devices
JP6221074B2 (ja) * 2013-03-22 2017-11-01 パナソニックＩｐマネジメント株式会社 半導体装置
TWI508247B (zh) * 2013-07-10 2015-11-11 矽品精密工業股份有限公司 半導體裝置及其製法
US20150228594A1 (en) * 2014-02-13 2015-08-13 Qualcomm Incorporated Via under the interconnect structures for semiconductor devices
US9793243B2 (en) * 2014-08-13 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer(s) on a stacked structure having a via

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060180938A1 (en) * 2005-02-14 2006-08-17 Fujitsu Limited Semiconductor device, method of manufacturing the same, capacitor structure, and method of manufacturing the same
US20100270686A1 (en) * 2006-11-08 2010-10-28 Rohm Co., Ltd. Semiconductor device
US20130181347A1 (en) * 2009-05-08 2013-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump Pad Structure
US20130313722A1 (en) * 2012-05-22 2013-11-28 Samsung Electronics Co., Ltd. Through-silicon via (tsv) semiconductor devices having via pad inlays

Also Published As

Publication number Publication date
US20170110429A1 (en) 2017-04-20
TW201725679A (zh) 2017-07-16
US9711478B2 (en) 2017-07-18
CN106992163A (zh) 2017-07-28

Similar Documents

Publication Publication Date Title
US11600587B2 (en) Pad design for reliability enhancement in packages
TWI746776B (zh) 半導體元件及其製造方法
KR102593085B1 (ko) 반도체 장치, 반도체 패키지 및 이의 제조 방법
US10431614B2 (en) Edge seals for semiconductor packages
TWI466250B (zh) 具有增大焊接接觸面的晶圓級封裝結構及製備方法
US8319329B2 (en) Stacked integrated circuit package having recessed sidewalls
TWI512896B (zh) 半導體晶粒及在基板穿孔上形成內連線結構的方法
US9960119B2 (en) Method and structure for wafer level packaging with large contact area
US10475739B2 (en) Semiconductor device
CN106298715A (zh) 混合接合焊盘结构
KR20180053802A (ko) 기판 구조체 제조 방법 및 이를 이용하여 제조된 기판 구조체
US20240347506A1 (en) Method of forming package structure
TW202310365A (zh) 三維元件結構及其形成方法
KR102704110B1 (ko) 두꺼운 금속층 및 범프를 갖는 반도체 소자들
JP5358089B2 (ja) 半導体装置
KR20230039211A (ko) 반도체 장치
CN104733398A (zh) 一种晶圆三维集成引线工艺
TWI695474B (zh) 具有抗焊墊剝離結構的半導體裝置以及相關方法
TWI497677B (zh) 具有側邊矽貫通電極之半導體結構與其形成方法
TWI753291B (zh) 堆疊式晶片封裝
US12159859B2 (en) Thermal pad, semiconductor chip including the same and method of manufacturing the semiconductor chip
US20240304580A1 (en) Bonding structure and method thereof
TW202230691A (zh) 半導體晶片
KR20240075660A (ko) 반도체 칩, 반도체 패키지 및 반도체 칩 제조 방법
TWI467725B (zh) 三維多晶片堆疊模組及其製造方法