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JP5411434B2 - 半導体装置とその製造方法 - Google Patents

半導体装置とその製造方法 Download PDF

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Publication number
JP5411434B2
JP5411434B2 JP2008041006A JP2008041006A JP5411434B2 JP 5411434 B2 JP5411434 B2 JP 5411434B2 JP 2008041006 A JP2008041006 A JP 2008041006A JP 2008041006 A JP2008041006 A JP 2008041006A JP 5411434 B2 JP5411434 B2 JP 5411434B2
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Prior art keywords
via hole
protective film
pad electrode
island
semiconductor device
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JP2008041006A
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JP2009200281A (ja
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浩史 石関
正文 上原
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Priority to JP2008041006A priority Critical patent/JP5411434B2/ja
Priority to US12/389,857 priority patent/US7915731B2/en
Publication of JP2009200281A publication Critical patent/JP2009200281A/ja
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Publication of JP5411434B2 publication Critical patent/JP5411434B2/ja
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Description

本発明はパッド電極上に突起電極を有した半導体装置とその製造方法に関するものである。
従来、表面実装用の半導体装置においてはパッド電極上にバンプが形成されていた。このような半導体装置のパッド部の平面図を図１０に示し、図１０のＢ−Ｂ線に沿った断面図を図１１に示す。図示の如く、従来のパッド部においては、保護膜開口部５７ａに露出したパッド電極露出部５６ａの下方に不完全埋め込みのビアホール５５を配置することは回避されていた。
その理由は、ビアホール５５の内部に何も存在しない空洞が発生することから、その中に、パッシベーション用の保護膜５７をエッチングする際に生じるケミカル種残渣が残ったり、Ａｕバンプ５９をメッキ法により形成する際のメッキ液が前記空洞に残ったりして、パッド電極露出部５６ａのビアホール５５内部の部分を腐食する等の問題や、ＣＯＧ（Ｃｈｉｐ Ｏｎ Ｇｌａｓｓ）実装時の力のかかり具合によってはビアホール５５周辺の層間絶縁膜５４にクラックを引き起こす等の問題があったからである。
従って、パッド電極露出部５６ａの下方に不完全埋め込みのビアホール５５の配置は避け、パッド電極露出部５６ａに隣接した領域において、１層目メタル配線５１上の層間絶縁膜５４に不完全埋め込みのビアホール５５を形成していた。
また、図１１に示すように、Ａｕバンプ５９を形成した際、Ａｕバンプ周辺部５９ａが保護膜５７のパッド周辺部段差５８に相当する分だけ盛り上がっていた。
なお、この種の半導体装置は特許文献１、２に記載されている。
特開平７−１６１７２２号公報 特開２００３−１７５２１号公報
上述の理由により、パッド電極露出部５６ａの下方に不完全埋め込みのビアホール５５の配置を避けていたため、パッド電極５６の下方の領域の有効活用が図られていないという問題があった。
また従来の構造では、Ａｕバンプ周辺部５９ａが盛り上がっているということから、半導体装置の実装時においてＡｕバンプ５９の下方の半導体基板５１に局所的に大きな力が加わるという問題があった。特に、Ａｕバンプ５９の下方の半導体基板５１中に半導体素子５２が形成されている場合に、この半導体素子５２に大きな力が加わるという問題もあった。
そこで、本発明の半導体装置は、半導体基板と、前記半導体基板上に形成された下層配線と、前記下層配線上に層間絶縁膜を介して形成され、前記層間絶縁膜に形成されたビアホールを通して前記下層配線と接続されたパッド電極と、前記パッド電極上に形成され、前記パッド電極を露出する１つの開口部と、前記開口部の中に島状保護膜とを有する保護膜と、前記パッド電極上に形成され、前記保護膜の開口部を通して前記パッド電極に接続された突起電極と、を有し、前記ビアホールは前記島状保護膜の下方に形成され、かつ前記ビアホールに、前記パッド電極の一部が不完全に埋め込まれていることを特徴とする。
また、本発明の半導体装置の製造方法は、半導体基板上に下層配線を形成する工程と、
前記下層配線を覆う層間絶縁膜を形成する工程と、前記下層配線上の前記層間絶縁膜にビアホールを形成する工程と、前記ビアホールを通して前記下層配線と接続されたパッド電極を形成する工程と、前記パッド電極上に、前記パッド電極を露出する１つの開口部と、前記開口部の中に島状に形成された島状保護膜とを有する保護膜を形成する工程と、前記パッド電極上に形成され、前記保護膜の開口部を通して前記パッド電極に接続された突起電極を形成する工程と、を有し、前記ビアホールは前記島状保護膜の下方に形成され、かつ前記ビアホールに前記パッド電極の一部が不完全に埋め込まれることを特徴とする。
本発明によれば、ビアホールをパッド電極の下に配置することによりパッド電極の下部を有効に活用することができる。これは、ビアホールを島状保護膜の下方に形成することにより、不完全に埋め込まれたビアホール内部が保護膜エッチング用のケミカル種にさらされることが無いこと、またビアホール内のパッド電極と突起電極の直接の接触が無くなったことから、ビアホール部に絡む上述の問題を解決することができたからである。
また、本発明によれば、保護膜の開口部の中に島状保護膜が設けられているので、突起電極の表面を平坦化することができ、半導体装置の実装時に半導体基板に局所的に大きな力が加わるのを防止できる。
本発明の実施形態による半導体装置について、液晶表示装置（以下ＬＣＤ）を駆動するＬＣＤドライバーＩＣを例にとり説明する。図１は、ＬＣＤドライバーＩＣのパッド部の構成を示す平面図であり、図２はそのＡ−Ａ部分の断面図である。
本実施形態によれば、パッド電極７の下方にビアホール１０を形成していることから、パッド部のパターンサイズを小さくでき、半導体基板の有効活用が図れる。なお、ＬＣＤドライバーＩＣは機種により異なるが、約２００〜７００位のパッド電極７を有している為、パッド部のパターンサイズ縮小化の効果は大きい。
図３はＬＣＤパネルブロック図を示している。ＬＣＤドライバーＩＣの種類として、表示信号ドライバーＩＣ２０、走査ドライバーＩＣ２１がある。これらはＬＣＤパネル１９上の格子状に配置された画素に、それぞれ表示信号と走査信号を供給している。表示信号ドライバーＩＣ２０、走査ドライバーＩＣ２１は電源２２からの電力供給を受けている。また、両ドライバーＩＣ２０、２１はコントローラ２３の指示により必要な画素をドライブする。ＬＣＤパネル１９が形成されたガラス板上のパネル電極（不図示）に両ドライバーＩＣ２０，２１のＡｕバンプ１１（突起電極の一例）が直接圧着され、いわゆるＣＯＧ（Ｃｈｉｐ Ｏｎ Ｇｌａｓｓ）構造となっている。
以下、パッド部の詳細な構造、製造方法について、図１、図２を参照しながら説明する。半導体基板１中に通常のＩＣ製造工程である酸化、ホトリソグラフィ、エッチング、イオン注入、熱処理の各工程を経て半導体素子２を形成する。半導体素子２には例えばトランジスタ、抵抗素子等が含まれる。その後、半導体素子２の上の絶縁膜３に半導体素子２と１層目メタル配線５（下層配線の一例）とのコンタクトを取るためのコンタクトホール４が形成される。次に１層目メタルとしてＡｌ等をスパッタ等で付着しホトリソグラフィ処理等で１層目メタル配線５を形成する。
その後、層間絶縁膜６が半導体基板１の全面にＬＰＣＶＤ等で形成される。この場合、表面の平坦化を図るため、並びに一層目メタル配線５とパッド電極７を含めた２層目のメタル配線とのコンタクトをとるための開口、いわゆるビアホール１０の上面を滑らかな形状にする為、層間絶縁膜６は多層構造をとり、最上部はリフロー可能であり、またエッチングスピードの速いＢＰＳＧ等で構成されることが好ましい。
層間絶縁膜６は１μｍ前後の厚みを有し、ホトリソグラフィ処理等を経てビアホール１０が形成される。ビアホール１０の直径はその上面が１μｍ前後になるが、上部が角張らないようウエット＋ドライエッチング方式で行うのが好ましい。その後にスパッタ等で付着された２層目のメタルがビアホール１０内を十分に被覆し、一層目メタル配線５と２層目のメタルからなるパッド電極７等が良好なコンタクトが採れるようにするためである。
しかしながら、このように注意を払った工程を採用した場合にも、図４に示すように完全にビアホール１０内を２層目のメタルで埋め込むことが出来ず、ビアホール１０内にはメタルが存在しない空洞部１３が生じるとともに、ビアホール側面下部のメタルの薄い部分１２が形成されることになる。
その後、シリコン酸化膜、シリコン窒化膜の順に生成された保護膜８を基板全面にプラズマＣＶＤ等により付着した後、ホトリソグラフィ処理等により保護膜開口部８ａの加工を行い、突起電極であるＡｕバンプ１１とのコンタクト面となるパッド電極露出部７ａを形成するが、この場合パッド電極露出部７ａの下方に形成されたビアホール１０の上は島状保護膜９で覆われる。仮にビアホール１０上が島状保護膜９で覆われることなく露出している場合はビアホール１０内の空洞部１３に保護膜エッチング用ケミカルが残るという弊害が生ずる場合がある。
この後、Ａｕメッキの為の前処理としてシード層等としてＣｒ，Ｎｉ，Ａｕ等の多層金属（以下ＵＢＭ）１４が、図６に示す様に島状保護膜９、パッド電極７上にスパッタで付着される。この場合もビアホール１０上が島状保護膜９で覆われていないとスパッタで形成されたＵＢＭ（アンダーバンプメタル）１４の段差被覆性が悪いため、図５に示すようにビアホール１０の空洞部１３の中のパッド電極７上にＵＢＭ１４が充分に形成されない。
次に、ホトリソグラフィ処理等によりＵＢＭ１４にメッキ用のパターンが形成され、またＡｕメッキ用マスクが形成された上で電解メッキによりＡｕバンプ１１が形成される。この場合ビアホール１０上が島状保護膜９で覆われていないと、前述したビアホール１０の空洞部１３のＵＢＭ１４の付着していないパッド電極７上には図７に示すごとくＡｕメッキが形成されず、結果的に空洞部１３にメッキ液が充填された状態でＡｕメッキ層で閉鎖された部分が生ずることになる。
最後にメッキ用マスクを除去することにより本発明の実施形態によるパッド電極７の下に不完全埋め込みのビアホール１０を有する半導体装置が完成する。
仮にビアホール１０上が島状保護膜９で覆われていなかったとすれば前述の保護膜エッチング用のケミカル残渣や空洞部に残ったメッキ液が空洞部１３のパッド電極７と反応し経時的にその部分のパッド電極材料を腐食するという信頼性上大きな問題を引き起こすことになる。
本発明はビアホール１０上を島状保護膜９で覆っているため、空洞部１３が保護膜エッチング用ケミカルに曝されたりＡｕメッキ液に浸ることも無く、前述の様なパッド電極材料腐食という信頼性上の問題の解決を図ることが出来る。
更に、図２、図６のビアホール１０に示すように、ビアホール１０が島状保護膜９で覆われていることから、ビアホール１０の空洞部もスパッタに比べ段差被覆性の良好なプラズマＣＶＤにより生成された島状保護膜９で埋め込まれることになり、ＣＯＧ実装時の力によりビアホール１０内に空洞がある場合に受ける力の偏りもなくなり、ビアホール１０周辺の層間絶縁膜６にクラックが入る危険性も改善される。
この結果、埋め込みの無いビアホール１０をパッド電極露出部７ａの下に形成した場合の弊害を排除しつつパッド部の占める面積の縮小が図られた図１、図２に示される新パッド構造を採用することが可能となる。
次に、本発明のもう１つの利点が発揮される実施形態について以下に説明する。図２のパッド構造を有するドライバー用ＩＣは図９に示す如く、ＣＯＧ用実装装置を使用してＩＣのＡｕバンプ１１部分を下にして、その下にあるパネル電極１５が形成されたＬＣＤパネル用ガラス板１６とパネル電極１５の部分で機械的に圧着される。この場合、図８に示すごとく従来例を示す図１０、図１１同様に保護膜開口部内のパッド電極上が島状保護膜９で覆われていないと、図１１に示す様にＡｕバンプ周辺部５９ａは真ん中より保護膜の厚さである1μｍ前後のパッド周辺部段差５８分だけ高くなることから、ＬＣＤパネル用ガラス板６２に向かってパッド周辺部段差５８部分上のＡｕバンプのみがパネル電極６１と接触することになる。
そうすると、その部分の下に存在する半導体素子５２等に定常時に比し大きな実装時圧力６０を加えることになりデバイス特性劣化の原因となる。パッド全体の面積に対して周辺面積が少なくなればなるほどその力は大きくなる。突起電極はＡｕバンプ５９なので長時間、パッド周辺部のみで力を負担することにはならないが、たとえ短時間といえども微細化の進んだ小さな半導体素子５２への影響は少なくない。
それに対して、本発明では図９に示す如く、パッド電極露出部７ａ上に島状保護膜９を形成している為、全体としてＡｕバンプ１１表面の平坦性が良好になり、実装時圧力１８の分散が可能となり半導体素子２への影響を最小限に留めることができる。
また、島状保護膜９をパッド電極露出部７ａ内に島状に残すのは、仮にその部分にクラックが入った場合でも保護膜８の全体にクラックが拡大するのを防止する為である。この場合、図１に示すごとく複数の島で構成することによりその効果を高めている。複数の島にすればその一つにクラックが入ったとしても、他方の島でＡｕバンプ１１を保持することが出来るので信頼性向上に寄与するからである。
本発明の実施形態による半導体装置の平面図である。 図１のＡ−Ａ線に沿った断面図である。 ＬＣＤパネルブロック図である。 パッド電極形成時のビアホールを示す断面図である。 参考例によるビアホールを示す断面図である。 本発明の実施形態によるビアホールを示す断面図である。 参考例によるビアホールを示す断面図である。 参考例による半導体装置の実装時の圧力のかかり方を示す断面図である。 本発明の実施形態による半導体装置の実装時の圧力のかかり方を示す断面図である。 従来例による半導体装置の平面図である。 従来例による半導体装置の断面図である。
符号の説明
１ 半導体基板 ２ 半導体素子 ３ 絶縁膜 ４ コンタクトホール
５ １層目メタル配線 ６ 層間絶縁膜 ７ パッド電極
７ａ パッド電極露出部 ８ 保護膜 ８ａ 保護膜開口部 ９ 島状保護膜
１０ ビアホール １１ Ａｕバンプ １１ａ Ａｕバンプ周辺部
１２ ビアホール側面下部のメタルの薄い部分 １３ 空洞部 １４ ＵＢＭ
１５ パネル電極 １６ ＬＣＤパネル用ガラス板 １７ パッド周辺部段差
１８ 実装時圧力 １９ ＬＣＤパネル ２０ 信号ドライバーＩＣ
２１ 走査ドライバーＩＣ ２２ 電源 ２３ コントローラ
５１ 半導体基板 ５２ 半導体素子 ５３ １層目メタル配線
５４ 層間絶縁膜 ５５ ビアホール ５６ パッド電極 ５７ 保護膜
５８ パッド周辺部段差 ５９ Ａｕバンプ ５９ａ Ａｕバンプ周辺部
６０ 実装時圧力 ６１ パネル電極 ６２ ＬＣＤパネル用ガラス板

Claims (7)

  1. 半導体基板と、
    前記半導体基板上に形成された下層配線と、
    前記下層配線上に形成された層間絶縁膜と、
    前記層間絶縁膜に形成されたビアホールと、
    前記ビアホール内を不完全に埋め込んで形成されたパッド電極と、
    前記パッド電極上を被覆し該パッド電極の一部を露出する開口部と、該開口部内の前記ビアホールの上方に露出する前記パッド電極部分及びその近傍を被覆する島状保護膜とを有する保護膜と、
    前記開口部に露出する前記パッド電極に接続され、該開口部の外側の前記保護膜上まで延在する突起電極と、を具備し、前記ビアホール内に形成された空洞部が前記島状保護膜によって埋め込まれることを特徴とする半導体装置。
  2. 前記島状保護膜が複数形成されていることを特徴とする請求項１に記載の半導体装置。
  3. 前記ビアホールは前記島状保護膜の下方に複数形成されていることを特徴とする請求項１又は請求項２に記載の半導体装置。
  4. 前記突起電極の下方に半導体素子が形成されていることを特徴とする請求項１乃至３のいずれかに記載の半導体装置。
  5. 前記保護膜はシリコン酸化膜とシリコン窒化膜の２層構造からなる請求項１乃至４のいずれかに記載の半導体装置。
  6. 半導体基板上に下層配線を形成する工程と、
    前記下層配線を覆う層間絶縁膜を形成する工程と、
    前記下層配線上の前記層間絶縁膜にビアホールを形成する工程と、
    前記ビアホールを通して前記下層配線と接続され、該ビアホール内を不完全に埋め込むパッド電極を形成する工程と、
    前記パッド電極上に、前記パッド電極の一部を露出する１つの開口部と、前記開口部の中に島状に形成された島状保護膜とを有する保護膜を形成する工程と、
    前記保護膜の開口部を通して前記パッド電極に接続され、該開口部の外側まで延在する突起電極を形成する工程と、を有し、
    前記ビアホールは前記島状保護膜の下方に形成され、前記ビアホール内に形成された空洞部が前記島状保護膜によって埋め込まれることを特徴とする半導体装置の製造方法。
  7. 前記突起電極はメッキ法により形成されることを特徴とする請求項６に記載の半導体装置の製造方法。
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