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TWI652372B - Semiconductor light-emitting device and the method thereof - Google Patents

Semiconductor light-emitting device and the method thereof Download PDF

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Publication number
TWI652372B
TWI652372B TW104121229A TW104121229A TWI652372B TW I652372 B TWI652372 B TW I652372B TW 104121229 A TW104121229 A TW 104121229A TW 104121229 A TW104121229 A TW 104121229A TW I652372 B TWI652372 B TW I652372B
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Taiwan
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layer
forming
plasma
emitting device
semiconductor light
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TW104121229A
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Chinese (zh)
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TW201700770A (en
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郭倩丞
詹世豪
陳誌濠
劉埃森
彭韋智
許嘉良
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晶元光電股份有限公司
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Priority to TW104121229A priority Critical patent/TWI652372B/en
Priority to US15/198,649 priority patent/US20170002463A1/en
Publication of TW201700770A publication Critical patent/TW201700770A/en
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Publication of TWI652372B publication Critical patent/TWI652372B/en

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Abstract

本發明提供一種形成半導體發光裝置的方法,包括提供一基板,形成一磊晶疊層在該基板上,以一第一沉積模式形成一金屬層在該磊晶層上,以及以一第二沉積模式形成一透明導電層在該金屬層上,其中該第一沉積模式及該第二沉積模式是在同一腔體完成。The present invention provides a method of forming a semiconductor light emitting device comprising providing a substrate, forming an epitaxial layer on the substrate, forming a metal layer on the epitaxial layer in a first deposition mode, and a second deposition The pattern forms a transparent conductive layer on the metal layer, wherein the first deposition mode and the second deposition mode are performed in the same cavity.

Description

半導體發光裝置及其形成方法Semiconductor light emitting device and method of forming same

本發明是有關於一種薄膜沉積用的噴灑頭以及含有噴灑頭的薄膜沉積裝置,且特別是關於多模式的噴灑頭以及一種多模式的薄膜沉積裝置。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a showerhead for film deposition and a film deposition apparatus including a showerhead, and more particularly to a multi-mode showerhead and a multi-mode thin film deposition apparatus.

傳統製作薄膜發光二極體時,可利用分子束磊晶製程(Molecular Beam Epitaxy; MBE)、化學氣相沉積法製程(Chemical Vapor Deposition; CVD)、電漿輔助化學氣相沉積製程(Plasma Enhanced Chemical Vapor Deposition; PECVD)、原子層磊晶製程(Atomic Layer Epitaxy; ALE)或原子層沉積製程(Atomic Layer Deposition; ALD)來生長構成發光二極體所需要的各種薄膜。其中,利用原子層沉積製程以及電漿輔助化學氣相沉積製程來生長構成發光二極體所需要的各種薄膜已經逐漸成為趨勢。In the conventional fabrication of thin film light-emitting diodes, Molecular Beam Epitaxy (MBE), Chemical Vapor Deposition (CVD), and Plasma Enhanced Chemical Vapor Deposition (Plasma Enhanced Chemical) can be used. Vapor Deposition; PECVD), Atomic Layer Epitaxy (ALE) or Atomic Layer Deposition (ALD) to grow various films required to form a light-emitting diode. Among them, the use of an atomic layer deposition process and a plasma-assisted chemical vapor deposition process to grow various films required to form a light-emitting diode has gradually become a trend.

對於現今製程技術而言,原子層沉積製程與電漿輔助化學氣相沉積製程分屬兩個不同製程腔體,不僅設備成本高,在元件轉移(transfer)的過程中,未完成封裝的發光二極體元件會暴露於環境中,造成薄膜品質的降低。For the current process technology, the atomic layer deposition process and the plasma-assisted chemical vapor deposition process belong to two different process chambers, which not only has high equipment cost, but also does not complete the packaged light during the component transfer process. The polar components are exposed to the environment, resulting in a reduction in film quality.

一種形成半導體發光裝置的方法,包括提供一基板,形成一磊晶疊層在該基板上,以一第一沉積模式形成一金屬層在該磊晶層上,以及以一第二沉積模式形成一透明導電層在該金屬層上,其中該第一沉積模式及該第二沉積模式是在同一腔體完成。A method of forming a semiconductor light emitting device, comprising: providing a substrate, forming an epitaxial layer on the substrate, forming a metal layer on the epitaxial layer in a first deposition mode, and forming a second deposition mode A transparent conductive layer is on the metal layer, wherein the first deposition mode and the second deposition mode are completed in the same cavity.

以下將詳細說明本發明實施例之製作與使用方式。然應注意的是,本發明提供許多可供應用的發明概念,其可以多種特定形式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式,非用以限制本發明之範圍。 實施例: The manner of making and using the embodiments of the present invention will be described in detail below. It is to be noted that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Example:

首先,請參照第1圖,其顯示的是根據本發明的薄膜沉積裝置的剖面示意圖。如第1圖所示,根據本發明的薄膜沉積裝置包括一腔體900,其係由一下腔體120、一上腔體110位於上腔體110之上,及一固定裝置130位於下腔體120及上腔體110之間,將下腔體120及上腔體110連結固定,上腔體110包括一上腔體上部件110A及一上腔體下部件110B所組成。腔體900內包括一承載座140,設置於下腔體120內,用以承載一基板200、一設置於承載座140上方且位在上腔體上部件110A內的電漿產生系統,其包括一進氣室180及一電漿氣體分散盤170。此外,根據本發明的薄膜沉積裝置更包括一第一進氣系統300,適於提供一第一薄膜沉積模式時所需的第一製程氣體;及一第二進氣系統400,連接於電漿產生系統,適於提供一第二薄膜沉積模式時所需的第二製程氣體。腔體900內更包括一氣相沉積用的噴灑頭150,其包括一第一階氣盤150A以及一第二階氣盤150B,設置於承載座140與電漿產生系統之間的上腔體下部件110B內。First, referring to Fig. 1, there is shown a schematic cross-sectional view of a thin film deposition apparatus according to the present invention. As shown in FIG. 1, a thin film deposition apparatus according to the present invention includes a cavity 900 which is formed by a lower cavity 120, an upper cavity 110 above the upper cavity 110, and a fixing device 130 located in the lower cavity. Between 120 and the upper cavity 110, the lower cavity 120 and the upper cavity 110 are connected and fixed. The upper cavity 110 comprises an upper cavity upper part 110A and an upper cavity lower part 110B. The cavity 900 includes a carrier 140 disposed in the lower cavity 120 for carrying a substrate 200, a plasma generating system disposed above the carrier 140 and located in the upper cavity upper component 110A, including An inlet chamber 180 and a plasma gas dispersion tray 170. Furthermore, the thin film deposition apparatus according to the present invention further includes a first intake system 300 adapted to provide a first process gas required for a first thin film deposition mode; and a second intake system 400 coupled to the plasma A generating system adapted to provide a second process gas required for a second thin film deposition mode. The cavity 900 further includes a vapor deposition shower head 150, which includes a first-order air disk 150A and a second-order air disk 150B disposed under the upper cavity between the carrier 140 and the plasma generating system. Inside component 110B.

接著,請參照第2A圖,其所顯示的是如第1圖所示的氣相沉積用的噴灑頭150的第一階氣盤150A和第二階氣盤150B的俯視圖。如第2A圖所示,第一階氣盤150A具有相對的第一上表面150A1及第一下表面150A2,且包括複數個具第一孔徑r1(介於3mm以及9mm之間)的第一凹穴151,以第一距離d1彼此互相間隔排列形成於第一上表面150A1,且每一第一凹穴151包括一第一排氣孔153貫穿第一階氣盤150A至第一下表面150A2且具第二孔徑r2(介於0.5mm以及2.5mm之間);以及複數個具第三孔徑r3(介於5mm以及15mm之間)的第二凹穴152,以第二距離d2彼此互相間隔排列形成於第一上表面150A1,且每一第二凹穴152包括一第二排氣孔154貫穿第一階氣盤150A至第一下表面150A2且具第四孔徑r4(介於0.5mm以及2.5mm之間)。其中,第一凹穴151與第二凹穴152彼此交錯排列。Next, referring to FIG. 2A, there is shown a plan view of the first-order air disc 150A and the second-stage air disc 150B of the sprinkler head 150 for vapor deposition as shown in FIG. 1. As shown in FIG. 2A, the first-order air disk 150A has a first first upper surface 150A1 and a first lower surface 150A2, and includes a plurality of first concaves having a first aperture r1 (between 3 mm and 9 mm). The holes 151 are formed on the first upper surface 150A1 at a distance from each other by a first distance d1, and each of the first recesses 151 includes a first exhaust hole 153 extending through the first air plate 150A to the first lower surface 150A2. a second aperture r2 (between 0.5 mm and 2.5 mm); and a plurality of second pockets 152 having a third aperture r3 (between 5 mm and 15 mm) spaced apart from each other by a second distance d2 Formed on the first upper surface 150A1, and each of the second recesses 152 includes a second exhaust hole 154 extending through the first air plate 150A to the first lower surface 150A2 and having a fourth aperture r4 (between 0.5 mm and 2.5) Between mm). Wherein, the first recess 151 and the second recess 152 are staggered with each other.

同樣地,如第2A圖所示,第二階氣盤150B具有相對的一第二上表面150B1及一第二下表面150B2,且第二階氣盤150B包括一第一製程氣體進氣口165,連接於一第一進氣系統300(如第1圖所示),以在第一薄膜沉積模式啟動時導入第一製程氣體。第二階氣盤150B更包括一主氣體供應管160,連接第一製程氣體進氣口165且設置於第二階氣盤150B上、複數個彼此相間隔的分支氣體供應管162,分別與主氣體供應管160連接且設置於第二階氣盤150B上、複數個歧管164形成於主氣體供應管160及分支氣體供應管162上,歧管164以第一距離d1彼此互相間隔排列且貫穿第二階氣盤150B至第二下表面150B2,且每一歧管164分別對應於第一階氣盤150A上的每一第一凹穴151。在第一薄模沉積模式啟動時,在本實施例為原子層沉積模式,第一製程氣體經第一製程氣體進氣口165進入主氣體供應管160以及分支氣體供應管162,然後再經由連接於主氣體供應管160以及分支氣體供應管162的歧管164被導入第一凹穴151內,然後再經由每一第一凹穴151內的第一排氣孔153均勻噴灑於基板200表面。Similarly, as shown in FIG. 2A, the second-order air disk 150B has a second upper surface 150B1 and a second lower surface 150B2, and the second-stage air disk 150B includes a first process gas inlet 165. Connected to a first air intake system 300 (as shown in FIG. 1) to introduce a first process gas when the first thin film deposition mode is activated. The second-stage air disk 150B further includes a main gas supply pipe 160, and is connected to the first process gas inlet 165 and disposed on the second-order gas disk 150B, and a plurality of branch gas supply pipes 162 spaced apart from each other, respectively The gas supply pipe 160 is connected to and disposed on the second-stage gas disk 150B, and a plurality of manifolds 164 are formed on the main gas supply pipe 160 and the branch gas supply pipe 162. The manifolds 164 are spaced apart from each other by a first distance d1 and penetrate through each other. The second order air plate 150B to the second lower surface 150B2, and each manifold 164 corresponds to each of the first pockets 151 on the first order air plate 150A. When the first thin mode deposition mode is activated, in the atomic layer deposition mode in this embodiment, the first process gas enters the main gas supply pipe 160 and the branch gas supply pipe 162 through the first process gas inlet 165, and then is connected. The manifold 164 of the main gas supply pipe 160 and the branch gas supply pipe 162 is introduced into the first pocket 151, and then uniformly sprayed onto the surface of the substrate 200 through the first exhaust hole 153 in each of the first pockets 151.

此外,第二階氣盤第二階氣盤150B更包括複數個第一開口166,形成於主氣體供應管160及分支氣體供應管162以外的區域,第一開口166以第二距離d2彼此互相間隔排列方式貫穿第二上表面150B1及第二下表面150B2,且每一第一開口166分別對應於第一階氣盤150A上的每一第二凹穴152,複數個第一開口166與對應的複數個第二凹穴152組成複數個矩陣排列的電漿產生部,第二薄膜沉積模式啟動時,電漿可在複數個電漿產生部中產生,並經由每一第二凹穴152內的第二排氣孔154將電漿均勻噴灑於基板200表面。In addition, the second-order air disc second-stage air disc 150B further includes a plurality of first openings 166 formed in a region other than the main gas supply pipe 160 and the branch gas supply pipe 162, and the first openings 166 are mutually mutually connected by the second distance d2. The first array of openings 164 extends through the second upper surface 150B1 and the second lower surface 150B2, and each of the first openings 166 corresponds to each of the second recesses 152 on the first stepped disk 150A, and the plurality of first openings 166 correspond to The plurality of second recesses 152 form a plurality of matrix-arrayed plasma generating portions. When the second thin film deposition mode is activated, the plasma may be generated in the plurality of plasma generating portions and passed through each of the second recesses 152. The second exhaust hole 154 uniformly sprays the plasma onto the surface of the substrate 200.

接著,請參照第2B圖,其顯示的是如第2A圖所示的第一階氣盤150A和第二階氣盤150B組合成一氣相沉積用的噴灑頭150,且沿剖面線B-B’所呈現的剖面示意圖。如第2B圖所示,連接於位在第二階氣盤150B上的主氣體供應管160或分支氣體供應管162的各個歧管164乃對準伸入位在第一階氣盤150A上的各個第一凹穴151內,在第一薄膜沉積模式啟動時,使第一製程氣體經由第一排氣孔153均勻噴灑於基板表面;位在第二階氣盤150B上的第一開口166乃對準於位在第一階氣盤150A上的第二凹穴152,且在第二薄膜沉積模式啟動時,使容納於進氣室180(如第1圖所示)內的第二製程氣體190(如第5圖所示),通過如第1圖所示的電漿氣體分散盤170,進入複數個第一開口166與對應的複數個第二凹穴152形成複數個矩陣排列的電漿產生部,在複數個矩陣排列的電漿產生部內產生第二薄膜沉積模式所需的電漿,然後再經由每一第二凹穴152內的第二排氣孔154將電漿均勻噴灑於基板200表面。Next, please refer to FIG. 2B, which shows that the first-order air disc 150A and the second-order air disc 150B as shown in FIG. 2A are combined into a vapor deposition head 150, and along the section line B-B. 'The schematic diagram of the profile presented. As shown in FIG. 2B, the respective manifolds 164 of the main gas supply pipe 160 or the branch gas supply pipe 162 connected to the second-stage gas disk 150B are aligned to extend into the first-order gas disk 150A. In each of the first recesses 151, when the first thin film deposition mode is activated, the first process gas is uniformly sprayed on the substrate surface via the first exhaust hole 153; the first opening 166 located on the second-order air disk 150B is Aligned with the second pocket 152 located on the first-order disc 150A, and when the second thin film deposition mode is activated, the second process gas contained in the inlet chamber 180 (as shown in FIG. 1) is 190 (as shown in FIG. 5), through the plasma gas dispersing disc 170 as shown in FIG. 1, entering a plurality of first openings 166 and corresponding plurality of second recesses 152 to form a plurality of matrix-arranged plasmas a generating portion that generates a plasma required for the second thin film deposition mode in the plasma generating portion of the plurality of matrix arrays, and then uniformly sprays the plasma onto the substrate through the second exhaust hole 154 in each of the second recesses 152 200 surface.

如第2C圖所示,其顯示的是如第1圖所示的電漿氣體分散盤170剖面放大圖,其包括一第一電漿氣體分散盤170A、一第二電漿氣體分散盤170B以及一第三電漿氣體分散盤170C,且利用一石英固定環178夾持固定,其中第一電漿氣體分散盤170A及第三電漿氣體分散盤170C均由絕緣材質(例如石英)所構成。第一電漿氣體分散盤170A包括複數個以第二距離d2互相間隔排列且具第五孔徑r5(介於0.5mm以及2.5mm之間)並貫穿第一電漿氣體分散盤170A的第三排氣孔172;第二電漿氣體分散盤170B,設置於第一電漿氣體分散盤170A下方,且第二電漿氣體分散盤170B包括複數個以第二距離d2互相間隔排列且具第六孔徑r6(介於0.5mm以及5mm之間)並貫穿第二電漿氣體分散盤170B的第四排氣孔174,每一第四排氣孔174對應於每一第三排氣孔172;第三電漿氣體分散盤170C,設置於第二電漿氣體分散盤170B與氣相沉積用的噴灑頭150的第二階氣盤150B之間,第三電漿氣體分散盤170C包括複數個以第二距離d2互相間隔排列並貫穿電漿氣體分散盤的偏壓電極177,其內部設置有具第七孔徑r7的第五排氣孔176。此外,第三排氣孔172的孔徑小於第四排氣孔174的孔徑。As shown in FIG. 2C, there is shown a cross-sectional enlarged view of the plasma gas dispersion disk 170 as shown in FIG. 1, which includes a first plasma gas dispersion disk 170A, a second plasma gas dispersion disk 170B, and A third plasma gas dispersion disk 170C is sandwiched and fixed by a quartz fixing ring 178, wherein the first plasma gas dispersion disk 170A and the third plasma gas dispersion disk 170C are each made of an insulating material such as quartz. The first plasma gas dispersion disk 170A includes a plurality of third rows arranged at a second distance d2 and spaced apart from each other and having a fifth aperture r5 (between 0.5 mm and 2.5 mm) and penetrating through the first plasma gas dispersion disk 170A. The air hole 172; the second plasma gas dispersing disc 170B is disposed under the first plasma gas dispersing disc 170A, and the second plasma gas dispersing disc 170B includes a plurality of second holes d2 spaced apart from each other and having a sixth aperture R6 (between 0.5 mm and 5 mm) and penetrating through the fourth exhaust hole 174 of the second plasma gas dispersing disc 170B, each fourth exhaust hole 174 corresponding to each of the third exhaust holes 172; The plasma gas dispersion disk 170C is disposed between the second plasma gas dispersion disk 170B and the second-order gas disk 150B of the vapor deposition head 150, and the third plasma gas dispersion disk 170C includes a plurality of The distance d2 is spaced apart from each other and penetrates the bias electrode 177 of the plasma gas dispersion disk, and is internally provided with a fifth vent hole 176 having a seventh aperture r7. Further, the diameter of the third exhaust hole 172 is smaller than the diameter of the fourth exhaust hole 174.

接著,請參照第2D圖及第2D’圖。其中,第2D圖顯示的是上述偏壓電極177及電漿產生部的詳細剖面圖,其中偏壓電極177包括一金屬電極177B以及上、下夾持金屬電極177B的電絕緣介電層177A、177C。如第2D圖所示,金屬電極177B外接一電壓源(未顯示),第一階氣盤150A與第二階氣盤150B係由金屬材料製成且接地,且藉由電絕緣介電層177C與金屬電極177B電絕緣隔開,當第二製程氣體經第五排氣孔176進入第一開口166與對應第二凹穴152形成的電漿產生部,外接電壓源的金屬電極177B與接地的第一階氣盤150A與第二階氣盤150B提供的一偏壓將第二製程氣體形成電漿,然後再經由每一第二凹穴152內的第二排氣孔154將電漿均勻噴灑出來。第2D圖所顯示的是一種圓柱形電漿產生部,其電極177B是平面電極。在根據本發明的其他實施例中,可將平面電極之圓柱形電漿產生部修改為同心球形之上、下電極,如第2D’圖所示,形成碗狀之電漿產生部在同電位面上各點至電極177B的距離D相等,相較圓柱形電漿產生部有較均勻之電位分佈,電漿密度亦較均勻,電漿反應產生的熱可均勻分散,不易集中於特定點,且可消除圓柱形底部周圍之死角,減少製程應用時particle之產生。Next, please refer to the 2D and 2D' drawings. 2D is a detailed cross-sectional view of the bias electrode 177 and the plasma generating portion, wherein the bias electrode 177 includes a metal electrode 177B and an electrically insulating dielectric layer 177A for sandwiching the metal electrode 177B. 177C. As shown in FIG. 2D, the metal electrode 177B is externally connected to a voltage source (not shown). The first-order air disk 150A and the second-order air disk 150B are made of a metal material and grounded, and the electrically insulating dielectric layer 177C is used. Electrically insulated from the metal electrode 177B, when the second process gas enters the first opening 166 and the plasma generating portion corresponding to the second recess 152 through the fifth exhaust hole 176, the metal electrode 177B of the external voltage source is grounded A bias voltage provided by the first-order air disk 150A and the second-order air disk 150B forms a plasma for the second process gas, and then uniformly sprays the plasma through the second exhaust hole 154 in each of the second recesses 152. come out. Fig. 2D shows a cylindrical plasma generating portion whose electrode 177B is a planar electrode. In other embodiments according to the present invention, the cylindrical plasma generating portion of the planar electrode may be modified to be a concentric spherical upper and lower electrode, as shown in FIG. 2D', and the bowl-shaped plasma generating portion is formed at the same potential. The distance D from each point on the surface to the electrode 177B is equal, and has a relatively uniform potential distribution compared with the cylindrical plasma generating portion, and the plasma density is relatively uniform, and the heat generated by the plasma reaction can be uniformly dispersed, and it is difficult to concentrate on a specific point. It can eliminate the dead angle around the bottom of the cylinder and reduce the generation of particles during process application.

如第1圖所示,本實施例所揭示的第一進氣系統300,其包括原子層沉積模式所需的第一前驅物氣體供應源310、第二前驅物氣體供應源320、潔淨氣體供應源330、第一製程氣體導管125,其一端連接第二階氣盤150B的第一製程氣體進氣口165,而另一相異端則連接一高壓控制閥350、一第一高壓管315,連接於第一前驅物氣體供應源310與高壓控制閥350之間、一第二高壓管325,連接於第二前驅物氣體供應源320與高壓控制閥350之間、以及一第三高壓管335,連接於潔淨氣體供應源330與高壓控制閥350之間。其中,第一進氣系統300藉由控制高壓控制閥350來切換第一前驅物氣體、第二前驅物氣體或潔淨氣體供應進入第一製程氣體進氣口165。潔淨氣體可選自不會與第一前驅物氣體和第二前區域氣體產生化學反應的惰性氣體,例如氮氣或鈍氣。As shown in FIG. 1, the first air intake system 300 disclosed in this embodiment includes a first precursor gas supply source 310, a second precursor gas supply source 320, and a clean gas supply required for the atomic layer deposition mode. The source 330 and the first process gas conduit 125 are connected at one end to the first process gas inlet 165 of the second-stage gas disk 150B, and the other phase is connected to a high-pressure control valve 350 and a first high-pressure pipe 315. Between the first precursor gas supply source 310 and the high pressure control valve 350, a second high pressure pipe 325, connected between the second precursor gas supply source 320 and the high pressure control valve 350, and a third high pressure pipe 335, It is connected between the clean gas supply source 330 and the high pressure control valve 350. Wherein, the first intake system 300 switches the first precursor gas, the second precursor gas or the clean gas supply into the first process gas inlet 165 by controlling the high pressure control valve 350. The clean gas may be selected from inert gases that do not chemically react with the first precursor gas and the second precursor gas, such as nitrogen or blunt gas.

接著,請參照第3圖,其顯示的是根據本發明以進行第一薄膜沉積模式時,薄膜沉積裝置內的第一製程氣體流動示意圖。如上所述,本發明所揭示的第一薄膜沉積模式是原子層沉積製程,當第一薄膜沉積模式啟動時,第一進氣系統300中的第一前驅物氣體供應源310被開啟,使得第一前驅物氣體自第一高壓管315經高壓控制閥350進入第一製程氣體導管125,然後進入氣相沉積用的噴灑頭150中的第二階氣盤150B的進氣口165,接著再通過主氣體供應管160和分支氣體供應管162,並藉由連接於主氣體供應管160和分支氣體供應管162的歧管164將第一前驅物氣體導入第一凹穴151內,然後再經由每一第一凹穴151內的第一排氣孔153使第一前驅物氣體被均勻噴灑於基板200表面。之後,先關閉第一前驅物氣體供應源310,然後開啟潔淨氣體供應源330,以如上所述的方式將潔淨氣體沿第三高壓管335導入氣相沉積用的噴灑頭150內,藉由抽氣泵500使得殘留的第一前驅物氣體以及潔淨氣體經由抽氣管550被抽出腔體900。接著,先關閉潔淨氣體供應源330,然後開啟第二前驅物氣體供應源320,使第二前驅物氣體供應源320以如上所述的方式將第二前驅物氣體沿第二高壓管325導入氣相沉積用的噴灑頭150內,並噴灑於附著有第一前驅物的基板200表面,使第二前驅物與基板200表面的第一前驅物進行反應,形成所要的薄膜。最後,先關閉第二前驅物氣體供應源320,然後開啟潔淨氣體供應源330,以如上所述的方式將潔淨氣體沿第三高壓管335導入氣相沉積用的噴灑頭150內,並且藉由抽氣泵500使得殘留的第二前驅物氣體以及潔淨氣體經由抽氣管550被抽出腔體900,以上便可完成一個原子層沉積製程循環。上述的原子層沉積製程循環次數,可視所需要的薄膜厚度,多次重複進行。Next, please refer to FIG. 3, which is a schematic view showing the flow of the first process gas in the thin film deposition apparatus when the first thin film deposition mode is performed according to the present invention. As described above, the first thin film deposition mode disclosed by the present invention is an atomic layer deposition process, and when the first thin film deposition mode is activated, the first precursor gas supply source 310 in the first intake system 300 is turned on, so that A precursor gas enters the first process gas conduit 125 from the first high pressure pipe 315 via the high pressure control valve 350, and then enters the gas inlet 165 of the second stage gas disk 150B in the vapor deposition head 150, and then passes through The main gas supply pipe 160 and the branch gas supply pipe 162, and introduce the first precursor gas into the first pocket 151 by the manifold 164 connected to the main gas supply pipe 160 and the branch gas supply pipe 162, and then pass each The first exhaust hole 153 in the first recess 151 causes the first precursor gas to be uniformly sprayed on the surface of the substrate 200. Thereafter, the first precursor gas supply source 310 is turned off, and then the clean gas supply source 330 is turned on, and the clean gas is introduced into the vapor deposition head 150 along the third high pressure pipe 335 in the manner described above, by pumping The air pump 500 causes the residual first precursor gas and the clean gas to be drawn out of the cavity 900 via the exhaust pipe 550. Next, the clean gas supply source 330 is turned off, then the second precursor gas supply source 320 is turned on, and the second precursor gas supply source 320 is introduced into the gas along the second high pressure pipe 325 in the manner described above. The shower head 150 for phase deposition is sprayed on the surface of the substrate 200 to which the first precursor is attached, and the second precursor is reacted with the first precursor on the surface of the substrate 200 to form a desired film. Finally, the second precursor gas supply source 320 is turned off, and then the clean gas supply source 330 is turned on, and the clean gas is introduced into the vapor deposition head 150 for vapor deposition along the third high pressure pipe 335 in the manner as described above. The air pump 500 causes the residual second precursor gas and the clean gas to be drawn out of the cavity 900 via the exhaust pipe 550, and an atomic layer deposition process cycle can be completed. The number of atomic layer deposition process cycles described above can be repeated multiple times depending on the desired film thickness.

如第1圖所示,本實施例所揭示的第二進氣系統400包括一第二製程氣體供應源410、一第四高壓管415以及一高壓控制閥450,藉由控制高壓控制閥450,在第二薄膜沉積模式啟動時將第二製程氣體經由第四高壓管415輸送至進氣室180的第二製程氣體導管115,然後進入進氣室180內。As shown in FIG. 1 , the second intake system 400 disclosed in this embodiment includes a second process gas supply source 410 , a fourth high pressure pipe 415 , and a high pressure control valve 450 . By controlling the high pressure control valve 450 , The second process gas is delivered to the second process gas conduit 115 of the inlet chamber 180 via the fourth high pressure pipe 415 when the second thin film deposition mode is activated, and then enters the intake chamber 180.

接著,請參照第4圖,其顯示的是根據本發明以進行第二薄膜沉積模式時,薄膜沉積裝置內的製程氣體流動示意圖。如上所述,本發明所揭示的第二薄膜沉積模式是電漿輔助化學氣相沉積製程,當第二薄膜沉積模式被啟動時,第二進氣系統400的第二製程氣體供應源被開啟,且第二製程氣體在高壓控制閥450控制下,經由第四高壓管415進入第二製程氣體導管115,並輸入進氣室180內。進入進氣室180的第二製程氣體190先經第三排氣孔172通過第一電漿氣體分散盤170A,然後經過第四排氣孔174通過第二電漿氣體分散盤170B,接著通過第三電漿氣體分散盤170C的第五排氣孔176進入複數個第一開口166與對應的複數個第二凹穴152形成複數個矩陣排列的電漿產生部,在複數個矩陣排列的電漿產生部內產生第二薄膜沉積模式所需的電漿,然後再經由每一第二凹穴152內的第二排氣孔154將電漿均勻噴灑於基板200表面,形成一想要的電漿輔助的化學氣相沉積薄膜。本實施例的第二製程氣體例如包括矽甲烷(silane)、氬氣、氫氣、氧氣其中之一或其組合。Next, please refer to Fig. 4, which is a schematic view showing the flow of process gas in the thin film deposition apparatus in the second thin film deposition mode according to the present invention. As described above, the second thin film deposition mode disclosed by the present invention is a plasma assisted chemical vapor deposition process, and when the second thin film deposition mode is activated, the second process gas supply source of the second intake system 400 is turned on, And the second process gas enters the second process gas conduit 115 via the fourth high pressure pipe 415 under the control of the high pressure control valve 450, and is input into the intake chamber 180. The second process gas 190 entering the intake chamber 180 passes through the first plasma gas dispersion disk 170A through the third exhaust hole 172, and then passes through the second plasma gas dispersion disk 170B through the fourth exhaust hole 174, and then passes through the first The fifth venting opening 176 of the three-plasma gas dispersing disc 170C enters the plurality of first openings 166 and the corresponding plurality of second recesses 152 to form a plurality of matrix-arranged plasma generating portions, and the plasma is arranged in a plurality of matrices. The plasma required for the second thin film deposition mode is generated in the generating portion, and then the plasma is evenly sprayed on the surface of the substrate 200 through the second exhaust hole 154 in each of the second recesses 152 to form a desired plasma assisting. Chemical vapor deposited film. The second process gas of the present embodiment includes, for example, one of silane, argon, hydrogen, oxygen, or a combination thereof.

第5A以及5B圖顯示的是利用本發明一實施例的薄膜沉積裝置以形成半導體元件之各步驟結構示意圖。5A and 5B are views showing the structure of each step of forming a semiconductor element by using the thin film deposition apparatus of one embodiment of the present invention.

請先參照第5A圖,半導體元件之形成方法包括提供一半導體基底10,在半導體基底10上形成一磊晶疊層1000,依序包括一半導體基底10、一緩衝層20、一第一半導體層30、一主動層40、一第二半導體層600。在本實施例中,第一半導體層30包含n型氮化鎵層(n-GaN),主動層40包含氮化鎵系列的材料的疊層,主動層40包含氮化鎵系列的材料所形成之多重量子井結構(Multiple Quantum Well, MQW)用以發出光,第二半導體層600包含p型氮化鎵層(p-GaN)。然後利用本發明的薄膜沉積裝置100,在第二半導體層600表面以第一薄膜沉積模式,例如為前述之原子層沉積法(ALD)沉積一厚度介於1~10nm的金屬層620,其中金屬層620與第二半導體層600為歐姆接觸。此金屬層620之材料可選自銅、箔或鎳。然後利用本發明的薄膜沉積裝置以一第二薄膜沉積模式,例如為前述之電漿輔助化學氣相沉積法(PECVD),於溫度小於攝氏350度C的條件下,在上述的金屬層620表面沉積一厚度介於1~5nm的石墨烯層640,以形成一包含金屬層620與石墨烯層640的複合電流擴散層,其中金屬層620與石墨烯層640為歐姆接觸用以提高橫向電流散佈的能力。Referring to FIG. 5A, a method of forming a semiconductor device includes providing a semiconductor substrate 10, and forming an epitaxial layer 1000 on the semiconductor substrate 10, including a semiconductor substrate 10, a buffer layer 20, and a first semiconductor layer. 30. An active layer 40 and a second semiconductor layer 600. In this embodiment, the first semiconductor layer 30 includes an n-type gallium nitride layer (n-GaN), the active layer 40 includes a stack of materials of a gallium nitride series, and the active layer 40 comprises a material of a gallium nitride series. A multiple quantum well structure (MQW) is used to emit light, and a second semiconductor layer 600 includes a p-type gallium nitride layer (p-GaN). Then, using the thin film deposition apparatus 100 of the present invention, a metal layer 620 having a thickness of 1 to 10 nm is deposited on the surface of the second semiconductor layer 600 in a first thin film deposition mode, for example, the aforementioned atomic layer deposition method (ALD), wherein the metal Layer 620 is in ohmic contact with second semiconductor layer 600. The material of the metal layer 620 can be selected from copper, foil or nickel. Then, using the thin film deposition apparatus of the present invention in a second thin film deposition mode, for example, the aforementioned plasma assisted chemical vapor deposition (PECVD), at a temperature of less than 350 ° C, on the surface of the metal layer 620 described above. A graphene layer 640 having a thickness of 1 to 5 nm is deposited to form a composite current diffusion layer comprising a metal layer 620 and a graphene layer 640, wherein the metal layer 620 is in ohmic contact with the graphene layer 640 for improving lateral current dispersion. Ability.

其次,請參照第5B圖,薄膜沉積利用習知的微影及蝕刻製程,去除部分的金屬層620、石墨烯層640、第二半導體層600以及主動層40,露出第一半導體層30,接著分別在石墨烯層640與露出的第一半導體層30上分別形成第一電極61與第二電極62用以引入外部電流。Next, referring to FIG. 5B, the thin film deposition removes a portion of the metal layer 620, the graphene layer 640, the second semiconductor layer 600, and the active layer 40 by using a conventional lithography and etching process to expose the first semiconductor layer 30, and then A first electrode 61 and a second electrode 62 are respectively formed on the graphene layer 640 and the exposed first semiconductor layer 30 to introduce an external current.

第6A~6C圖顯示的是利用本發明另一實施例的薄膜沉積裝置以形成半導體元件之各步驟結構示意圖。6A to 6C are views showing the structure of each step of forming a semiconductor element by using the thin film deposition apparatus of another embodiment of the present invention.

請先參照第6A圖,半導體元件之形成方法包括提供一半導體基底10,在半導體基底10上形成一磊晶疊層1000,依序包含一緩衝層20、一第一半導體層30、一主動層40以及一第二半導體層600。在本實施例中,第一半導體層30包含n型氮化鎵層(n-GaN),主動層40包含氮化鎵系列的材料所形成之多重量子井結構(Multiple Quantum Well, MQW)用以發出光,第二半導體層600包含p型氮化鎵層(p-GaN)。然後利用本發明的薄膜沉積裝置100在第二半導體層600表面以第一薄膜沉積模式,例如為前述之原子層沉積法(ALD)沉積一厚度介於1~10nm的金屬層620。此金屬層620之材料可選自銅、箔或鎳。Referring to FIG. 6A, the method for forming a semiconductor device includes providing a semiconductor substrate 10, and forming an epitaxial layer 1000 on the semiconductor substrate 10, sequentially including a buffer layer 20, a first semiconductor layer 30, and an active layer. 40 and a second semiconductor layer 600. In this embodiment, the first semiconductor layer 30 includes an n-type gallium nitride layer (n-GaN), and the active layer 40 includes a multiple quantum well structure (MQW) formed by a material of a gallium nitride series. The light is emitted, and the second semiconductor layer 600 includes a p-type gallium nitride layer (p-GaN). Then, a metal layer 620 having a thickness of 1 to 10 nm is deposited on the surface of the second semiconductor layer 600 by a thin film deposition apparatus 100 of the present invention in a first thin film deposition mode, for example, the aforementioned atomic layer deposition (ALD). The material of the metal layer 620 can be selected from copper, foil or nickel.

其次,請參照第6B圖,然後利用本發明的薄膜沉積裝置以一第二薄膜沉積模式,例如為前述之電漿輔助化學氣相沉積法 (PECVD),於溫度約攝氏700~1000度C的條件下,使碳原子穿透金屬層620而到達第二半導體層600的表面,在第二半導體層600與金屬層620之間形成一厚度介於1~5nm的石墨烯層650,其中,石墨烯層650與第二半導體層600形成歐姆接觸。Next, please refer to FIG. 6B, and then use the thin film deposition apparatus of the present invention in a second thin film deposition mode, such as the aforementioned plasma assisted chemical vapor deposition (PECVD), at a temperature of about 700 to 1000 degrees C. Under the condition, the carbon atoms are passed through the metal layer 620 to reach the surface of the second semiconductor layer 600, and a graphene layer 650 having a thickness of 1 to 5 nm is formed between the second semiconductor layer 600 and the metal layer 620, wherein the graphite The olefin layer 650 forms an ohmic contact with the second semiconductor layer 600.

最後,請參照第6C圖,利用蝕刻製程去除金屬層620,露出石墨烯層650以形成一透明的電流擴散層,用以提高橫向電流散佈的能力。接著,利用習知的微影及蝕刻製程,去除部分的石墨烯層650、第二半導體層600以及主動層40,以露出第一半導體層30,接著分別在石墨烯層650與露出的第一半導體層30上分別形成第一電極61與第二電極62用以引入外部電流。Finally, referring to FIG. 6C, the metal layer 620 is removed by an etching process to expose the graphene layer 650 to form a transparent current diffusion layer for improving the lateral current spreading capability. Then, a portion of the graphene layer 650, the second semiconductor layer 600, and the active layer 40 are removed by a conventional lithography and etching process to expose the first semiconductor layer 30, followed by the graphene layer 650 and the exposed first A first electrode 61 and a second electrode 62 are formed on the semiconductor layer 30 to introduce an external current, respectively.

綜上所述,本發明實施例已提供一種適用於原子層沉積及電漿輔助化學氣相沉積的噴灑頭以及一種含有噴灑頭的薄膜沉積裝置,可在同一腔體內視需要切換不同沉積模式的薄膜沉積製程,解決現有無法不同模式的薄膜沉積製程於同一腔體的缺點。In summary, the embodiments of the present invention have provided a shower head suitable for atomic layer deposition and plasma assisted chemical vapor deposition, and a thin film deposition apparatus including a shower head, which can switch between different deposition modes in the same cavity as needed. The thin film deposition process solves the shortcomings of existing thin film deposition processes that cannot be in different modes in the same cavity.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可更動與組合上述各種實施例。While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

10‧‧‧半導體基底10‧‧‧Semiconductor substrate

20‧‧‧緩衝層 20‧‧‧buffer layer

30‧‧‧第一半導體層 30‧‧‧First semiconductor layer

40‧‧‧主動層 40‧‧‧ active layer

600‧‧‧第二半導體層 600‧‧‧Second semiconductor layer

61‧‧‧第一電極 61‧‧‧First electrode

62‧‧‧第二電極 62‧‧‧second electrode

620‧‧‧金屬層 620‧‧‧metal layer

640‧‧‧石墨烯層 640‧‧‧graphene layer

650‧‧‧石墨烯層 650‧‧‧graphene layer

100‧‧‧薄膜沉積裝置 100‧‧‧film deposition apparatus

900‧‧‧腔體 900‧‧‧ cavity

110‧‧‧上腔體 110‧‧‧Upper cavity

110A‧‧‧上腔體上部件 110A‧‧‧Upper upper body parts

110B‧‧‧上腔體下部件 110B‧‧‧Upper upper part

115‧‧‧第二製程氣體導管 115‧‧‧Second process gas conduit

120‧‧‧下腔體 120‧‧‧ lower cavity

125‧‧‧第一製程氣體導管 125‧‧‧First Process Gas Pipeline

130‧‧‧固定裝置 130‧‧‧Fixed devices

140‧‧‧承載座 140‧‧‧Hosting

150‧‧‧氣相沉積用的噴灑頭 150‧‧‧spray head for vapor deposition

150A‧‧‧第一階氣盤 150A‧‧‧first air disc

150B‧‧‧第二階氣盤 150B‧‧‧second order air disc

150A1‧‧‧第一上表面 150A1‧‧‧ first upper surface

150A2‧‧‧第一下表面 150A2‧‧‧ first lower surface

150B1‧‧‧第二上表面 150B1‧‧‧Second upper surface

150B2‧‧‧第二下表面 150B2‧‧‧Second lower surface

151‧‧‧第一凹穴 151‧‧‧ first recess

152‧‧‧第二凹穴 152‧‧‧Second pocket

153‧‧‧第一排氣孔 153‧‧‧First vent

154‧‧‧第二排氣孔 154‧‧‧Second vent

160‧‧‧主氣體供應管 160‧‧‧Main gas supply pipe

162‧‧‧分支氣體供應管 162‧‧‧Branch gas supply pipe

164‧‧‧歧管 164‧‧‧Management

165‧‧‧第一製程氣體進氣口 165‧‧‧First process gas inlet

166‧‧‧第一開口 166‧‧‧ first opening

170‧‧‧電漿氣體分散盤 170‧‧‧ Plasma gas dispersion plate

170A‧‧‧第一電漿氣體分散盤 170A‧‧‧First plasma gas dispersion plate

170B‧‧‧第二電漿氣體分散盤 170B‧‧‧Second plasma gas dispersion plate

170C‧‧‧第三電漿氣體分散盤 170C‧‧‧The third plasma gas dispersion plate

172‧‧‧第三排氣孔 172‧‧‧ third vent

174‧‧‧第四排氣孔 174‧‧‧fourth vent

176‧‧‧第五排氣孔 176‧‧‧ fifth vent

177‧‧‧偏壓電極 177‧‧‧ bias electrode

177A‧‧‧介電層 177A‧‧‧ dielectric layer

177B‧‧‧金屬電極 177B‧‧‧Metal electrode

177C‧‧‧介電層 177C‧‧‧ dielectric layer

178‧‧‧石英固定環 178‧‧‧Quartz retaining ring

180‧‧‧進氣室 180‧‧‧Intake room

190‧‧‧第二製程氣體 190‧‧‧Second process gas

200‧‧‧基板 200‧‧‧Substrate

300‧‧‧第一供氣系統 300‧‧‧First gas supply system

310‧‧‧第一前驅物氣體供應源 310‧‧‧ First source of precursor gas

315‧‧‧第一高壓管 315‧‧‧First high pressure pipe

320‧‧‧第二前驅物氣體供應源 320‧‧‧Second precursor gas supply

325‧‧‧第二高壓管 325‧‧‧Second high pressure tube

330‧‧‧潔淨氣體供應源 330‧‧‧Clean gas supply

335‧‧‧第三高壓管 335‧‧‧ third high pressure pipe

350‧‧‧高壓控制閥 350‧‧‧High pressure control valve

400‧‧‧第二供氣系統 400‧‧‧Second gas supply system

410‧‧‧第二製程氣體供應源 410‧‧‧Second process gas supply

415‧‧‧第四高壓管 415‧‧‧ fourth high pressure pipe

450‧‧‧高壓控制閥 450‧‧‧High pressure control valve

500‧‧‧抽氣泵 500‧‧‧Air pump

550‧‧‧抽氣管 550‧‧‧Exhaust pipe

第1圖顯示的是根據本發明的薄膜沉積裝置的剖面示意圖。Figure 1 is a schematic cross-sectional view showing a thin film deposition apparatus according to the present invention.

第2A圖顯示的是第1圖所示的氣相沉積用的噴灑頭150的第一階氣盤150A和第二階氣盤150B的俯視圖。Fig. 2A is a plan view showing the first-stage air disk 150A and the second-stage air disk 150B of the shower head 150 for vapor deposition shown in Fig. 1.

第2B圖顯示的是第2A圖所示的第一階氣盤150A和第二階氣盤150B組合成氣相沉積用的噴灑頭150且沿剖面線B-B’所呈現的剖面示意圖。Fig. 2B is a schematic cross-sectional view showing the first-stage air disk 150A and the second-order air disk 150B shown in Fig. 2A combined into a vapor deposition head 150 and taken along a section line B-B'.

第2C圖顯示的是第1圖所示的電漿氣體分散盤170剖面放大圖。Fig. 2C is an enlarged cross-sectional view showing the plasma gas dispersion disk 170 shown in Fig. 1.

第2D圖及第2D’圖顯示的是第2C圖之偏壓電極177及電漿產生部的詳細剖面圖示意圖。2D and 2D' are schematic cross-sectional views showing the bias electrode 177 and the plasma generating portion in Fig. 2C.

第3圖顯示的是根據本發明以進行第一薄膜沉積模式時,薄膜沉積裝置內的製程氣體流動示意圖。Figure 3 is a schematic illustration of process gas flow in a thin film deposition apparatus in accordance with the present invention for performing a first thin film deposition mode.

第4圖顯示的是根據本發明以進行第二薄膜沉積模式時,薄膜沉積裝置內的製程氣體流動示意圖。Figure 4 is a schematic illustration of process gas flow in a thin film deposition apparatus in accordance with the present invention for performing a second thin film deposition mode.

第5A及5B圖是利用根據本發明的薄膜沉積裝置,在半導體上形成含石墨烯層及金屬層的複合電流擴散層的剖面製程。5A and 5B are cross-sectional processes for forming a composite current diffusion layer containing a graphene layer and a metal layer on a semiconductor by using the thin film deposition apparatus according to the present invention.

第6A~6C圖是利用本發明的薄膜沉積裝置以形成半導體元件之各步驟結構示意圖。6A to 6C are views showing the structure of each step of forming a semiconductor element by using the thin film deposition apparatus of the present invention.

Claims (10)

一種形成半導體發光裝置的方法,包括: 提供一基板; 形成一磊晶層在該基板上; 以一第一沉積模式形成一金屬層在該磊晶層上;以及 以一第二沉積模式形成一透明導電層在該金屬層上, 其中該第一沉積模式及該第二沉積模式是在同一腔體完成。A method of forming a semiconductor light emitting device, comprising: providing a substrate; forming an epitaxial layer on the substrate; forming a metal layer on the epitaxial layer in a first deposition mode; and forming a second deposition mode A transparent conductive layer is on the metal layer, wherein the first deposition mode and the second deposition mode are completed in the same cavity. 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中該第一沉積模式包括電漿輔助化學氣相沉積法(PECVD)。A method of forming a semiconductor light emitting device according to claim 1, wherein the first deposition mode comprises plasma assisted chemical vapor deposition (PECVD). 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中該第二沉積模式包括原子層沉積法(ALD)。A method of forming a semiconductor light-emitting device according to claim 1, wherein the second deposition mode comprises atomic layer deposition (ALD). 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中該透明導電層不包含非金屬材料。The method of forming a semiconductor light-emitting device according to claim 1, wherein the transparent conductive layer does not comprise a non-metal material. 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中該透明導電層與該金屬層形成歐姆接觸。The method of forming a semiconductor light emitting device according to claim 1, wherein the transparent conductive layer forms an ohmic contact with the metal layer. 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中形成該透明導電層的溫度小於攝氏350度C。The method of forming a semiconductor light-emitting device according to claim 1, wherein the transparent conductive layer is formed at a temperature of less than 350 ° C. 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中該金屬層的厚度小於10 nm。A method of forming a semiconductor light-emitting device according to claim 1, wherein the metal layer has a thickness of less than 10 nm. 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中該透明導電層的厚度小於5 nm。The method of forming a semiconductor light emitting device according to claim 1, wherein the transparent conductive layer has a thickness of less than 5 nm. 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中形成該透明導電層的溫度介於攝氏700~1000度C之間。The method of forming a semiconductor light-emitting device according to claim 1, wherein the transparent conductive layer is formed at a temperature between 700 and 1000 degrees C. 如申請專利範圍第1項所述的形成半導體發光裝置的方法,其中該透明導電層位於該金屬層與該磊晶層之間。The method of forming a semiconductor light emitting device according to claim 1, wherein the transparent conductive layer is located between the metal layer and the epitaxial layer.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030164503A1 (en) 2002-03-04 2003-09-04 United Epitaxy Co., Ltd. High efficiency light emitting diode and method of making the same
US20060001032A1 (en) 2003-03-10 2006-01-05 Sanken Electric Co., Ltd. Light-emitting semiconductor device and method of fabrication
US20140099739A1 (en) 2012-10-10 2014-04-10 Advanced Optoelectronic Technology, Inc. Method for manufacturing light emitting diode chip with electrodes having smooth surfaces

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030164503A1 (en) 2002-03-04 2003-09-04 United Epitaxy Co., Ltd. High efficiency light emitting diode and method of making the same
US20060001032A1 (en) 2003-03-10 2006-01-05 Sanken Electric Co., Ltd. Light-emitting semiconductor device and method of fabrication
US20140099739A1 (en) 2012-10-10 2014-04-10 Advanced Optoelectronic Technology, Inc. Method for manufacturing light emitting diode chip with electrodes having smooth surfaces

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