TWI616238B - Method of sorting? semiconductor devices - Google Patents

Abstract

A semiconductor component classification method includes: defining a plurality of semiconductor components on a carrier device into a plurality of classification regions; providing a selected operation, selecting one of the plurality of classification regions as a first sorting region; providing one Sorting operation, taking out one or a plurality of semiconductor components attached to the first sorting area on the carrying device; and providing a flipping operation to take out another sorting region attached to the plurality of sorting regions on the carrying device One or a plurality of semiconductor components.

Description

Semiconductor component classification method

The present invention relates to a method of classifying semiconductor elements, and more particularly to a method of classifying semiconductor light-emitting elements.

In the semiconductor back-end process, a wafer that is divided into a plurality of semiconductor components is classified by a spotting (Probing) specification, and a plurality of semiconductor components are controlled by a sorting device or a die flipper. Different specifications are selected and packaged and delivered to different customers or warehouses.

When using the sorting device for picking up semiconductor components, although it can be sorted and sorted according to different bins of each semiconductor component, the cost of the device is expensive, the maintenance cost is high, and the picking speed can be singled at a time. Slow, not economical enough; if using flipping equipment for sorting, because the turning equipment can not distinguish and identify semiconductor components of different specifications, only a wide range of semiconductor components with similar specifications can be selected, and there is no way to disperse semiconductors according to different specifications. The components are sequentially selected for single sorting and picking.

A semiconductor component classification method includes: defining a plurality of semiconductor components on a carrier device into a plurality of classification regions; providing a selected operation, selecting one of the classification regions as one a sorting area; providing a sorting operation to take out the semiconductor component attached to the sorting area on the carrying device; and providing a flipping operation to take out the semiconductor component attached to another sorting area on the carrying device.

A semiconductor component classification method includes: providing a selected operation, selecting a first plurality of semiconductor components on a carrier device as a sorting area; providing a sorting operation to extract the first portion attached to the carrier device One or a plurality of semiconductor components of the picking region; and providing a flipping operation to take out a second plurality of semiconductor components attached to the carrier.

10‧‧‧ wafer

10a‧‧‧Semiconductor components

12‧‧‧First adhesive layer

12’‧‧‧Second Adhesive Layer

15‧‧‧First carrier platform

16‧‧‧Second carrier platform

17‧‧‧ computer system

18‧‧‧ picking device

100‧‧‧ sorting equipment

20‧‧‧Base

22‧‧‧First carrying device

23‧‧‧Second carrying device

24‧‧‧ Third carrying device

25‧‧‧First carrier platform

26‧‧‧Second carrying platform

27‧‧‧Airbag

27a‧‧‧ cushion

28‧‧‧heater

29‧‧‧ Pressurizer

Defect Bin‧‧‧Failure Area

200‧‧‧Adhesive equipment

Bin 1‧‧‧ first classification area

Bin 2‧‧‧Second classification area

Bin 3‧‧‧ Third Classification Area

Bin 4‧‧‧ Fourth Classification Area

Bin 5‧‧‧ Fifth Classification Area

Bin 6‧‧‧ sixth classification area

Line 1‧‧‧ first dividing line

Line 2‧‧‧Second divider

Line 3‧‧‧ third dividing line

Fig. 1A is a method of classifying a semiconductor element according to an embodiment of the present invention.

Figure 1B is a schematic view of the sorting apparatus used in the embodiment of the present invention.

1C is a schematic diagram of a flipping device used in the embodiment of the present invention.

Fig. 2A is a diagram showing the photoelectric characteristics of a plurality of semiconductor elements of the present invention.

2B is a schematic view showing the distribution of photoelectric characteristics of a plurality of semiconductor elements of the present invention.

FIG. 2C is a schematic diagram of the classification process and the arrangement manner after the selection according to the embodiment of the present invention.

The 2D figure is a classification process of the embodiment of the present invention and a schematic diagram of the arrangement after the selection.

Fig. 1A is a view showing a method of classifying a semiconductor element according to a first embodiment of the present invention. As shown in FIG. 1A, a semiconductor component classification method includes: defining a plurality of semiconductors on a carrier device The component includes a plurality of classification regions; one of the plurality of classification regions is selected as a sorting region, and the other of the plurality of classification regions is a flip region; and a sorting operation is performed to select a sorting region attached to the carrying device a semiconductor component; and a semiconductor component attached to the flip region on the carrier by a flipping operation.

A semiconductor component is an electronic circuit component that utilizes special electrical characteristics of a semiconductor material to perform a specific function, including a light emitting diode or a transistor. The semiconductor component of the present embodiment refers to a light emitting diode, including a substrate, and a first conductive semiconductor. a layer, a light-emitting layer, and a second conductive semiconductor layer formed on a wafer by MOCVD or MBE epitaxy, formed by a mask to define a mesa position, and then formed by an etching platform The semiconductor structure is formed by coating or wire-bonding, and finally cutting to form a plurality of semiconductor components. The plurality of semiconductor components after cutting are first classified. The specification classification in this embodiment first defines a plurality of classification regions according to photoelectric characteristics by using a spotting operation; and then selects one or more classification regions as a sorting region. In one embodiment, the semiconductor element is dispersively dispersed in the epitaxial wafer due to epitaxial or component processing, or the semiconductor component is destroyed, or may be a semiconductor component having a smaller number of different specifications. The area in which the semiconductor component is located selects it as the sorting area. Next, at least one sorting operation is provided to select the semiconductor component of the sorting area, and the range of the remaining semiconductor elements on the carrying device is the flipping area. Finally, the semiconductor component attached to the flipped region of the carrier device is selected by at least one flipping operation. In one embodiment, the inversion region may be a semiconductor element having a relatively uniform and concentrated photoelectric characteristics and a semiconductor element having a large number of particles. The sorting operation is combined with the flipping operation to achieve the best cost and efficiency considerations for the classification. The definition of the semiconductor component classification area includes the classification according to the customer's requirement specification or the preset specification photoelectricity characteristic range. The photoelectric characteristics include brightness, illuminating wavelength, operating voltage, operating current, or component power.

Fig. 1B is a sorting apparatus 100 used for sorting work in the first embodiment. The sorting apparatus 100 shown in FIG. 1B, in the first embodiment, the sorting apparatus 100 includes a first carrying platform 15, A second carrying platform 16, a picking device 18 and a control system 17. The picking device 18 includes a robot arm. The cut wafer 10 includes a plurality of semiconductor components 10a attached to an adhesive layer 12 and placed on the first carrying platform 15, and the picking device 18 will sort the semiconductor components in the sorting region. The first adhesive layer 12 and the second adhesive layer 12' membrane. The control system 17 is electrically connected to the first carrier platform 15, the second carrier platform 16, and the picking device 18. The sorting device 18 can be controlled according to the specification of the semiconductor component 10a, and the plurality of semiconductor components 10a in the sorting region are A load bearing platform 15 is transferred to the second load bearing platform 16, wherein the second load bearing platform 16 can include a plurality of load bearing platforms, and a plurality of second adhesive layers. When there are multiple sorting regions, the semiconductors of different sorting regions can be Element 10a is transferred to a different carrier platform.

Fig. 1C is a flipping device 200 used in the flipping operation in the first embodiment. As shown in FIG. 1C, the inverting apparatus 200 includes a substrate 20; a heater 28 is disposed on the substrate; a first carrier platform 25 is located on the heater; and a pressurizer 29 is disposed above the substrate 20, wherein the pressurizer The 29 further includes an air bag 27 and a cushion 27a located in the air bag. A first adhesive layer 12 is disposed on the first load-bearing platform 25 of the flipping operation, (adhering and carrying a plurality of semiconductor components 10a remaining after the sorting operation, that is, the semiconductor component 10a of the flipping region. Further to the second carrier platform 26 A second adhesive layer 12' is disposed thereon, and the adhesive surface of the second adhesive layer 12' faces the plurality of semiconductor elements 10a of the first adhesive layer 12 and the inversion region, and is then pressed by the air bag 27 of the pressurizer 29 to adhere the second adhesive layer. The layer 12' is closely adhered to the semiconductor element 10a, and finally heated by the heater 28, so that the second adhesive layer 12' is adhered to the plurality of semiconductor elements 10a. Then, the semiconductor element 10a and the first adhesive layer 12 are attached to each other. The method of force reduces the adhesion between the semiconductor component 10a and the first adhesive layer 12 of the classification region to be taken out. The method comprises applying a degumming solvent (not shown) on the first adhesive layer 12 at the position of the classification region to be taken out. For example, when acetone penetrates the attachment surface of the first adhesive layer 12 and the plurality of semiconductor elements 10a, the adhesion of the plurality of semiconductor elements 10a to the first adhesive layer 12 is weakened, and the film is automatically peeled off. Equipment (not shown) or torn by hand the first adhesive layer 12 and second adhesive The layer 12', a plurality of semiconductor elements 10a coated with the area to be classified of acetone are left in the second adhesive layer 12', and the plurality of semiconductor elements 10a remaining in the uncoated area of acetone are still pasted after being torn. On the adhesive layer 12, the classification is completed. If there are a plurality of inverted regions, the implementation is repeated several times until all the inverted regions are attached to the other adhesive layer, that is, all the flipping operations are completed. The method for reducing the adhesion between the semiconductor element and the adhesive layer can remove the adhesion of the adhesive layer by irradiating UV light or the like in addition to the above-described method of applying the degumming solvent. In the method of irradiating UV light, the adhesive layer may be selected by a UV blue film having a reduced viscosity after UV light irradiation. The advantage of the flipping operation is that the semiconductor components of the large-area classification area can be selected at one time, which is faster than a single sorting operation. For semiconductor components with poor uniformity of photoelectric characteristics, such as blue LEDs, classification can be done by sorting operations with flipping operations.

In the first embodiment, the specification sorting operation can be further matched with a semiconductor component photoelectric characteristic image recognition device for identifying the photoelectric characteristic specifications of the respective semiconductor components 10a. In an embodiment, the photoelectric image recognition device further includes a function of defining a coordinate position, and after identifying a plurality of semiconductor components of different or the same photoelectric characteristic specifications, simultaneously analyzing coordinate positions of different photoelectric characteristics of the semiconductor component, and further Define the classification area. An optical property distribution diagram of a plurality of semiconductor elements arranged in a wafer pattern on a carrier device as shown in FIG. 2A. A plurality of semiconductor elements arranged in a wafer pattern are classified into a plurality of classification regions by a classification operation of photoelectric characteristics. The specification classification operation includes a sorting device using a photoelectric characteristic test instrument or other light-emitting diode photoelectric characteristic image recognizer to generate a photoelectric characteristic distribution map as shown in FIG. 2A. The photoelectric characteristic image discriminator disclosed in the embodiment is different from the color region, represents different photoelectric characteristics, defines a plurality of classification regions, and can also display the positions of the plurality of semiconductor components according to the X-axis and the Y-axis coordinates. In this embodiment, a plurality of classification regions, as shown in FIG. 2A, are represented here by different black and white contrasts, representing light-emitting diode regions of different powers, and are defined as: Defect Bin, Bin 1, Bin 2. Bin 3, Bin 4 multiple classification areas. In this embodiment, Defect Bin is a failure region of the light-emitting diode, Bin 1 is 175-180 mW, Bin 2 is 181-185 mW, Bin 3 is 185-190 mW, and Bin 4 is 190-195 mW. In addition to being defined with different powers, it can be defined by wavelength, brightness, operating voltage, or current.

When the definition is completed, a selected job is provided, and one or a plurality of classification areas are selected, for example, Bin 1, Bin 2, Bin 4, and Defect Bin are selected as the sorting area, and Bin 3 is used as the flipping area. The selection of the sorting area and the inverting area described above can be made using the actual photoelectric characteristic distribution map as a reference for the selected position.

In an embodiment, after the definition is completed, a selected operation is provided, and the most classified area of the selected semiconductor component is a flipped area, and the classified area with a small number of semiconductor element particles is a sorting area, thereby achieving better sorting operation. Cost and efficiency with flipping operations. For the sake of clarity, Figure 2B is taken as a schematic diagram of Figure 2A. As shown in FIG. 2B, a plurality of classification regions including Defect Bin, Bin 1, Bin 2, Bin 3, and Bin 4, wherein Bin 1 is the classification region with the largest number, and thus is selected as a flip region; Bin 2, Bin 3. Bin 4 and Defect Bin are selected as the sorting area.

In an embodiment, after the definition is completed, a selected job is provided, a plurality of sorting regions are selected such that the plurality of flipping regions are not adjacent to each other, and then the plurality of semiconductor components of the sorting region are first sorted by the sorting operation, so that The plurality of flipping regions are not adjacent to each other, and then the flipping operations are respectively performed for the individual flipping regions to solve the defect that the conventional flipping operation cannot recognize the boundary between the regions. Referring to FIG. 2B, non-adjacent Bin 1 and Bin 3 are selected as the inversion regions, and the remaining Bin 2, Bin 4 and Defect Bin are the sorting regions. After bin 2, Bin 4 and Defect Bin first pick out the semiconductor components of these classification areas via the sorting operation, Bin 1 and Bin 3 can visually recognize Bin 1 and Bin by the space left by the sorting area. At the boundary of 3, Bin 1 and Bin 3 are respectively arranged to be arranged on different carrying devices by flipping operations.

In another embodiment, the boundaries of the various classification regions are defined by Line 1, Line 2, and Line 3 dividers. Referring to Figure 2B, Bin 1~Bin 4 is selected as the flip area, and the selected line is located. The plurality of semiconductor elements adjacent to the 1~Line 3 dividing line are sorting areas. After the sorting operation is completed, spaces are left between the plurality of flipping areas, so that the inverting areas are not adjacent to each other.

FIG. 2C is a schematic diagram of a classification process and an arrangement manner after selection according to an embodiment of the present invention. In this embodiment, as shown in FIG. 2C, a plurality of semiconductor elements arranged in a wafer are carried on the first carrier device 22. The first step is defined as Bin 1~6 classification according to the method described in the previous embodiment. region. Then, the classification area Bin 1 of the most semiconductor components is selected as the inversion area, and the other classification areas Bin 2 to 6 are the sorting areas, and the data selected as the sorting area is input into the sorting device, for example, 176-180 mW, 181~ Luminance data of Bin 2~6 such as 185mW, 186~190mW, 191~195mW, 196~200mW and 201~205mW. The second step puts a plurality of semiconductor components on the first carrier device 22 into the sorting device, and the sorting device performs a plurality of sorting operations according to the previously input sorting region data. After the plurality of sorting operations, the semiconductor components of the sorting regions Bin 2 to 6 are respectively selected by the sorting operation to the plurality of second carrying devices 23, and the remaining sorting region Bin 1 is also the semiconductor component of the flipping region. It remains on the first carrier 22. The fourth step puts the semiconductor component of the flip region Bin 1 into the flip device for the flipping operation. After the fifth step, the semiconductor element of the flip region Bin 1 is flipped over from the first carrier device 22 to the third carrier device 24 via the flipping operation. The semiconductor elements of the flip region Bin 1 are arranged on the third carrier device 24 according to the irregularity of the original flip region, and the semiconductor components of the sorting regions Bin 2 to 6 are sequentially arranged in the second carrier device 23 in the sorting operation. In the above, a plurality of semiconductor components are sent to the warehouse for storage or delivery to the customer together with the third carrier device 24. In another embodiment, after the inversion area Bin1 is turned over, the arrangement shape on the third carrying device 24 may be irregular or scattered; after the sorting area Bin 2~6 is sorted, in the first The arrangement shape on the two carrying devices 23 may be square or circular.

FIG. 2D is a schematic diagram of a classification process and an arrangement manner after selection according to an embodiment of the present invention. In this embodiment, as shown in FIG. 2D, a plurality of semiconductor elements arranged in a wafer shape are first carried on the first carrier device 22, and are defined as Bin 1 to 3 classification regions according to the method described in the previous embodiment. . Then, the classification areas Bin 1, Bin 2, and Bin 3 are selected as three inversion areas, and the plurality of semiconductor elements adjacent to the Line 1, Line 2, and Line 3 separation lines are three sorting areas Bin 4, Bin 5, and Bin 6, and input the sorting area data into the sorting device. The second step places the semiconductor component in a sorting device for sorting operations. The third step, after a plurality of sorting operations, the sorting areas Bin 4, Bin 5, and Bin 6 of the plurality of semiconductor elements adjacent to the Line 1, Line 2, and Line 3 separation lines are respectively sorted by the sorting operation. The plurality of second carrying devices 23 are arranged in a square shape. At this time, the remaining plurality of flipping regions Bin1, Bin 2, and Bin 3 remain on the first carrying device 22. In the fourth step, the remaining plurality of inversion areas Bin 1, Bin 2, and Bin 3 are placed in a flipping device to perform three inversion operations in sequence, and the batch is attached to a plurality of third carrying devices 24, and the method of attaching and attaching includes heating. , pressurize, or illuminate. After the flipping operation, the plurality of flipping regions Bin1, Bin2, and Bin3 semiconductor components are respectively placed on the carrying device 24 according to the irregular arrangement originally arranged on the carrying device 22, and finally sent to the warehouse for storage. Or delivery to customers. In another embodiment, after the flipping operation, the arrangement of the plurality of flip regions Bin 1, Bin 2, and Bin 3 semiconductor elements on the carrying device may be irregular or scatter; Line 1, Line 2, and The plurality of semiconductor component sorting areas Bin 4, Bin 5, and Bin 6 adjacent to the Line 3 dividing line may be square or circular in shape after being sorted.

The examples of the invention are intended to be illustrative only and not to limit the scope of the invention. Any changes or modifications of the present invention to those skilled in the art will be made without departing from the spirit and scope of the invention.

Claims (10)

A semiconductor component classification method includes: defining a plurality of semiconductor components on a carrier device into a plurality of classification regions, wherein the plurality of classification regions respectively comprise a plurality of the plurality of semiconductor components; providing a selected operation from the plurality of classifications Selecting a first sorting area, a first inverting area and a second inverting area in the area, the first sorting area is located between the first inverting area and the second inverting area; providing a sorting operation, taking out The semiconductor elements located in the first sorting region are separated from the second inversion region by a gap from a top view; and after the sorting operation, A flipping operation flips one or a plurality of semiconductor elements of the semiconductor elements of the first flip region or the second flip region. The semiconductor component classification method according to claim 1, wherein the selected operation further comprises selecting a second sorting area and a plurality of flipping areas from the plurality of sorting areas. The method of classifying a semiconductor device according to claim 1, wherein the defining manner comprises classifying according to photoelectric characteristics of the plurality of semiconductor elements, wherein the photoelectric characteristics comprise brightness, illuminating wavelength, operating voltage, current, or power. The method of classifying a semiconductor device according to claim 3, wherein the photoelectric characteristics of the semiconductor elements of the first inversion region or the second inversion region are relatively uniform and concentrated. The semiconductor component classification method of claim 2, wherein the sorting operation comprises taking out the semiconductor components located in the second sorting region, so that the flip regions are viewed from a top view. A gap is separated. The method of classifying a semiconductor device according to claim 5, wherein the step of selecting the second sorting region comprises defining a boundary of the plurality of flip regions as a dividing line, and selecting a plurality of semiconductors adjacent to the dividing line. The component is the second sorting area. The method of classifying a semiconductor device according to claim 1, wherein the number of the semiconductor elements included in the first inversion region is greater than the semiconductors included in the first sorting region and/or the second inversion region. The number of components. The method of classifying a semiconductor component according to claim 1, wherein the sorting operation comprises: using a sorting device to affix the semiconductor components of the first sorting region to a second carrying device; The method of splicing includes heating, pressurizing, or illuminating, and/or one of the semiconductor elements of the first sorting region being attached to the second carrier includes an square or a circular shape. The method of classifying a semiconductor device according to claim 1, wherein the inverting operation comprises transferring the semiconductor elements of the first inversion region to a third carrier device using an inverting device. A method of classifying a semiconductor component, comprising: providing a selected operation, comprising: selecting a first plurality of semiconductor components on a first carrier device as a sorting region; and selecting a second group of the first carrier device The semiconductor component is a first inversion region; providing a sorting operation to take the first plurality of semiconductor components located in the sorting region to a second carrier; and providing a flip after the sorting operation Working to move the second plurality of semiconductor components on the first carrier to the third carrier device; wherein the second plurality of semiconductor components is greater than the first plurality of semiconductor components The number.