TWI480657B - Thin film transistor array substrate and manufacturing method thereof - Google Patents

Description

Thin film transistor array substrate and manufacturing method thereof

The present invention relates to a liquid crystal display device (LCD).

Generally, the transmittance of a liquid crystal having dielectric anisotropy in a liquid crystal display device is controlled by an electric field to display an image. The liquid crystal display device is generally formed by combining a color filter array substrate with a thin film transistor array substrate and including a liquid crystal layer therebetween.

Recently, several new modes of liquid crystal display devices (LCDs) are being developed to solve the narrow viewing angle of liquid crystal display devices (LCDs) of the prior art. A liquid crystal display device (LCD) having a wide viewing angle can be classified into an In-Plane Switching (IPS), an Optically Compensated Birefringence (OCB) mode, and a Fringe Field Switching (FFS). ) mode, or other mode.

Among liquid crystal display devices (LCDs) having a wide viewing angle, a planar switching (IPS) mode liquid crystal display device allows a pixel electrode and a common electrode to be arranged on the same substrate such that a horizontal electric field is induced to the two electrodes. between. Also, the major axes of the liquid crystal molecules are arranged in a horizontal direction with respect to one of the substrates. Therefore, the liquid crystal display device of the planar switching (IPS) mode has a wider viewing angle than the twisted nematic (TN) mode liquid crystal display device of the prior art.

"FIG. 1" is a schematic diagram of a pixel structure in a liquid crystal display device of a planar switching (IPS) mode of the prior art. "Picture 2" is a cross-sectional view of the pixel structure along the I-I' line of "Fig. 1".

Referring to "Fig. 1" and "Fig. 2", a gate line 1 and a data line 5 intersect each other to define a pixel area. A thin film transistor TFT used as a switching unit is located at the intersection of the gate line 1 and the data line 5.

Above the pixel region, a first common line 3 opposite to the gate line 1 intersects the data line 5, and the first common electrode 3a extends from the first common line 3 and is parallel to the data line 5, and A common electrode 3a is formed on both sides of the pixel area.

The gate line 1 includes a gate 1a having a widened width. A first storage electrode 6 is adjacent to the gate 1a. The first storage electrode 6 and the first common electrode 3a are formed as a single body.

Moreover, a second common line 13 electrically connected to the first common line 3 is formed above the first common line 3. The second common electrode 13a extends from the second common line 13 toward the pixel region. Further, the third common electrode 13b overlapping the portion of the first common electrode 3a extends from the second common line 13.

The second common electrode 13a and the pixel electrode 7a are alternately arranged in the pixel region. The pixel electrode 7a extends from a second storage electrode 7 overlapping the first storage electrode 6.

"Fig. 2" shows a cross-sectional view of the I-I' line in a region along the data line 5, and in "Fig. 2", a gate insulating film 12 is formed on the base substrate 10. The data line 5 is formed on the gate insulating film 12. The first common electrode 3a arranged on both sides of the data line 5 is formed on the base substrate 10. The third common electrode 13b is formed over a protective (or passivation) film 19 and overlaps the first common electrode 3a portion.

The color filter array substrate includes a black matrix 21 opposite to the data line. The black matrix 21 is formed on a top substrate 20. A red (R) filter layer 25a and a green (G) filter layer 25b are formed on both sides of the black matrix 21. 〞29〞 represents an overlay.

Such a conventional planar switching (IPS) mode liquid crystal display device forces the width L1 of the black matrix 21 to be wider (for example, at least 36 micrometers (μm)) to prevent generation through the backlight unit and around the pixel region. Light from the edges of the transmitted light leaks. More specifically, the black matrix 21 is formed to reach one edge of the first common electrode 3a so as to interrupt the passage of light between the data line 5 and the first common electrode 3a in a direction inclined by at least a constant angle with respect to a vertical line. . For this reason, the aperture ratio of the pixel region is lowered.

Further, since the first common electrode 3a is arranged on both side faces of the data line 5, it is difficult to increase the aperture ratio of the pixel region in the thin film transistor array substrate of the prior art.

Accordingly, in view of the above problems, the present invention is directed to a thin film transistor array substrate whereby one or more problems due to limitations and disadvantages of the prior art are eliminated.

One of the objects of the present invention is to provide a thin film transistor array substrate and a method of fabricating the same, which is suitable for increasing the aperture ratio of a pixel region by arranging a common electrode on a data line.

Another object of the present invention is to provide a thin film transistor array substrate and a method of fabricating the same, which are suitable for increasing the aperture ratio of a pixel region by forming a pixel electrode and a common electrode on a substrate.

It is still another object of the present invention to provide a thin film transistor array substrate and a method of fabricating the same that is adapted to prevent a breakage defect by smoothing a tapered surface in a data line region adjacent to a pixel region.

Other features and advantages of the invention will be set forth in part in the description of the invention in the <RTI The objectives and other advantages of the invention will be realized and attained by the <RTI

According to a general object of the present invention, a thin film transistor array substrate includes a substrate; a gate line and a data line; the gate line and the data line are arranged to cross each other to define a pixel area on the substrate; a switch An element, which is located at a intersection of the gate line and the data line; a plurality of second pixel electrodes and a plurality of first common electrodes, wherein the second pixel electrodes and the first common electrode are alternately arranged on the substrate a second common electrode, which is formed to overlap with the data line, wherein the data line is located between a gate insulating film and a protective film; a first storage electrode is formed on the substrate; a second storage electrode formed to overlap the first storage electrode and formed as a single body with one of the switching elements, and an organic insulating film formed on the switching element, the second storage electrode, a data line, a gate pad, and a data pad, wherein the second common electrode is formed to cover the data line, the protective film, the organic insulating film, and the gate insulating film over the substrate, and has Reach the substrate surface of the inclined surface of.

According to a general object of the present invention, a method of fabricating a thin film transistor array substrate includes: providing a substrate; forming a first metal film on the substrate; and patterning the first metal film into a pattern by a first mask process a gate, a gate line, a first storage electrode and a gate pad; sequentially forming a gate insulating film, a semiconductor layer, and a second metal film on the substrate and passing through a second mask process The second metal film and the semiconductor layer form a source/drain, a second storage electrode, a channel layer, and a data line; sequentially forming a protective film and an organic insulating film on the substrate, and passing a third light The mask process forms a pattern of the organic insulating film to expose a portion of the protective film; the first and second etching steps are sequentially performed, and the organic insulating film patterned in the first and second etching steps is used as an etch mask and An etch gas having a different oxygen content ratio is used to form a pixel region on the substrate, a first contact hole exposing the second storage electrode, and a second contact hole exposing the gate pad; A third metal film is formed on the substrate, and then the pattern of the third metal film in the pixel region is formed into a plurality of pixel electrodes and a plurality of common electrodes.

Other systems, methods, features, and advantages of the invention will be apparent to those skilled in the <RTIgt; It is to be understood that all such other systems, methods, features and advantages are intended to be included within the scope of the present invention and are protected by the following claims. The content of this section is not to be construed as limiting the scope of the patent application. Further aspects and advantages will be discussed in conjunction with the following examples. It is to be understood that the foregoing general description of the invention and the claims

Embodiments of the present invention will be described in detail below in conjunction with the drawings. The embodiments introduced hereinafter are examples of those skilled in the art. Accordingly, the embodiments may be embodied in different forms and are not limited to the embodiments described herein.

Moreover, it should be understood that in an embodiment of the invention, when an element, such as a substrate, a layer, a region, a film, or an electrode, is referred to as being formed on top of another element, It may be located directly above or below the other component, or may be inserted with (indirect) components. A component 〞 above or below 〞 can be determined according to the drawing. In the drawings, the dimensions of the components are exaggerated for clarity and do not represent the actual dimensions of the components.

Fig. 3 is a schematic view showing a pixel area of a liquid crystal display device of the first embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display device of the first embodiment of the present invention includes a pixel region defined by a gate line 215 crossing a data line 315. A thin film transistor is disposed at the intersection of the gate line 215 and the data line 315.

A first common line 225 is adjacent to the gate line 215 at a position adjacent to the gate line 215. The first common line 225 intersects the data line 315.

The gate line 215 has a widened width at a position (region) crossing the data line 315. The widened width of the gate line 215 is used as the gate 250 of a thin film transistor TFT. Therefore, the gate 250 and the gate line 215 are formed as a single body. The thin film transistor TFT includes a gate 250, a source 440, a drain 450, and a channel layer (not shown).

Moreover, a first storage electrode 225a is formed in the pixel region and is formed integrally with the first common line 225 (extending from the first common line 225). The first storage electrode 225a and the second storage electrode 260 together form a storage capacitor in the pixel region. The second storage electrode 260 is opposite to the first storage electrode 225a. The second storage electrode 260 and the drain 450 are formed as a single body (or extended).

Among the pixel regions, a first pixel electrode 240 is formed to overlap the first common line 225, and a plurality of second pixel electrodes 730 extend from the first pixel electrode 240 toward the pixel region and the data Lines 315 are parallel. A plurality of second pixel electrodes 730 are arranged at regular intervals within the pixel area. Further, the second storage electrode 260 is electrically connected to the first pixel electrode 240 through the first contact hole 610.

Moreover, a second common line 245 is formed to oppose the first common line 225 and the first storage electrode 225a in the pixel region. A plurality of first common electrodes 740 extend from the second common line 245 toward the pixel region and are parallel to the data line 315. Moreover, the first common electrode 740 is alternately arranged with the second pixel electrode 730 in the pixel region.

A second common electrode 235 extends from both sides of the second common line 245 to overlap the data line 315. The second common electrode 235 prevents leakage caused by light generated by a light source of a backlight unit (not shown) and passing around the data line 315. Moreover, the second common electrode 235 is electrically connected to the first storage electrode 225a through a third contact hole 630. Therefore, a common voltage is supplied to the second common electrode 235, the first common electrode 740, and the second common line 245 through the first common line 225 and the first storage electrode 225a.

Moreover, an organic insulating film 600 is located between the second common electrode 235 and the data line 315. Moreover, the liquid crystal display device (LCD) of the present invention provides a path P of liquid crystal material which allows a liquid crystal material to flow around the data line 315 between pixel regions adjacent to each other. The path P of the liquid crystal material is formed by completely removing the organic insulating film 600 from around the data line, or by forming an organic insulating film 600 thinner than other regions in a region adjacent to (or surrounding) the data line.

At the same time, a gate pad 210 extending from the gate line 215 is formed in a pad region of a liquid crystal display device (LCD). A gate pad contact electrode 710 is formed in contact with the pad pad 210. The gate pad contact electrode 710 is in contact with the gate pad 210 through a second contact hole 620.

"4A" to "8B" are cross-sectional views showing a method of manufacturing a liquid crystal display device, and show a thin film transistor array along the II-II' line and the III-III' line of "Fig. 3". The cross-sectional structure of the substrate.

Referring to "FIG. 4A" and "FIG. 4B", a first metal film is deposited on a base substrate 100 of a transparent insulating material by a sputtering method. Then, an etching step is performed on the deposited metal film during a first mask process.

During the first mask process, a photoresist having a photosensitive material is first formed over the deposited metal film. Then, the photoresist is subjected to exposure and development by using a photomask having a transmissive region and a non-transmissive region, thereby forming a photoresist pattern. Thereafter, the deposited metal film is etched by using the photoresist pattern as a mask to form a gate 250, a first storage electrode 225a, and a gate pad 210. At the same time, a gate line 215 and a first common line 225 are formed. The gate line 215 and the gate 250 form a single body. The first common line 225 and the first storage electrode 225a are formed as a single body.

The first metal film may be from a group of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, or a combination thereof Choose a material to form. Although the metal film is formed in a single layer as shown, the metal film may be formed by stacking at least two metal layers as needed.

After the gate electrode 250 and the like are formed on the base substrate 100, as shown in "5A" and "5B", a gate insulating film 200, an amorphous germanium film, and a doped amorphous germanium film ( A semiconductor layer of n+ or p+) and a second metal film are sequentially formed over the base substrate 100 having the gate electrode 250 and the first storage electrode 225a and the gate pad 210 described above.

The second metal film may be from a group of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, or a combination thereof One of the materials selected is formed. Further, a transparent conductive material layer such as Indium Tin Oxide (ITO) can be used as the second metal film. Moreover, although the second metal film is formed in a single layer as shown, the second metal film may be formed by stacking at least two metal layers as needed.

Subsequently, a second mask process using one of the halftone mask and the diffractive mask is performed on the base substrate 100 covered with the second metal film to form the source/drain electrodes 440 and 450 from the second metal film. The second storage electrode 260, and a data line 315, and a channel layer 340 are formed from the semiconductor layer. Although not shown, a data pad is also formed at the same time.

The channel layer pattern 320 exists below the data line 315 due to the use of a halftone mask or a diffractive reticle. As shown in FIG. 5B, a storage capacitor is formed between the first storage electrode 225a and the second storage electrode 260. Thereafter, a protective film 500 is formed on the entire surface of the base substrate 100.

Referring to "FIG. 6A" to "FIG. 6C" and "FIG. 7", an organic insulating film 600 is formed on the base substrate 100 on which the protective film 500 is formed, as shown in FIG. 6A. Thereafter, a third mask process is performed on the base substrate 100 on which the organic insulating film 600 is formed, and a light having a total transmission region P1 non-transmissive region P2 and a semi-transmissive region P3 is used in the third mask process. Cover 800. As shown in FIG. 6B, the third mask process completely removes the organic insulating film 600 corresponding to the total transmission region P1 of the mask 800 for exposing the protective film, and partially removing the semi-transmissive region P3 of the mask 800. The corresponding organic insulating film 600 serves to reduce the thickness of the protective film 500, and maintain (i.e., not remove) the organic insulating film 600 corresponding to the non-transmissive region P2 of the reticle 800 as it is.

The organic insulating film 600 has a lower dielectric constant than the protective film 500. The organic insulating film 600 may have a dielectric constant of about 3.0 to 4.0. Preferably, the organic insulating film 600 between the data line 315 and the second common electrode 235 (see "8B") formed later has a dielectric constant of about 3.4 to 3.8. The organic insulating film 600 located between the data line 315 and the second common electrode 235 formed later may have a thickness of about 3 to 6 micrometers (μm). Alternatively, the organic insulating film 600 may have different thicknesses depending on the driving frequency of the liquid crystal display device (LCD).

As the drive frequency becomes higher, a coupling effect between the data line 315 and the second common electrode ("235" of FIG. 3) produces a signal delay, wherein the second common electrode is later formed in the organic insulation Above the film 600. However, the liquid crystal display device (LCD) of the present invention uses the low dielectric constant organic insulating film 600 so that the parasitic capacitance generated between the data line 315 and the second common electrode 235 is reduced. Therefore, signal delay can be prevented.

More specifically, the parasitic capacitance is inversely proportional to the distance between the data line 315 and the second common electrode 235. Therefore, the larger the thickness of the organic insulating film 600 between the data line 315 and the second common electrode 235, the smaller the parasitic capacitance. As a result, the signal delay caused by the coupling effect between the data line 315 and the second common electrode 235 can be reduced.

For example, if the driving frequency of the liquid crystal display device (LCD) is set to 120 Hz, the thickness of the organic insulating film 600 between the data line 315 and the second common electrode 235 may be about 2.5 to 3.5 micrometers (μm). Within the scope. Alternatively, when the liquid crystal display device (LCD) has a driving frequency of 240 Hertz (Hz), the thickness of the organic insulating film 600 may be in the range of about 5.5 to 6.5 micrometers (μm). Thus, since the thickness is not set to a fixed value when the liquid crystal display device (LCD) is designed, it can be changed according to the specifications of the liquid crystal display device. Moreover, it is necessary to change the position of the second common electrode 235 to prevent light leakage and increase the aperture ratio of the pixel area. In this case, the organic insulating film 600 can be made thinner or thicker depending on the driving frequency.

Further, the organic insulating film 600 may be formed from an acrylic-based resin. The acrylic-based resin contains a photo propylene, but is not limited thereto. In other words, if the material of the organic insulating film 600 has a low dielectric constant, the organic insulating film 600 is not limited to photo propylene.

By combining "FIG. 6B", as described above, the third mask process of the liquid crystal display device (LCD) manufacturing method of the present embodiment performs the exposure and development steps of the base substrate 100 for completely and partially removing organic The insulating film 600. In other words, at this time, the organic insulating film 600 is patterned by the exposure and development steps.

After the exposure and development steps, an etching step is performed by using the patterned organic insulating film 600 as a mask.

In the etching step, as shown in "Fig. 6C", a portion of the base substrate 100 is exposed to form a pixel region PIX. A first contact hole 610 is formed to expose a portion of the second storage electrode 260, wherein the second storage electrode 260 and the drain 450 are formed as a single body. Moreover, a second contact hole 620 is formed to expose the gate pad 210 (a portion).

At the same time, the protective film 500 and the gate insulating film 200 formed around the data line 315 are sequentially etched. Also, since the halftone mask or the diffractive mask is used in the third mask process, the tapered surface formed adjacent to both sides of the data line can be smoothed. Similarly, the protective film 500 and the gate insulating film 200 stacked on the gate pad 210 are also sequentially etched to form the second contact hole 620. However, only the protective film 500 is etched to form the first contact hole 610 exposing a portion of the second storage electrode 260. Furthermore, the third mask process employed in the method of the present invention performs two etching steps by using gases of different oxygen content ratios. Also, the edge surfaces of the protective film 500 and the gate insulating film 200 are smoothed. Therefore, the second common electrode covering the data line 315 formed later has a top surface on the organic insulating film 600, and two smooth inclined surfaces reaching the surface of the base substrate 100. As a result, disconnection caused by poor step coverage (i.e., a steep step portion) at the boundary between the second common electrode 235 and the pixel region can be prevented.

Moreover, as described above, the present embodiment forms a thinner organic insulating film 600 over the thin film transistor and the storage capacitor. Thus, the thickness of the organic insulating film 600 formed over the thin film transistor and the storage capacitor is reduced. In addition, the organic insulating film 600 and the protective film 500 remaining on the data line 315 and the gate insulating film 200 remaining under the data line 315 have tapered surfaces on both sides of the data line 315 due to the use of a halftone mask. And the diffractive reticle, the continuity of the data line 315 is improved.

Further, as shown in "Fig. 7", a third contact hole 630 is formed to correspond to the first storage electrode 225a by the third mask process.

The second and third contact holes 620 and 630 are formed by etching the protective film 500 and the gate insulating film 200. To this end, only a dry etching step in a conventional technique can be used. In this case, the organic insulating film 600 remains in the contact holes after the exposure and development processes. Thus, since the organic insulating film 600 is left, the inner surface of each contact hole becomes rough, and the tapered inner surface surface defects are generated in these contact holes.

On the other hand, as shown above, the third mask process employed in the method of the present embodiment performs two etching steps by using etching gases of different oxygen contents. Therefore, such a tapered inner side surface defect is not generated within these contact holes.

Referring to FIGS. 8A and 8B, a third metal film is formed on the base substrate 100 having contact holes, the third metal film is indicated by a thick line 700, and then the photoresist film 770 is applied to Above the third metal film. Subsequently, a fourth mask process having an exposure and development step is performed on the photoresist film 770 and the third metal film, so that the pattern of the third metal film is formed as a first pixel electrode 240, a first common electrode 740, The two pixel electrodes 730, a second common electrode 235, and a gate pad contact electrode 710.

The third metal film may be from a group of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, or a combination thereof One of the materials selected is formed. Further, a transparent conductive material layer such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) can be used as the third metal film. Moreover, although the third metal film is formed in a single layer as shown, the third metal film may be formed by stacking at least two metal layers as needed.

The first common electrode 740, the second common electrode 235, and the gate pad contact electrode 710 may be formed of an opaque metal, and the first pixel electrode 240 and the second pixel electrode 730 may be formed of a transparent conductive material. In this case, the mask process is performed twice.

In order to remove a black matrix or reduce the width of the black matrix from the color filter substrate, the second common electrode 235 in the liquid crystal display device (LCD) of the present embodiment is preferably formed of an opaque metal.

In contrast, the first pixel electrode 240, the first common electrode 740, the second pixel electrode 730, the second common electrode 235, and the gate pad contact electrode 710 may be formed of a transparent conductive material. In this case, a black matrix is formed on the color filter array substrate opposite to the data line 315.

The first pixel electrode 240 is connected to the second storage electrode 260 through the first contact hole 610. The second pixel electrode 730 and the first common electrode 740 are alternately arranged in the pixel region of the base substrate 100 and are parallel to the data line 315.

The second common electrode 235 is formed to cover the data line 315. In other words, the second common electrode 235 is formed on the surface of the organic insulating film 600 covering the data line 315, that is, the horizontal surface of the organic insulating film 600 above the data line 315 and the organic insulating film on both sides of the data line 315 The inclined side surface of the film 600. As a result, the second common electrode 235 is formed to cover all of the gate insulating film 200 under the data line 315, and the protective film 500 and the organic insulating film 600 deposited on the data line 315.

Such a second common electrode 235 shields an electric field formed between the data line 315 and the second pixel electrode 730. Also, leakage of light generated along the data line 315 can be prevented.

Moreover, since the organic insulating film 600 is formed of a material having a lower dielectric constant than the protective film 500, the parasitic capacitance generated between the second common electrode 235 and the data line 315 can be reduced. Therefore, the signal delay caused by the coupling effect can be reduced.

The gate pad contact electrode 710 is electrically connected to the gate pad 210 through the second contact hole 620. Although not shown, the data pad contact electrodes in a data pad area are also electrically connected to a data pad.

The "Fig. 9" to "Fig. 11" are cross-sectional views showing the cross-sectional structures of the liquid crystal display devices along the lines IV-IV', V-V' and VI-IV' of "Fig. 3", respectively.

The liquid crystal display device (LCD) of this embodiment can include two types of spacers. One type of spacer is a gap column spacer for maintaining a cell gap between a color filter array substrate and a thin film transistor array substrate, and another type of spacer is a contact column spacer. It is used to prevent the damage of the gap column spacer from external pressing. The gap column spacer is applied to a liquid crystal display device (LCD) of the prior art. Thus, the contact column spacer formed in the present embodiment together with the gap column spacer will now be described.

"9th to 11th" shows a contact column spacer 400. Since the spacer is not limited to its position, the position of the gap column spacer (not shown) and the contact column spacer can be freely changed.

When the display region of the liquid crystal display device (LCD) is pressed by an external force, the contact column spacer 400 employed in the liquid crystal display device (LCD) of the present embodiment disperses the force with which the spacer column spacer can withstand. If the liquid crystal display device (LCD) contains only the gap column spacer, the gap column spacer is destroyed or loses its restoring force. However, when a portion of the display area of the liquid crystal display device (LCD) is pressed by an external force greater than a predetermined force, the contact column spacer 400 maintains the liquid crystal display device (LCD) together with the gap column spacer. The cell gap.

The contact column spacer 400 shown in Fig. 9 is arranged to correspond to the storage capacitor. Referring to "Fig. 3" and "Fig. 9", a first storage electrode 225a formed as a single body with the first common line 225 is formed on the base substrate 100. Further, a gate insulating film 200, a protective film 500, an organic insulating film 600, and a second storage electrode 260 are sequentially formed over the first storage electrode 225a.

On the other hand, a black matrix 350 and a cover layer 371 are sequentially formed on the top substrate 300 of the color filter array substrate opposite to the base substrate 100. Moreover, a contact column spacer 400 corresponds to the second storage electrode 260 above the base substrate 100, and is formed over the cover layer 371.

Further, a trench G is formed on the organic insulating film 600 opposite to the contact column spacer 400. The trench G can be formed by completely or partially removing the organic insulating film 600 over the second storage electrode 260.

Please refer to FIG. 3, FIG. 10 and FIG. 11 , and the contact column spacer 400 and the gate line 215 ( FIG. 10 ) are formed on the cover 371 of the top substrate 300 . Above, and further contacting the column spacer 400 and the data line 315 ("FIG. 11") are formed on the cover 371 of the top substrate 300. In the "10th drawing", the other trench G is formed on the gate line 215 opposite to the contact column spacer 400 by completely removing the organic insulating film 600 over the protective film 500. Thus, the protective film 500 is exposed through the other trench G. Alternatively, another trench G may be formed through a pattern in which the organic insulating film 600 is formed, wherein the thickness of the organic insulating film 600 in the other trench G is smaller than that in other regions adjacent to the other trench G. .

Similarly, the further trench G is opposed to the further contact column spacer 400 ("FIG. 11"), and is formed on the data line 315 by removing the organic insulating film 600 over the protective film 500. Subsequently, the second common electrode 235 is formed over the organic insulating film 600. In detail, the second common electrode 235 is formed on the inner surface of the organic insulating film 600, the further trench G, and the exposed protective film 500. Alternatively, the organic insulating film 600 may remain in the further trench G, and the thickness of the organic insulating film 600 in the further trench G is compared to the organic insulating film 600 in other regions of the adjacent trench G. The thickness is smaller. This result can be achieved by a half-tone mask or a semi-transmissive area of the diffractive reticle.

If a portion of the display region of the liquid crystal display device having the columnar spacer 400 and the spacer column spacer is pressed, the gap column spacer maintains the cell gap until the contact column spacer 400 and the bottom surface of the trench G are contact. When the contact column spacer 400 is in contact with the bottom surface of the groove G, the gap column spacer maintains the cell gap together with the contact column spacer 400. In other words, the liquid crystal display device (LCD) of the present embodiment allows only the gap column spacers or the entire gap column spacers and the contact column spacers to be maintained according to the strength of the pressing force of a portion of the display region. Cell gap.

Fig. 12 is a cross-sectional view showing the cross-sectional structure of the path of the liquid crystal material along the line VII-VII' of "Fig. 3".

Referring to "Fig. 3" and "Fig. 12", the organic insulating film 600, the protective film 500, and the gate insulating film 200 are all removed from the liquid crystal display device (LCD) of the present embodiment. In contrast, the organic insulating film 600 is formed over the non-display area between the pixel regions. Also, a liquid crystal material is placed in each pixel area. Therefore, all pixel regions are required to be filled with liquid crystal materials of the same height.

In other words, although the liquid crystal material is overfilled or underfilled in some of the pixel regions, since the organic insulating film 600 is formed over the data line 315, the liquid crystal material is not uniformly distributed over the entire pixel region. If the liquid crystal material is filled to have different degrees (or different heights) in the pixel region, a defect such as a spot is generated. Further, when the liquid crystal material overfilled in the one pixel region is broken, the spacer or the organic insulating film 600 adjacent to the non-display region of the overfilled liquid crystal material may be damaged. Therefore, the screen quality of the liquid crystal display device (LCD) can be degraded.

In order to average the filling degree (height) of the liquid crystal material in all the pixel regions, the liquid crystal display device (LCD) of the present embodiment has a path P of liquid crystal material formed between adjacent pixel regions. Path P allows liquid crystal material to flow between adjacent pixel regions.

As shown in the drawing, the gate insulating film 200, the channel layer pattern 320, the data line 315, the protective film 500, the organic insulating film 600, and the second common electrode 235 are sequentially formed over the base substrate 100. The path P of the liquid crystal material can be formed by removing all or part of the organic insulating film 600 overlapping the data line 315.

The path P of the liquid crystal material is formed to have the same length as the width of the data line 315. Moreover, the width of the path P of the liquid crystal material can be selectively adjusted. Moreover, a path P of at least one liquid crystal material may be formed in each pixel region.

The "Fig. 13A" and "Fig. 13B" are cross-sectional views showing the cross-sectional structure of the liquid crystal display device along the line VIII-VIII' of "Fig. 3".

Please refer to FIG. 13A and FIG. 13B. The structure of the thin film transistor array substrate and the color filter array substrate surrounding the data line 315 is as shown in the figure.

The channel layer pattern 320 and the data line 315 are sequentially formed over the gate insulating film 200 of the base substrate 100. Further, the protective film 500 and the organic insulating film 600 are sequentially formed over the data line 315. Moreover, the second common electrode 235 is formed over the organic insulating film 600 to cover the data line 315. In other words, the second common electrode 235 is formed to cover the organic insulating film 600, the protective film 500, and the gate insulating film 200 and has an inclined surface reaching the base substrate 100.

Such a second common electrode 235 is formed of an opaque metal. Thus, the second common electrode 235 can be derived from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, or combinations thereof. One of the materials selected in one of the groups is formed.

Moreover, as opposed to the second common electrode 235, the black matrix 350 formed on the color filter array substrate can be reduced to a smaller width than the conventional technique. The black matrix 350 is formed to have a thickness ranging between the width of the second common electrode 235 and the data line 315. For example, the black matrix 350 can have a width in the range of approximately 6-16 micrometers (μm).

In this manner, the reduced width of the black matrix 350 allows a red (R) filter layer 303a, a green (G) filter layer 303b, and a blue (B) filter layer (not shown) to be formed as Has a larger size (ie, an enlarged size). Therefore, the aperture ratio of the liquid crystal display device (LCD) can be improved.

"Fig. 13B" is a schematic diagram of a color filter array substrate in which the black matrix has been completely removed. In this case, the second common electrode 235 over the thin film transistor array substrate serves as a black matrix. Since the black matrix is removed from the liquid crystal display device (ie, the color filter array substrate), the liquid crystal display device (LCD) shown in FIG. 13B has a larger liquid crystal display device than the "13A". The aperture ratio.

"Fig. 14A" and "Fig. 14B" are diagrams for explaining the problems caused by applying the etching method of the prior art to the contact hole manufacturing process of the present embodiment.

As shown in FIG. 14A and FIG. 14B, the thin film transistor array substrate of the present embodiment includes a gate pad 210 formed in the gate pad region of the base substrate 100. The thin film transistor array substrate further includes a gate insulating film 200, a protective film 500, and an organic insulating film 600 which are sequentially formed over the gate pad 210.

To expose the gate pad 210, a conventional dry etching process can be used. In this case, the organic insulating film 600 remains inside the hole after the exposure and development process. Therefore, the inner side surface of the hole becomes rough due to the retained organic insulating film 600.

As shown in "Fig. 14A", the organic insulating film 600 remaining in the hole forms a cut structure in one of the bottom portions of the organic insulating film 600. In other words, a step coverage is generated in the organic insulating film 600, the protective film 500, and the gate insulating film 200.

As shown in "Fig. 14B", the step generated in the hole covers a metal film 470 which is formed later to cause disconnection. Actually, in the present embodiment, an electrical disconnection can be generated in the gate pad contact electrode formed in the gate pad region by the step formed on the inner side wall of the contact hole. The metal film 470 may have a structure in which at least two metal layers are stacked.

In order to solve this problem, when forming a contact hole, the present embodiment changes the content of an etching gas and performs two etching processes.

"15A" to "15C" are schematic views for explaining an etching process during the manufacture of a contact hole in the present embodiment. The etching process can be applied to the third mask process shown in "Fig. 6a" to "Fig. 7".

As shown in "15A" to "15C", the gate pad 210 is formed on the base substrate 100. Thereafter, the gate insulating film 200, the protective film 500, and the organic insulating film 600 are sequentially formed over the gate pad 210.

Before the first etching process is performed, the organic insulating film 600 is patterned through a mask process, and the patterned organic insulating film is used as a mask in the first etching process. The flow ratio of the sulfur hexafluoride:oxygen (SF6:O2) etching gas used in the first etching process may be in the range of about 1:2.0 to 1:3.0. For sulfur hexafluoride: oxygen (SF6: O2) etching gas, it is preferred to have a flow ratio of about 1:2.5. For example, if sulfur hexafluoride (SF6) corresponds to 4000, the oxygen (O2) may range from about 10,000 to 12,000.

Subsequently, the flow ratio of the sulfur hexafluoride:oxygen (SF6:O2) etching gas is varied and then a second etching process is performed. At this time, the flow ratio of the sulfur hexafluoride:oxygen (SF6:O2) etching gas may be in the range of about 1:2.4 to 1:3.0. Preferably, sulfur hexafluoride: oxygen (SF6: O2) is set to a flow ratio of about 1:2.5.

In other words, if the content of the oxygen (O2) gas is increased during the first and second etching processes, the roughness of the inner side surface among the contact holes can be improved. Also, the time for performing the second etching is preferably the same as or shorter than the time for performing the first etching.

As shown in "Fig. 15B", the first and second inclined surfaces S1 and S2 of the contact hole of the gate pad 210 are formed as a smooth surface. Thus, the step coverage is not generated in the organic insulating film 600, the protective film 500, and the gate insulating film 200.

Further, although the metal film 470 is formed on the base substrate 100 as shown in FIG. 15C, the disconnection is not generated in the metal film 470 within the contact hole of the gate pad 210.

Thus, the third mask process of the present embodiment performs two etching processes. As a result, the step coverage over the inner side surface of the contact hole is eliminated.

"16th" to "18th" are cross-sectional views of the thin film transistor array substrate along the II-II' and III-III' lines of "Fig. 3", and explain the second to the present invention according to the present invention. A method of manufacturing a liquid crystal display device of a fourth embodiment.

Although the thin film transistor array substrate manufactured by the methods of the second to fourth embodiments has a partially different structure from the thin film transistor array substrate manufactured by the method of the first embodiment, the second to fourth embodiments are The manufacturing method can be carried out in the same manner as the manufacturing method of the first embodiment shown in "Ath 4A" to "8B". Therefore, the portions of the methods of the second to fourth embodiments which are different from the structures shown in "Fig. 4A" to "8B" will be explained. Further, the same reference numerals of the methods of the second to fourth embodiments denote the same elements as those shown in "Ath 4A" to "8B".

The methods of the second to fourth embodiments allow the modification of the structure among the non-display areas on which the data pads and the gate pads formed according to the method of the first embodiment are formed.

Referring to FIG. 3 and FIG. 16, the method of the second embodiment allows an organic insulating film 600a formed in a region covered with the gate pad 210 to have an organic insulating film formed over the data line 315. 600 different thicknesses.

More specifically, the method of the second embodiment allows the organic insulating film 600a in the thin film transistor region to be formed to have the same thickness as the organic insulating film 600a in the region of the gate pad 210. Although not shown, the organic insulating film pattern is formed in the region of the data pad in the same manner as in the regions of the gate pad 210 and the thin film transistor. In other words, the pattern of the organic insulating film 600a in the non-display area covered with the data pad and the gate pad 210 has a smaller thickness than the organic insulating film 600 overlapping the data line 315. The pattern of the organic insulating film 600a having a small thickness can be realized by a third mask process in which one of a halftone mask and a diffractive mask is used to form the contact holes.

In this manner, the height of the pattern of the organic insulating film 600a in the pad region is lowered from the fact that the organic insulating film 600 is thicker than the protective film 500 and the gate insulating film 200. If the pattern of the organic insulating film 600a is formed to have a uniform thickness in the display and non-display areas, contact defects of the terminals of the external driving integrated circuit are generated.

Therefore, a liquid crystal display device (LCD) having a reduced organic insulating film in the pad region makes it easy to electrically contact the terminal of the external driving integrated circuit.

The method of the third embodiment obtains the structure of a thin film transistor array substrate, as shown in Fig. 17, in which the pattern of the organic insulating film 600a is completely removed from the gate pad region and the data pad region. Thus, when the gate pad contact electrode 710 is formed over the protective film 500, the gate pad contact electrode 710 is electrically connected to the gate pad 210. Similarly, when a data pad contact electrode (not shown) is formed over the protective film 500, the data pad contact electrode (not shown) is electrically connected to a data pad (not shown).

The method of the fourth embodiment obtains a structure of a thin film transistor array substrate in which the pattern of the organic insulating film 600a, the protective film 500, and the gate insulating film 200 are completely removed from the gate pad region. Similarly, the pattern of the organic insulating film 600a and the protective film 500 are completely removed from the material pad region. In this case, the gate insulating film 200 under the data pad is retained. Moreover, the pattern of all the organic insulating films 600a between the gate pads and the data pads, the protective film 500, and the gate insulating film 200 are removed, so that the surface of the base substrate 100 is exposed between the pads and the gates. Between the mats.

As a result, the gate pad contact electrode 710 is formed directly on the gate pad 210 and the base substrate 100. Moreover, the gate pad contact electrode 710 completely covers the gate pad 210.

In this manner, the method of the embodiments of the present invention can form different structures in the pad region of a liquid crystal display device (LCD) without requiring an additional mask process.

While the embodiments of the present invention have been described above by way of exemplary embodiments, those skilled in the art will recognize that the present invention can be practiced without departing from the spirit and scope of the invention disclosed in the appended claims. Modifications and retouchings are within the scope of patent protection of the present invention. In particular, different variations and modifications of the components and/or combinations may be made in the specification, the drawings and the accompanying claims. In addition to variations and modifications in the component parts and/or combinations thereof, those skilled in the art should also be aware of the alternate use of the components and/or combinations.

1. . . Gate line

1a. . . Gate

3. . . First common line

3a. . . First common electrode

5. . . Data line

6. . . First storage electrode

7. . . Second storage electrode

7a. . . Pixel electrode

10. . . Bottom substrate

12. . . Gate insulating film

13. . . Second common line

13a. . . Second common electrode

13b. . . Third common electrode

19. . . Protective film

20. . . Top substrate

twenty one. . . Black matrix

25a. . . Red filter layer

25b. . . Green filter

29. . . Cover layer

100. . . Bottom substrate

200. . . Gate insulating film

210. . . Gate pad

215. . . Gate line

225. . . First common line

225a. . . First storage electrode

235. . . Second common electrode

240. . . First pixel electrode

245. . . Second common line

250. . . Gate

260. . . Second storage electrode

300. . . Top substrate

303a. . . Red filter layer

303b. . . Green filter

315. . . Data line

320. . . Channel layer pattern

340. . . Channel layer

350. . . Black matrix

371. . . Cover layer

400. . . Contact column spacer

440. . . Source

450. . . Bungee

470. . . Metal film

500. . . Protective film

600, 600a. . . Organic insulating film

610. . . First contact hole

620. . . Second contact hole

630. . . Third contact hole

700. . . Third metal film

710. . . Gate pad contact electrode

730. . . Second pixel electrode

740. . . First common electrode

770. . . Photoresist film

800. . . Mask

TFT. . . Thin film transistor

G. . . Trench

R. . . Top substrate

P. . . path

P1. . . Full transmission area

P2. . . Non-transmission zone

P3. . . Semi-transmission zone

L1. . . width

S1. . . First inclined surface

S2. . . Second inclined surface

1 is a schematic diagram of a pixel structure in a liquid crystal display device of a planar switching (IPS) mode of the prior art;

Figure 2 is a cross-sectional view of the pixel structure along the line I-I' of Figure 1;

3 is a schematic view showing a pixel region of a liquid crystal display device according to a first embodiment of the present invention;

4A, 5A, 6A-6C, 8A, and 8B are transverse layers of the thin film transistor array substrate along the II-II' line and the III-III' line of FIG. a cross-sectional view, and a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention;

4B is a schematic view showing the planar structure of the thin film transistor array substrate of FIG. 4A;

5B is a schematic view showing a planar structure of the thin film transistor array substrate of FIG. 5A;

Figure 7 is a schematic view showing the planar structure of the thin film transistor array substrate of Figure 6C;

9 to 11 are cross-sectional views showing cross-sectional structures of liquid crystal display devices along the lines IV-IV', V-V' and VI-IV' of Fig. 3, respectively;

Figure 12 is a cross-sectional view showing the cross-sectional structure of the liquid crystal material path along the line VII-VII' of Figure 3;

13A and 13B are cross-sectional views showing a cross-sectional structure of a liquid crystal display device taken along line VIII-VIII' of Fig. 3;

14A and 14B are diagrams for explaining the problems caused by applying the etching method of the prior art to the contact hole manufacturing process of the present embodiment;

15A to 15C are schematic views explaining an etching process during manufacture of a contact hole in the embodiment;

16 to 18 are cross-sectional views of the thin film transistor array substrate along the II-II' and III-III' lines of Fig. 3, and explain the liquid crystals according to the second to fourth embodiments of the present invention. A method of manufacturing a display device.

210. . . Gate pad

215. . . Gate line

225. . . First common line

225a. . . First storage electrode

235. . . Second common electrode

245. . . Second common line

250. . . Gate

260. . . Second storage electrode

315. . . Data line

400. . . Contact column spacer

450. . . Bungee

600. . . Organic insulating film

610. . . First contact hole

620. . . Second contact hole

630. . . Third contact hole

710. . . Gate pad contact electrode

730. . . Second pixel electrode

740. . . First common electrode

TFT. . . Thin film transistor

P. . . path

Claims (13)

A thin film transistor array substrate comprises: a substrate; a gate line and a data line arranged to cross each other to define a pixel area on the substrate; a switching element is disposed on the substrate a gate line intersecting one of the data lines; a plurality of second pixel electrodes and a plurality of first common electrodes are alternately formed on the substrate of the pixel region; and a second common electrode is formed as And overlapping with the data line, wherein the data line is located between a gate insulating film and a protective film; a first storage electrode is formed on the substrate; and a second storage electrode is formed with the first a storage electrode overlapping and forming a single body with one of the switching elements, and an organic insulating film formed on the switching element, the second storage electrode, the data line, a gate pad, and a Above the data pad, wherein the second common electrode is formed to cover the data line over the substrate, the protective film, the organic insulating film, and the gate insulating film, and has an inclined surface reaching a surface of the substrate, wherein The painting Region based on the substrate is completely removed from the organic insulating film, the protective film and the gate insulating film, one electrode area. The thin film transistor array substrate of claim 1, wherein the thin film transistor array substrate is formed The thickness of the insulating element, the second storage electrode, the gate pad, and the organic insulating film over the data pad is smaller than the thickness of the organic insulating film formed over the data line. The thin film transistor array substrate of claim 1, wherein the second common electrode is formed of an opaque metal. The thin film transistor array substrate of claim 1, wherein when the driving frequency of one of the thin film transistor array substrates is 120 Hz, the organic between the data line and the second common electrode The thickness of the insulating film is in the range of 2.5 to 3.5 micrometers (μm). The thin film transistor array substrate of claim 1, wherein when the driving frequency of one of the thin film transistor array substrates is 240 Hz, the organic between the data line and the second common electrode The thickness of the insulating film is in the range of 5.5 to 6.5 micrometers (μm). The thin film transistor array substrate of claim 1, further comprising a path of a liquid crystal material, the path being formed in a region overlapping a portion of the data line and configured to allow filling of the pixel The liquid crystal material in the region flows between pixel regions adjacent to each other. The thin film transistor array substrate of claim 6, wherein the path of the liquid crystal material is formed by removing a portion of the organic insulating film overlapping the data line. A method for manufacturing a thin film transistor array substrate comprises the following steps: Providing a substrate; forming a first metal film on the substrate; and patterning the first metal film into a gate, a gate line, a first storage electrode, and a gate through a first mask process a pad; sequentially forming a gate insulating film, a semiconductor layer, and a second metal film on the substrate and forming a source/drain from the second metal film and the semiconductor layer through a second mask process a second storage electrode, a channel layer, and a data line; sequentially forming a protective film and an organic insulating film on the substrate, and forming a pattern of the organic insulating film through a third mask process for exposing a portion of the protective film; the first etching step and the second etching step are sequentially performed, and the organic insulating film patterned in the first etching step and the second etching step is used as an etching mask and is used differently An oxygen content ratio etching gas for forming a pixel region on the substrate, a first contact hole exposing the second storage electrode, and a second contact hole exposing the gate pad; and forming a third Metal film The pattern of the third metal film in the pixel region is formed on the substrate and then formed into a pixel electrode and a second common electrode. The method of manufacturing a thin film transistor array substrate according to claim 8, wherein the third mask process removes the organic insulating film overlapping the data line Less than a part, and a path of liquid crystal material is formed so that the liquid crystal flows between adjacent pixel regions. The method of fabricating a thin film transistor array substrate according to claim 8, wherein the third mask process uses a halftone mask or a diffractive mask and the source/drain and the second storage electrode The organic insulating film on the upper portion has a smaller thickness than the organic insulating film over the data line. The method for manufacturing a thin film transistor array substrate according to claim 8, wherein the etching gas used in the first etching step comprises a sulfur hexafluoride: oxygen (SF ₆ : O ₂ ) flow ratio of 1 : Within the range of 2.0~1:3.0. The method for fabricating a thin film transistor array substrate according to claim 8, wherein the etching gas used in the second etching step comprises a sulfur hexafluoride: oxygen (SF ₆ : O ₂ ) flow ratio of 1 : Within the range of 2.4~1:3.0. The method of manufacturing a thin film transistor array substrate according to claim 8, wherein the first contact holes formed by the third mask process and the inner side surfaces of the second contact holes are smoothed.