KR101852632B1 - Thin film transistor array substrate and method for fabricating the same - Google Patents

Abstract

The present invention discloses a thin film transistor array substrate and a manufacturing method thereof. The disclosed thin film transistor array substrate of the present invention comprises: a substrate; A gate line and a data line cross-arrayed to define a pixel region on the substrate; A switching element disposed at an intersection of the gate line and the data line; A pixel electrode arranged in the pixel region in parallel with the data line and having a symmetrical structure vertically with respect to a center of the pixel region; And a common electrode and a common line disposed on the pixel electrode and the data line, respectively, with a gate insulating film and a protective film interposed therebetween, wherein a protective film region exposed between the common electrode and the common line has a stepped region And the region where the common line and the common line are formed and the region where the common line is formed are different from each other in thickness.
The present invention has an effect of reducing the liquid crystal driving voltage by reducing the thickness of the insulating film between the pixel electrode and the common electrode while overpassing the protective film on which the common electrode is formed, and by making the thickness of the insulating film of the data line region the same as in the conventional case.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor array substrate and a method of manufacturing the same. BACKGROUND ART [0002]

The present invention relates to a liquid crystal display device in which a liquid crystal driving voltage is reduced to reduce power consumption.

[0002] A liquid crystal display typically displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. The liquid crystal display device is formed by a color filter substrate on which a color filter array is formed and a thin film transistor array substrate on which a thin film transistor (TFT) array is formed.

In recent years, liquid crystal display devices employing various new methods have been developed to solve the narrow viewing angle problem of the liquid crystal display device. A liquid crystal display device having a wide viewing angle characteristic includes an in-plane switching mode (IPS), an optically compensated birefringence mode (OCB), and a fringe field swithching (FFS) mode.

In the transverse electric field type liquid crystal display device, a pixel electrode and a common electrode are disposed on the same substrate so that a horizontal electric field is generated between the electrodes. As a result, the long axes of the liquid crystal molecules are aligned in the horizontal direction with respect to the substrate, and thus the liquid crystal display device has a wide viewing angle characteristic as compared with a conventional TN (Twisted Nematic) type liquid crystal display device.

In recent years, a technique for manufacturing a liquid crystal display device using liquid crystal driven by a low voltage has been developed in order to reduce power consumption. Particularly, in the conventional transverse electric field type liquid crystal display device, since the pixel electrode is formed on the gate insulating film and then the protective film is formed and then the common electrode is formed, only the protective film exists between the common electrode and the pixel electrode.

However, recently, in the case of a monitor liquid crystal display device, there is a problem that a gate insulating film and a protective film are interposed between the pixel electrode and the common electrode to increase the driving voltage of the liquid crystal.

In order to prevent this, a method of reducing the thickness of the protective layer is devised. When the thickness of the protective layer is reduced, a parasitic capacitance between the data line and the common electrode (common line) increases.

Particularly, when the pixel driving voltage rises or the parasitic capacitance increases, there is a problem that the power consumption increases or the screen quality drops.

The present invention relates to a thin film transistor array substrate in which a thickness of an insulation film between a pixel electrode and a common electrode is reduced by over-etching a protective film on which a common electrode is formed, And a manufacturing method thereof.

Another object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the thin film transistor array substrate in which the protective film between the common electrodes of the present invention is removed by overgrowth to increase the liquid crystal driving area and improve device reliability.

According to an aspect of the present invention, there is provided a thin film transistor array substrate comprising: a substrate; A gate line and a data line cross-arrayed to define a pixel region on the substrate; A switching element disposed at an intersection of the gate line and the data line; A pixel electrode arranged in the pixel region in parallel with the data line and having a symmetrical structure vertically with respect to a center of the pixel region; And a common electrode and a common line disposed on the pixel electrode and the data line, respectively, with a gate insulating film and a protective film interposed therebetween, wherein a protective film region exposed between the common electrode and the common line has a stepped region And the region where the common line and the common line are formed and the region where the common line is formed are different from each other in thickness.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, comprising: providing a substrate divided into a display region and a non-display region; Forming a transparent conductive material on the substrate, and forming a pixel electrode in a pixel region of a display region according to a first mask process; Forming a metal film on the substrate on which the pixel electrode is formed, and then performing a second mask process to form a gate line, a gate electrode, a gate pad, and a data pad; Forming a gate insulating film, a semiconductor layer and a metal film sequentially on a substrate on which the gate electrode is formed, and forming a source / drain electrode and a data line according to a third mask process using a diffraction mask or a halftone mask; A protective film is formed on the substrate on which the source / drain electrodes are formed, and then a portion of the pixel electrode is exposed through a gate pad region, a data pad region, and a center of the drain electrode in a non- Forming a contact hole; Forming a common electrode on the protective film over the pixel electrode and a common line on the protective film over the data line in accordance with a fifth mask process, forming a transparent conductive material on the substrate on which the contact hole is formed, And simultaneously forming a contact electrode electrically connecting the drain electrode and the pixel electrode.

The present invention has an effect of reducing the liquid crystal driving voltage by reducing the thickness of the insulating film between the pixel electrode and the common electrode while overpassing the protective film on which the common electrode is formed, and by making the thickness of the insulating film of the data line region the same as in the conventional case.

Further, the protective film between the common electrodes of the present invention is removed by an over-etching angle, thereby increasing the liquid crystal driving area and improving the device reliability.

1 is a view showing a pixel region of a thin film transistor array substrate according to the present invention.
2A to 2E are views showing a manufacturing process of a thin film transistor array substrate according to the present invention.
3A and 3B are enlarged cross-sectional views of a data line region of the conventional technique and the present invention.
FIG. 4 is a simulation graph showing a state in which the liquid crystal driving voltage decreases according to the degree of overexposure of the protective film according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

Furthermore, in the description of the embodiments, it is to be understood that each pattern, layer, film, region, substrate, or the like is formed "on" or "under" each pattern, layer, film, The terms " on "and " under " all include being formed either" directly "or" indirectly "

In addition, reference to the top, side, or bottom of each component will be described with reference to the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

1 is a view showing a pixel region of a thin film transistor array substrate according to the present invention.

1, the transverse electric field type liquid crystal display device of the present invention is divided into a display region where a plurality of pixel regions are formed and a non-display region where gate pads 120 and data pads 120 are formed, A gate line 101 and a data line 103 are arranged in an intersecting manner to define a sub-pixel region.

A thin film transistor (TFT) as a switching element is disposed in a region where the gate line 101 and the data line 103 intersect. The thin film transistor includes a gate electrode 101a, a source / drain electrode, and a channel layer (not shown) drawn in the direction of the pixel region with a width wider than the gate line 101. [

In the pixel region, a pixel electrode 129 having a plate structure is formed on the substrate in a direction parallel to the data line 103. On the pixel electrode 129, common electrodes 150 formed in a plurality of slit structures are alternately arranged. A common line 151 formed integrally with the common electrode 150 is disposed around the pixel region. The common line 151 overlaps the gate line 101 and the data line 103 along the periphery of the pixel region. In particular, the common line 151 formed on the data line 103 serves as a shield electrode for shielding the electric field.

In particular, in the present invention, the pixel electrodes 129 formed on the substrate are electrically connected by the contact electrodes 300 formed on the protective film. This is because the contact electrode 300 is formed in the second contact hole 232 through the center of the drain electrode of the thin film transistor and the pixel electrode 129 is exposed so that the pixel electrode 129 and the drain electrode of the thin film transistor are electrically Lt; / RTI > Specific drawings and explanations related to this are shown in Figs. 2A to 2E.

The pixel electrode 129 and the common electrode 150 of the present invention are formed in a vertically symmetrical structure along the direction of the data line 103 about the pixel center line parallel to the gate line 101. In addition, the common electrode 150 and the pixel electrode 129 are formed to have a predetermined angle in the vertical direction about the pixel center line.

In addition, although the pixel electrode 129 is formed in the form of a rectangular plate, it is not fixed. Accordingly, the common electrode 150 may have a plurality of slit structures.

In particular, in order to lower the liquid crystal driving voltage while widening the liquid crystal driving area, the protective layer exposed between the common electrode 150 and the common lines shown in FIG. A detailed description thereof will be given in Figs. 2A to 2E.

A gate pad 110 extending from the gate line 101 is formed in the gate pad region of the liquid crystal display device and a gate electrode 110 electrically connected to the gate pad 110 through the first contact hole 231 is formed. A pad contact electrode 310 is formed.

A data pad 120 extending from the data line 103 is formed in a data pad area of the liquid crystal display device and data electrically connected to the data pad 120 through a third contact hole 233 A pad contact electrode 320 is formed.

2A to 2E are views showing a manufacturing process of a thin film transistor array substrate according to the present invention. The lines I-I ', II-II', and III-III 'are lines cut from the gate pad region, the data pad region, and the pixel region in FIG.

2A, a transparent metal film such as indium tin oxide (ITO), indium zinc oxide (ITO), or indium zinc oxide (ITZO) is formed on a lower substrate 100 made of a transparent insulating material. A metal film is deposited by a sputtering method, and a pixel electrode 129 is formed in a pixel region which is a display region in accordance with the first mask process.

Subsequently, a metal film is formed on the lower substrate 100, a gate electrode 101a is formed in the pixel region and the pad region in accordance with the second mask process, and a gate pad (not shown) is formed in the non- 110 and a data pad 120 are formed.

In the second mask process, a photoresist, which is a photosensitive material, is formed on the deposited metal film, a photoresist pattern is formed by an exposure and development process using a mask, and an etching process is performed using the photoresist pattern as a mask .

As described above, in the second mask process, not only the gate electrode 101a and the gate pad 110 but also a gate line (reference numeral 101 in Fig. 1) are formed together.

The metal film formed in the second masking step may be formed of a metal such as molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr) Or a mixture thereof.

When the gate electrode 101a or the like is formed on the lower substrate 100 as described above, the gate insulating film 102, the amorphous silicon film, and the doped amorphous silicon film (n + or p +), and then a third mask process using a diffraction mask or a halftone mask is performed to form a channel layer 114 and a source / drain (not shown) on the gate insulating film 102 over the gate electrode 101a, Electrodes 117a and 117b, and a data line 103 are formed. A semiconductor layer pattern 114a formed by simultaneously etching the semiconductor layer is formed under the data line 103. [

Then, a protective layer 250 is formed on the entire surface of the lower substrate 100.

When the passivation layer 250 is formed on the lower substrate 100 as described above, the gate pad 110 and the data pad 120 formed in the pad region through the fourth mask process, First, third and second contact holes 231, 233 and 232 are formed in the drain electrode 117b region, respectively.

The drain electrode 117b overlaps the pixel electrode 129 formed on the lower substrate 100 and the second contact hole 232 overlaps the center of the drain electrode 117b as shown in FIG. And a part of the pixel electrode 129 is exposed.

At this time, the dry etching process, the wet etching process (etching process for etching the drain electrode), and the dry etching process (the gate insulating film etching process formed on the pixel electrode) can be repeatedly performed.

As described above, when the first, second and third contact holes 231, 232 and 233 are formed on the protective film 250, a transparent conductive material is formed on the lower substrate 100 as shown in FIG. 2D The common line 150, the common line 151, the contact electrode 300, the gate contact electrode 310, and the data contact electrode 320 are simultaneously formed through the fifth mask process. The transparent conductive material may be the same as the material used to form the pixel electrode 129 in the first mask process.

The contact electrode 300 is electrically connected to the pixel electrode 129 through the second contact hole 232 through the drain electrode 117b. That is, the contact electrode 300 is formed along the inside of the second contact hole 232, is laterally contacted with the drain electrode 117b on the side surface of the contact electrode 300, Lt; / RTI >

Accordingly, the contact electrode 300 electrically connects the drain electrode 117b and the pixel electrode 129. [0050]

As described above, when the common electrode 150 is formed, the protective film 250 is over-etched by performing the dry etching process without removing the photoresist pattern used in the etching, as shown in FIG. 2E.

The protective film 250 is removed from the region other than the region where the common electrode 150, the common line 151, the contact electrode 300, the gate contact electrode 310 and the data contact electrode 320 are formed, The stepped region S is formed.

Therefore, a gate insulating layer 102, a protective layer 250, and a liquid crystal layer are interposed between the pixel electrode 129 and the common electrode 150 to form an electric field. The liquid crystal layer has a higher dielectric constant than the SiNx-based protective film 250 and the thickness of the protective film 250 interposed between the common electrode 150 and the pixel electrode 129 is substantially reduced, .

In the present invention, since the distance from the common line 151 overlapping the data line 103 is the same as the conventional distance, the parasitic capacitance along the data line 103 does not increase.

3A and 3B are enlarged cross-sectional views of a data line region of the conventional technique and the present invention.

3A and 3B, a first pixel electrode P1 and a second pixel electrode P2 are formed on a substrate ST, and on the first and second pixel electrodes P1 and P2, (GI) is formed.

A data line DL is formed on the gate insulating layer GI and a first common electrode Vcom1, a second common electrode Vcom2 and a common line SE are formed with a protective film PI therebetween.

3A, a gate insulating layer GI and a protective layer PI are stacked between the first and second pixel electrodes P1 and P2 and the first and second common electrodes Vcom1 and Vcom2.

Therefore, an electric field is formed along the path of C1 between the first and second pixel electrodes P1 and P2 and the first and second common electrodes Vcom1 and Vcom2. Since both the gate insulating film GI and the protective film PI exist in the path of C1, an electric field is applied to the entire protective film PI having a low dielectric constant characteristic, and the liquid crystal driving voltage is increased.

Referring to FIG. 3B, an electric field is formed between the first and second pixel electrodes P1 and P2 and the first and second common electrodes Vcom1 and Vcom2 along the path of C2. C2 can be seen through the gate insulating film (GI), the protective film (PI), and the liquid crystal layer. Further, the thickness of the protective film PI interposed in the C2 path is much thinner than the thickness of the protective film interposed in the prior art due to the overexposure angle.

Therefore, in the pixel structure according to the present invention, since the thin low dielectric constant protective film is interposed between the pixel electrode and the common electrode, and the high-permittivity liquid crystal layer is interposed between the pixel electrode and the common electrode, the liquid crystal can be driven with a low driving voltage.

Further, in the present invention, since the common electrode and the adjacent protective film are over-angled, the region in which the liquid crystal molecules operate by the electric field is widened, and the device reliability can be improved.

In the present invention, since the thickness of the protective film PI interposed between the data line DL and the common line SE is the same, both the prior art and the present invention are equally spaced by the length L. This means that there is little change in parasitic capacitance in the data line (DL) region.

FIG. 4 is a simulation graph showing a state in which the liquid crystal driving voltage decreases according to the degree of overexposure of the protective film according to the present invention.

As shown in FIG. 4, it can be seen that the gamma voltage corresponding to the transmittance curve is sequentially lowered according to the etching thickness of the protective film having the common electrode formed thereon.

For example, when the protective film has a transmittance of 90%, a voltage of 5.2 V is required when the protective film is not over-energized according to the prior art. However, when the overcoat thickness of the protective film is 1000 angstroms, And when it is 2000 Å, a voltage of 4.4 V is required.

As described above, the present invention has the effect of reducing the power consumption by lowering the voltage that can drive the liquid crystal by the common electrode and the pixel electrode, without increasing the parasitic capacitance in the data line region.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

101: gate line 150: common electrode
151: common line 103: data line
129: pixel electrode 250: protective film
300: contact electrode S: step difference region

Claims (9)

Board;
A gate line and a data line cross-arrayed to define a pixel region on the substrate;
A switching element disposed at an intersection of the gate line and the data line and having a gate electrode, a source / drain electrode, and a channel layer;
A pixel electrode arranged in the pixel region in a direction parallel to the data line and having a symmetrical structure vertically with respect to a center of the pixel region;
A common electrode disposed between the pixel electrode and the gate insulating film and the protective film;
A common line disposed between the data line and the protective film; And
And a contact electrode which penetrates through the drain electrode and contacts the side surface of the drain electrode and the surface of the pixel electrode to electrically connect the drain electrode and the pixel electrode,
Wherein a protective layer exposed between the common electrode and the common line has a stepped region formed by an overexposure angle so that the region where the common electrode and the common line are formed and the region where the common line is not formed have different thicknesses,
Wherein the thickness of the overcoat of the protective film is 1000 to 2000 ANGSTROM.
The thin film transistor array substrate according to claim 1, wherein the pixel electrode is formed between the substrate and the gate insulating film.
delete Providing a substrate separated into a display area and a non-display area;
Forming a transparent conductive material on the substrate, and forming a pixel electrode in a pixel region of a display region according to a first mask process;
Forming a metal film on the substrate on which the pixel electrode is formed, and then performing a second mask process to form a gate line, a gate electrode, and a gate pad;
A gate insulating film, a semiconductor layer, and a metal film are sequentially formed on the substrate on which the gate electrode is formed, and then a source / drain electrode, a data line, and a data pad are formed according to a third mask process using a diffraction mask or a halftone mask step;
A first contact hole exposing a part of the gate pad in accordance with a fourth mask process after forming a protective film on the substrate on which the source / drain electrode is formed, and a second contact hole penetrating the center of the drain electrode, Forming a third contact hole exposing a portion of the data pad; And
A transparent conductive material is formed on the substrate on which the first, second, and third contact holes are formed, and then a common electrode is formed on the protective film over the pixel electrode and a common electrode Forming a line integrally and simultaneously forming a contact electrode electrically connecting the drain electrode and the pixel electrode,
The contact electrode is formed inside the second contact hole through the center of the drain electrode to expose the pixel electrode on the lower side and is in contact with the side surface of the drain electrode and the surface of the pixel electrode, Respectively,
The step of forming the common electrode may further include the step of forming the common electrode and continuing the etching process so as to overcoat the adjacent protective film of the common line and the common line,
Wherein a stepped region is formed by an overexposed portion of the protective film exposed between the common electrode and the common line by overexposing the protective film so that the regions where the common line and the common line are formed and the regions where the common line is not formed have a thickness Different,
Wherein the overcoat thickness of the protective layer is 1000 to 2000 ANGSTROM.
delete delete 5. The method of claim 4,
In forming the first, second, and third contact holes,
And a second contact hole is formed through the dry etching process, the wet etching process and the dry etching process repeatedly in the case of the second contact hole passing through the center of the drain electrode.
The method of claim 4, wherein a gate insulating film, a protective film, and a liquid crystal layer interposed between the common electrode and the gate electrode are interposed between the common electrode and the pixel electrode.
9. The method according to claim 8, wherein the dielectric constant of the liquid crystal layer is higher than the dielectric constant of the protective film.

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