TWI476864B - Thin film transistor array substrate, liquid crystal display device comprising the same and fabricating methods thereof - Google Patents

Description

Thin film transistor array substrate and liquid crystal display device having the same and manufacturing method thereof

The present invention relates to a liquid crystal display device (LCD) having an organic insulating film.

Generally, a liquid crystal display device (LCD) uses an electric field to control the transmittance of a liquid crystal having dielectric anisotropy to realize an image. A liquid crystal display device (LCD) is typically fabricated by combining a color filter array substrate with a thin film transistor array substrate and a liquid crystal layer between the two substrates.

Recently, several new types of liquid crystal display devices (LCDs) are being developed to solve the narrow viewing angle of a liquid crystal display device (LCD) of the prior art. A liquid crystal display device (LCD) having a wide viewing angle is classified into an In-Plane Switching (IPS) type, an Optically Compensated Birefringence (OCB) type, and a Fringe Field Switching (Fringe Field Switching). FFS), or other types.

Among these liquid crystal display devices (LCDs) having a wide viewing angle, a planar switching (IPS) type liquid crystal display device (LCD) allows a pixel electrode and a common electrode to be arranged on the same substrate so that between the electrodes A horizontal electric field is sensed. Thus, the major axes of the liquid crystal molecules are aligned in a horizontal direction with respect to the substrate. Therefore, a planar switching (IPS) type liquid crystal display device (LCD) has a wider viewing angle than a twisted nematic (TN) type liquid crystal display device (LCD) of the prior art.

"FIG. 1" is a schematic diagram of a pixel structure in a planar switching (IPS) type liquid crystal display device (LCD) of the prior art. "Picture 2" is a cross-sectional view of a pixel structure along the I-I' of "Fig. 1".

Referring to "Fig. 1" and "Fig. 2", a gate line 1 and a data line 5 intersect each other to define a pixel area. A thin film transistor TFT used as a switching element is located at the intersection of the gate line and one of the data lines 1 and 5.

Above the pixel area, a first common line 3 opposite the gate line 1 intersects the data line 5. The plurality of first common electrodes 3a are parallel to the data line 5 and branched from the first common line 3, and are formed on both sides of the pixel area.

The gate line 1 includes a gate 1a having a certain width. A first storage electrode 6 is adjacent to the gate 1a. The first storage electrode 6 and the first common electrode 3a are formed as a single body.

Moreover, a second common line 13 for making electrical contact with the first common line 3 is formed above the first common line 3. A second common electrode 13a formed over the pixel region branches off from the second common line 13. Further, a plurality of third common electrodes 13b overlapping the first common electrode 3a portion are branched from the second common line 13.

The second common electrode 13a and the plurality of pixel electrodes 7a are alternately arranged in the pixel region. These pixel electrodes 7a are branched from the second storage electrode 7 overlapping the first storage electrode 6.

"Fig. 2" shows a cross section along the line I-I' of "Fig. 1". In the "Fig. 2", in the region of a data line 5, a gate insulating film 12 is formed at the bottom. Above the substrate 10. The data line 5 is formed on the gate insulating film 12. The first common electrode 3a arranged on both sides of the data line 5 is formed on the base substrate 10. The third common electrode 13b is formed over a protective (or passivation) film 19 and overlaps the first common electrode 3a portion.

The color array substrate includes a black matrix 21 opposite to the data line 5. The black matrix 21 is formed on a top substrate 20. A red (R) filter layer 25a and a green (G) filter layer 25b are formed on both sides of the black matrix 21. 〞29〞 indicates an outer coating.

Such a conventional planar switching (IPS) type liquid crystal display device (LCD) forces the width L1 of the black matrix 21 to become larger to prevent generation of light generated in the backlight unit and passing around the edge of the pixel region. Light leaks. More specifically, the black matrix 21 is formed to reach one of the edges of the first common electrode 3a so as to intercept the passage between the data line 5 and the first common electrode 3a in an oblique direction having at least a constant angle with respect to a vertical line. The light that passed. Thereby, the aperture ratio of the pixel region is reduced.

Further, since the pixel electrodes and the common electrode arranged in the pixel region are formed in a single metal layer, it is difficult to increase the aperture ratio of the pixel region by reducing the width of the electrode.

Accordingly, in view of the above, embodiments of the present invention are directed to a liquid crystal display device (LCD) to eliminate one or more problems due to limitations and disadvantages of the prior art.

One of the objects of the present invention is to provide a thin film transistor array substrate, a liquid crystal display device having the same, and a manufacturing method thereof, which are suitable for increasing an aperture ratio by forming a common electrode overlapping a data line on a substrate.

An object of the present invention is to provide a thin film transistor array substrate, a liquid crystal display device having the same, and a manufacturing method thereof, which are adapted to reduce parasitic capacitance by disposing an organic insulating film between a data line and a common electrode. .

Another object of the present invention is to provide a thin film transistor array substrate, a liquid crystal display device having the same, and a manufacturing method thereof, which are suitable for forming a common electrode and a pixel electrode including a fine width of an electrode, the common electrode and the pixel The electrodes are arranged on the top portion of the substrate and formed as a double laminated metal layer.

It is still another object of the present invention to provide a liquid crystal display device and a method of fabricating the same that are adapted to provide an aperture ratio by removing a black matrix opposite a data line from a color filter substrate.

Further, another object of the present invention is to provide a thin film transistor array substrate, a liquid crystal display device having the same, and a method of fabricating the same, which can easily perform a black spot repair process without removing an organic insulating film.

Other features and advantages of the invention will be set forth in part in the description which follows. The objectives and other advantages of the invention will be realized and attained by the <RTI

According to a general object of the present invention, a thin film transistor array substrate includes a substrate defined as a display area and a non-display area; a gate line and a data line are arranged to cross each other to be displayed on the substrate. A pixel region is defined; a first common line formed parallel to the gate line and intersecting the data line; a plurality of first common electrodes formed on both sides of the data line and from the data line a parallel first common line extending; a switching element located at an intersection of the gate line and the data line; a first pixel electrode formed parallel to the gate line; a second pixel electrode And extending from the first pixel electrode and parallel to the data line; a second common line opposite to the first common line in the pixel region; and a second common electrode facing the second common line a third common electrode extending from the second common line and overlapping the data line, the third common electrode being covered with an organic insulating film between the third common electrode and the data line, and being in the data line First common electricity Between the spaced apart; a first storage electrode, which extends from the first region to a pixel in the common line; and a second storage electrode formed to overlap the first storage electrode.

A method for fabricating a thin film transistor array substrate comprises the steps of: providing a substrate defining a display region and a non-display region; forming a first metal layer on the substrate and passing through a first mask process The first metal layer is patterned into a gate, a gate line, and a first common electrode arranged on the display area, and a gate pad arranged on the non-display area; sequentially forming a gate insulation a film, a semiconductor layer, and a second metal layer on the substrate and forming a source/drain, a second storage electrode, a channel layer, and a second metal layer and the semiconductor layer through a second mask process a data line; a protective film and an organic insulating film are sequentially formed on the substrate, and a pattern of the organic insulating film is formed by performing a exposure and development step according to a third mask process; and using a gas having a different oxygen content ratio, sequentially performing the first a first and a second etching step, wherein the patterned organic insulating film in the first and second etching steps is used as an etch mask for use in a drain region, a gate pad region, and a capital Forming a plurality of contact holes in the pad region; and sequentially forming a third metal layer and a fourth metal layer on the organic insulating film having the contact holes, and then passing the third metal layer through a fourth mask process And forming a fourth metal layer into a pixel electrode and a second common electrode.

Other systems, methods, features, and advantages of the invention will be apparent to those skilled in the <RTIgt; Advantages are included in the description, are included in the scope of the present invention, and are protected by the scope of the patent application. The internal part of this section should not be construed as limiting the scope of the patent application. Further aspects and advantages will be discussed in the following embodiments. It is to be understood that the foregoing general description of the invention and the claims

Embodiments of the present invention will be described in detail below in conjunction with the drawings. The embodiments described below are intended to convey the spirit of the present invention to those of ordinary skill in the art. Thus, these embodiments can be implemented in different shapes and are not limited to the embodiments described herein.

Moreover, it will be understood that in an embodiment of the invention, when an element, such as a substrate, a layer, a region, a film, or an electrode, is referred to as being formed on top of another element, 〞 or 〞 It may be located directly above or below this other component or may have an intermediate (indirect) component. The terms of a component, 〞 or 〞, will be determined according to the schema. In the drawings, the sides of the elements are exaggerated for clarity, but they do not represent the actual dimensions of these elements.

Fig. 3A is a schematic view showing a pixel area of a liquid crystal display device (LCD) according to the first embodiment of the present invention. Fig. 3B is a cross-sectional view of a liquid crystal display device (LCD) along the II-II' line and the III-III' line of "Fig. 3A".

Referring to FIG. 3A, a liquid crystal display device (LCD) according to a first embodiment of the present invention includes a pixel region defined by a gate line 101 intersecting with a data line 103. A thin film transistor TFT is located at the intersection of the gate line 101 and the data line 103.

A first common line 130 is parallel to the gate line 101 at a position adjacent to the gate line 101. The first common line 130 also intersects the data line 103.

The gate line 101 has a widened width at a position (region) crossing the data line 103, and this widened width is used as one of the gate electrodes 101a of the thin film transistor TFT. Therefore, the gate 101a and the gate line 101 are formed as a single body.

Among the regions where the thin film transistor TFT is formed, a first storage electrode 140 is formed to protrude from the first common line 130 toward the pixel region. A second storage electrode 129 is formed on the first storage electrode 140 in such a manner as to overlap with the first storage electrode 140. The first and second storage electrodes 140 and 129 are used to form a storage capacitor. Although the first and second storage electrodes 140 and 129 are formed in a rectangular shape, the first and second storage electrodes 140 and 129 can be formed into different shapes according to a desired capacitance value, such as an ellipse, a triangle, and Other shapes.

The first common electrode 131 is arranged on both sides of the pixel area. The first common electrode 131 branches off from the first common line 130 in parallel with the data line 103. The first common electrode 131 is adjacent to the first common line 130. The first common electrode 131 on one side (for example, the left side) is also formed adjacent to the data line 103. (As described in connection with the cross-sectional view, the first common electrode 131 having two in one pixel region is formed on both sides of the data line 103. Therefore, it can be said that the first common electrode 131 is adjacent to the data line 103).

Among the pixel regions, a first pixel electrode 119 is formed to overlap the first common line 130, and a plurality of second pixel electrodes are parallel to the data line 103 from the first pixel electrode 119 toward the pixel region. Expenditure. Each of the second pixel electrodes 139 is formed in a fine strip shape in the pixel region. The second pixel electrodes 139 are arranged in a pixel region at regular intervals. The first pixel electrode 119 and the second storage electrode 129 are formed as a single body. Therefore, the second pixel electrode 139 branches off from the second storage electrode 129. In addition, the second storage electrode 129 is electrically connected to one of the thin film transistors TFT through the first contact hole 230.

Moreover, a second common line 132 is formed to face the first common line 130 in the center of the pixel area. A plurality of second common electrodes 134 are branched from the second common line 132 toward the pixel region in parallel with the data line 103. Each of the second common electrodes 134 is formed in a strip shape.

The second common electrode 134 and the second pixel electrode 139 are alternately arranged in the pixel region. The second common line 132 is electrically connected to the terminal portion of the first common electrode 131 branched from the first common line 130 through a fourth contact hole 233.

A third common electrode 133 branches off from one end of the second common line 132 in such a manner as to overlap the data line 103. The third common electrode 133 prevents light generated in the backlight unit (not shown) and generated by light of a region of the data line 103 from leaking. Moreover, the third common electrode prevents external light from being reflected on its surface. To this end, the third common electrode 133 is formed of a material having a low light reflectance.

At the same time, a gate pad 110 connected to the gate line 101 is formed in a pad region of a liquid crystal display device (LCD). A gate pad contact electrode 310 is formed over the pad pad 110. The gate pad contact electrode 310 is in electrical contact with the gate pad 110 through the second contact hole 231.

In addition, a data pad 120 connected to the data line 103 is also formed in the pad area. A data pad contact electrode 320 is formed over the data pad 120. The data pad contact electrode 320 is in electrical contact with the data pad 120.

Referring to FIG. 3A and FIG. 3B, the gate 101a, the first storage electrode 140, and the plurality of first common electrodes 131 are formed in a display region of the base substrate 100, wherein the substrate is transparent. An insulating material is formed. The gate pad 110 is formed in the pad region corresponding to the non-display area of the base substrate 100. Since the gate 101a functions as one of the electrodes of the thin film transistor TFT, the gate 101a has a width wider than that of the gate line 101.

A channel layer 114 and source/drain electrodes 117a and 117b are formed on the gate electrode 101a at the center of the gate insulating film 102. The data line 103 is formed over the gate insulating film 102 between the first common electrodes 131 (see the cross section along the line II-II').

A protective (or passivation) film 109 and an organic insulating film 150 are sequentially formed on the base substrate 100, wherein the base substrate 100 has source/drain electrodes 117a and 117b and data lines 103. The second storage electrode 129 is formed on the organic insulating film 150 opposite to the first storage electrode 140. The first storage electrode 140 is electrically connected to the drain 117b through the first contact hole 230. The third common electrode 133 is formed on the organic insulating film 150 opposite to the data line 103. Further, the second pixel electrode 139 and the second common electrode 134 are alternately arranged on the organic insulating film 150 in the pixel region.

Moreover, a gate pad 110 connected to the gate line 101 is formed over a gate pad region. The gate insulating film 102, the protective film 109, and the organic insulating film 150 are sequentially formed. A pad contact electrode 310 electrically connected to the gate pad 110 through the second contact hole 231 is formed over the organic insulating film 150.

Further, a gate insulating film 102 is formed over one of the material pad regions of the base substrate 100. A data pad 120 extending from the data line 103 is formed over the gate insulating film 102. The protective film 109 and the organic insulating film 150 are sequentially formed on the data pad 120. A material pad contact electrode 320 electrically connected to the material pad 120 through the third contact hole 232 is formed over the organic insulating film 150. In addition, the channel layer pattern 114a remains under the data pad 120 and the data line 103. This is due to the fact that a metal film and a channel layer are continuously etched during an etching process using a diffractive reticle or a halftone reticle.

After the organic insulating film 150 is formed, the formed second storage electrode 129, second pixel electrode 139, second common electrode 134, third common electrode 133, gate pad contact electrode 310, and data pad contact electrode 320 have A double metal layer structure. More specifically, the second storage electrode 129 includes a top storage electrode layer 129a and a bottom storage electrode layer 129b. Each of the second pixel electrodes 139 includes a top pixel electrode layer 139a and a bottom pixel electrode layer 139b. Each of the second common electrodes 134 includes a top common electrode layer 134a and a bottom common electrode layer 134b. The third common electrode 133 includes a top common electrode layer 133a and a bottom common electrode layer 133b. The gate pad contact electrode 310 includes a top gate pad contact electrode layer 310a and a bottom pad pad contact electrode layer 310b. Finally, the data pad contact electrode 320 includes a top data pad contact electrode layer 320a and a bottom data pad contact electrode layer 320b.

Although not shown, the first pixel electrode 119 and the second common line 132 are also formed in a double metal layer structure.

The bottom layer of the second storage electrode 129, the second pixel electrode 139, the second common electrode 134, the third common electrode 133, the gate pad contact electrode 310, and the data pad contact electrode 320 may be composed of molybdenum (Mo) or titanium (Ti). A material selected from the group consisting of tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, and combinations thereof. For example, these underlayers can be formed from a molybdenum-titanium alloy (MoTi). On the other hand, the top layer of the second storage electrode 129, the second pixel electrode 139, the second common electrode 134, the third common electrode 133, the gate pad contact electrode 310, and the data pad contact electrode 320 can be self-made from a copper-nickel alloy ( CuNx) is formed which has a low reflection property and a high conductivity property.

If the copper-nickel alloy (CuNx) is used to form the second storage electrode 129, the second pixel electrode 139, the second common electrode 134, the third common electrode 133, the gate pad contact electrode 310, and the data pad contact electrode 320 In the top layer, the third common electrode 133 located above the data line 103 can shield the light source from the light source toward the outside and can reduce the reflectance of the external light. Therefore, deterioration of the picture quality caused by the light leakage defect and the external light diffuse reflection can be prevented.

Generally, molybdenum-titanium alloy (MoTi) is a metal that is not easily corroded. However, when the second storage electrode 129, the second pixel electrode 139, the second common electrode 134, the third common electrode 133, the gate pad contact electrode 310, and the material pad contact electrode 320 are both formed in the structure of the bimetal layer The galvanic effect is generated by the electrons recovered from the underlying molybdenum-nickel alloy (MoNx) due to the copper-nickel alloy (CuNx) on the top layer. Thus, a fine electrode can be formed by using the above-described gamma effect. In other words, each of the second pixel electrodes 139 and the second common electrode 134 having a strip shape can be formed into a fine width by being formed by two metal layers different from each other.

The organic insulating film 150 is formed of a material having a lower dielectric constant than the protective film 109. The organic insulating film 150 has a dielectric constant of about 3.0 to 4.0. Preferably, the organic insulating film 150 has a dielectric constant of about 3.4 to 3.8. Moreover, the organic insulating film 150 can be in the range of 3.5 to 6.0 micrometers (μm). Preferably, the organic insulating film 150 has a thickness ranging from about 3.5 to 6.0 micrometers (μm). Alternatively, the organic insulating film 150 can be designed to have different thicknesses according to the driving frequency of a liquid crystal display device (LCD) to be described below.

Moreover, the organic insulating film 150 can be formed of a propionate alkenyl resin. The propionate alkenyl resin contains a photo propylene, but is not limited thereto. In other words, if the material of the organic insulating film 150 has a low dielectric constant, the organic insulating material is not limited to photo propylene. The organic insulating film 150 formed of a low dielectric constant can reduce the parasitic capacitance generated between the data line 103 and the third common electrode 133 and can further reduce the load of the data line 103.

In fact, the third common electrode 133 of the present embodiment can be located above the data line 103. Thereby, the parasitic capacitance can be generated between the second pixel electrodes 139 adjacent to the data line 103. In this case, the organic insulating film 150 having the above dielectric constant characteristics can reduce the parasitic capacitance.

In detail, the third common electrode 133 shields an electric field generated between the data line 103 and the second pixel electrode adjacent to the data line 103, and between the second pixel electrodes adjacent to the data line 103. . As the third common electrode 133 is closer to the data line 103, the masking function of the third common electrode 133 becomes superior. However, the parasitic capacitance is also increased more. In order to solve this problem, it is preferable that the organic insulating film 150 has a dielectric constant as low as possible.

Moreover, the organic insulating film 150 can be formed to have different thicknesses depending on the driving of the liquid crystal display device (LCD). The third common electrode 133 formed on the organic insulating film 150 opposite to the data line 103 in this embodiment causes the parasitic capacitance to be generated between the third common electrode 133 and the data line 103 when a data voltage having a different voltage value is generated. When continuously applied to the data line 103, such a parasitic capacitance produces a coupling effect between the third common electrode 133 and the data line 103.

As the driving frequency becomes higher, the coupling effect generated between the data line 103 and the third common electrode 133 causes the data voltage to be delayed over the data line 103. The application of the low dielectric constant organic insulating film 150 of the present embodiment reduces the parasitic capacitance between the data line 103 and the third common electrode 133. Therefore, it is possible to prevent the delay of the signal.

More specifically, the parasitic capacitance is inversely proportional to the distance between the data line 103 and the third common electrode 133. Therefore, the parasitic capacitance decreases as the thickness of the organic insulating film 150 increases. As a result, the signal delay caused by the coupling effect between the data line 103 and the third common electrode 133 can be reduced.

For example, if the driving frequency of the liquid crystal display device (LCD) is set to 120 Hz, the thickness of the organic insulating film 150 can be in the range of about 2.5 to 3.5 micrometers (μm). Alternatively, when the liquid crystal display device (LCD) has a driving frequency of 240 Hz, the thickness of the organic insulating film 150 can be in the range of about 5.5 to 6.5 micrometers (μm). Thus, since the thickness value is not set to a fixed value when designing a liquid crystal display device (LCD), it can be different depending on the specifications of the liquid crystal display device (LCD). Moreover, it is necessary to change the position of the third common electrode 133 to prevent light leakage and increase the aperture ratio. In this case, the organic insulating film 150 can be thinner or thicker depending on the driving frequency.

"4A" to "4G" are cross-sectional views of a thin film transistor substrate along the II-II' and III-III' lines of "Fig. 3A" and are used to explain the thin film transistor array substrate. Manufacturing method.

Referring to "Ath 4A" to "4G", a metal film is deposited on a base substrate 100 of a transparent insulating material by a sputtering method. Then, a first mask process is performed on the metal film.

In the first mask process, a photoresist having a photosensitive material is first formed on the deposited metal film. The photoresist is exposed and developed using a mask defining a transmissive region and a non-transmissive region, thereby providing a photoresist pattern. Thereafter, the metal film is etched using the photoresist pattern as a mask to form a gate 101a, a first storage electrode 140, a plurality of first common electrodes 131, and a gate pad 110. Although not shown, a gate line (101 in "3A") and a first common line (130 in "3A") are formed at the same time. The gate line 101 and the gate 101a are formed as a single body. The first common line (130 in FIG. 3A) is formed as a single body with the first common electrode 131 and the first storage electrode 140 (actually, the first common electrode 131 and the first storage electrode 140 are common to the first Line 130 is formed, see paragraphs 0057 and 0056, and gate 101a is formed from gate line 101 and is actually part of gate line 101, see paragraph 0055).

The metal film can be selected from the group consisting of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, and combinations thereof. A material is formed. Although the metal film is formed in a single layer in the drawing, the metal film can be formed by stacking at least two metal layers as needed.

After the electrodes and pads are formed on the base substrate 100, as shown in FIG. 4B, an amorphous germanium film gate insulating film 102 and a doped amorphous germanium film (n+ or p+) semiconductor layer are formed. 124 is sequentially formed on the base substrate 100 having the gate 101a, the first storage electrode 140, the first common electrode 131, and the gate pad 110. Subsequently, a source/drain metal film 127 is formed over the semiconductor layer 124.

The source/drain metal film 127 can be composed of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, and One of the materials selected from the composition is formed. Further, a transparent conductive material such as Indium Tin Oxide (ITO) can be used as the source/drain metal film 127. Moreover, although the source/drain metal film is formed as a single layer in the drawing, the source/drain metal film can be formed by stacking at least two metal layers as needed.

As shown in FIG. 4C, a second mask process is performed on the base substrate 100 covering the source/drain metal film 127 using one of a halftone mask and a diffractive mask to form a source/ The drain electrodes 117a and 117b, a data line 103, a data pad 120, and a channel layer 114 (similar to "3B", a reference numeral 114 in "4C" indicates a channel layer 114).

The second mask process allows sequential etching of the source/drain metal film 127 and the semiconductor layer 124 under the source/drain metal film 127. Thus, the channel layer 114 is formed under the source/drain electrodes 117a and 117b to have a size corresponding to the source/drain electrodes 117a and 117b. The channel layer 114 is also formed under the data line 103 and the data pad 120 and has a size corresponding to the data line 103 and the data pad 120.

Moreover, the drain 117b is formed to overlap the first storage electrode 140. Therefore, a storage capacitor is formed.

Thereafter, as shown in "4D", a protective film 109 and an organic insulating film 150 are sequentially formed on the base substrate 100 having the above structure.

The organic insulating film 150 has a lower dielectric constant than the protective film 109. The organic insulating film 150 can have a dielectric constant of about 3.0 to 4.0. Preferably, the organic insulating film 150 has a dielectric constant of about 3.4 to 3.8. Alternatively, as described above (see "3A" and "3B"), the organic insulating film 150 can be designed to have different thicknesses depending on the driving frequency of the liquid crystal display device (LCD).

Further, the organic insulating film 150 can be formed of a propionate alkenyl resin. The propionate alkenyl resin contains a photo propylene, but is not limited thereto. In other words, if the material of the organic insulating film 150 has a low dielectric constant, the organic insulating material is not limited to photo propylene.

As shown in FIG. 4E and FIG. 4F, a third mask process is performed on the base substrate 100 covered with the organic insulating film 150 by using a mask 300 having a transmissive area P1 and a non-transmissive area P2. .

The third mask process allows the organic insulating film 150 to be patterned through the exposure and development steps. Moreover, the third mask process allows an etching step to be performed using the patterned organic insulating film 150 as an etch mask. Thus, a plurality of portions of the contact holes exposing the drain 117b, the gate pad 110, and the data pad 120 are formed.

The contact holes include a first contact hole 230 formed opposite to the drain 117b, a second contact hole 231 formed opposite the gate pad 110, and a third contact hole 232 formed opposite the data pad 120. . Meanwhile, although not shown, a fourth contact hole 233 is formed.

The second contact hole 231 partially exposes the gate pad 110, and the first contact hole 230 and the third contact hole 232 partially expose the protective film 109 only. Thus, the present embodiment of the invention allows the etching step to be performed twice at a location opposite the gate pad 110. Although not shown, the fourth contact hole 233 is formed in the same structure as the second contact hole 231 such that the second common line 132 is electrically connected to the first common electrode 131. At this point, it is necessary to perform the etching step twice at a position opposite to the fourth contact hole 233. These two etching steps will be explained in detail later in conjunction with "6A" to "6C".

Then, as shown in the "figure 4G", the first and second metal films are sequentially formed on the organic insulating film 150 in which the first to fourth contact holes 230 to 233 are formed, before the fourth mask process is performed. on.

The fourth mask process allows sequential coating, exposure, development, and etching steps to be performed such that a second storage electrode 129, a plurality of second pixel electrodes 139, a plurality of second common electrodes 134, and a third common electrode 133. A gate pad contact electrode 310 and a data pad contact electrode 320 are formed in a double metal layer structure. Meanwhile, although not shown, the first pixel electrode 119 and the second common line 132 shown in "FIG. 3A" are formed.

The first metal film can be composed of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, and combinations thereof A material of choice is formed. For example, a molybdenum-titanium alloy (MoTi) can be used as the first metal film. On the other hand, the second metal film can be formed of a metal having a low reflection property and high conductivity. For example, copper nitride (CuNx) can be used as the second metal film.

Thus, the second storage electrode 129 includes a top storage electrode layer 129a and a bottom storage electrode layer 129b. Each of the second pixel electrodes 139 includes a top pixel electrode layer 139a and a bottom pixel electrode layer 139b. Each of the second common electrodes 134 includes a top common electrode layer 134a and a bottom common electrode layer 134b. The third common electrode 133 includes a top common electrode layer 133a and a bottom common electrode layer 133b. The gate pad contact electrode 310 includes a top gate pad contact electrode layer 310a and a bottom pad pad contact electrode layer 310b. Finally, the data pad contact electrode 320 includes a top data pad contact electrode layer 320a and a bottom data pad contact electrode layer 320b.

Although not shown, the first pixel electrode 119 and the second common line 132 shown in "Fig. 3A" are also formed in a bimetal layer structure.

Moreover, due to the bimetal structure, the second pixel electrode 139 and the second common electrode 134 formed over the pixel region can be formed to have a fine width.

"5A" and "5B" are schematic diagrams for explaining the problems occurring when the etching method of the prior art is applied to the contact hole manufacturing process of the present embodiment.

Referring to FIG. 5A and FIG. 5B, the thin film transistor array substrate of the present embodiment includes a gate pad 110 formed in the gate pad region of the base substrate 100. The thin film transistor array substrate further includes a gate insulating film 102, a protective film 109, and an organic insulating film 150 formed over the gate pad 110.

To expose the gate pad 110, a conventional dry etching process is used. Moreover, after the exposure and development process, the residue of the organic insulating film 150 remains in the holes. Therefore, the inner surface of the hole becomes rough due to the residue of the organic insulating film 150.

As shown in "Fig. 5A", the residue of the organic insulating film 150 forces a cut structure to be formed in the bottom of the organic insulating film 150. In other words, a step covering structure is formed among the organic insulating film 150, the protective film 109, and the gate insulating film 102.

As shown in "Fig. 5B", the step covering structure generated inside the hole will break in a metal film 180 which is formed later. Actually, electrical disconnection can be generated in the gate pad contact electrode formed in the gate pad region of the present embodiment by the step coverage formed on the inner side wall of the contact hole. The metal film 180 can have a structure in which at least two metal layers are stacked.

To solve this problem, when forming such a contact hole, the present embodiment can change the content ratio of an etching gas and perform two etching processes.

"Fig. 6A" to "6C" are schematic views for explaining an etching process during the manufacture of the contact hole of this embodiment.

As shown in "6A" to "6C", the gate pad 110 is formed on the base substrate 100. Thereafter, the gate insulating film 102, the protective film 109, and the organic insulating film 150 are sequentially formed over the gate pad 110.

Before performing a first etching process, the organic insulating film 150 is patterned through a mask process, and the patterned organic insulating film is used as a mask during the first etching process. The flow ratio of the SF6:O2 etching gas used in the first etching process can be in the range of about 1:2.0-1:3.0. Preferably, the SF6:O2 etching gas has a flow rate of about 1:2.5. For example, if SF6 corresponds to 4000, O2 may be in the range of 10000 to 12000.

Subsequently, the flow ratio of the etching gas of SF6:O2 is changed and then a second etching process is performed. At this time, the flow ratio of the SF6:O2 etching gas can be in the range of about 1:2.4-1:3.0. Preferably, SF6:O2 is set to a flow ratio of approximately 1:2.5.

In other words, if the content of oxygen (O2) increases during the first and second etching processes, the roughness of the inner surface increases. Thus, the time during which the second etching process is performed is preferably equal to or shorter than the time during which the first etching process is performed.

As shown in "Fig. 6B", the first and second inclined surfaces S1 and S2 of the contact hole of the gate pad 110 are formed as a smooth surface. Thus, no step coverage occurs in the organic insulating film 150, the protective film 109, and the gate insulating film 102.

Further, as shown in "Fig. 6C", although the metal film 180 is formed on the base substrate 100, the disconnection in the metal film 180 does not occur in the contact holes of the gate pad 110.

Thus, the third mask process of the present embodiment performs the etching process twice, and as a result, the step coverage on the inner surface of the contact hole can be eliminated.

"Fig. 7" and "Fig. 8" are schematic views showing the cross-sectional structure of the color filter substrate corresponding to the IV-IV' line in "Fig. 3".

Referring to FIG. 7 and FIG. 8, the cross-sectional structure of the color filter array substrate of this embodiment is formed to be opposite to the area of the data line 103.

A plurality of first common electrodes 131 are formed on the base substrate on both sides of the data line 103. The gate insulating film 102 is formed between the data line 103 and the first common electrode 131. The protective film 109 and the organic insulating film 150 are sequentially formed between the data line 103 and the third common electrode 133.

The third common electrode 133 located above the data line 103 serves to shield the light from the light source of the backlight unit below the base substrate 100 to the light of a top substrate 200. The third common electrode 133 has a top common electrode layer 133a and a bottom common electrode layer 133b. The bottom common electrode 133b is selected from the group consisting of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), alloys thereof, and combinations thereof. A material is formed. The top common electrode layer 133a can be formed from copper nitride (CuNx) having a low reflection property and high conductivity.

Such a third common electrode 133 shields light entering from the rear surface of the base substrate 100, thereby preventing light leakage. Moreover, the third common electrode 133 prevents reflection of light entering from the outside of the top substrate 200 having a color filter layer.

In this manner, the third common electrode 133 formed of a material capable of shielding light is placed above the data line 103. Thus, the width L2 of a black matrix 204 formed over the top substrate 200 can be reduced. Therefore, as the width of the black matrix 204 decreases, the aperture ratio of the pixel region increases.

The black matrix 204 of the top substrate 200 opposite to the third common electrode 133 can be formed to be narrower than the distance between the first common electrodes 131. Moreover, the width of the black matrix 204 can be formed to have a width ranging from the width of the width data line 103 to the distance between the first common electrodes 131.

The reduced width of the black matrix 204 allows a color filter layer, such as a red (R) filter layer 203a and a green (G) filter layer 203b, to be formed between the black matrix 204 to have a wider width (ie, Enlarged size). Therefore, the aperture ratio of the pixel area is increased.

As shown in Fig. 8, the color filter array substrate of this embodiment is arranged without a black matrix. This is due to the fact that light is shielded through the third common electrode 133. In this manner, since the black matrix 204 is removed, the manufacturing process of the color filter array substrate of the liquid crystal display device (LCD) can be reduced.

In addition, the aperture ratio of the pixel area can be increased. Although not shown, the reference numerals 114a and 209 209 which are not described respectively indicate a channel layer pattern and an overcoat layer.

Moreover, the parasitic capacitance can be increased through the third common electrode 133 above the data line 103. The organic insulating film 150 is formed of a material having a lower dielectric constant than that of the protective film 109, and the organic insulating film 150 can reduce parasitic capacitance.

As described above, the liquid crystal display device (LCD) of the first embodiment of the present invention and the method of manufacturing the same can be applied completely or selectively to other embodiments in the same manner. Therefore, the description of the first embodiment described above will be applied to the following other embodiments in the same manner.

Fig. 9A is a schematic view showing a pixel area in a liquid crystal display device (LCD) according to a second embodiment of the present invention. "Fig. 9B" is an enlarged view of a thin film transistor shown in "Fig. 9A".

The liquid crystal display device (LCD) of the second embodiment shown in "Fig. 9A" and "Fig. 9B" is provided in the same manner as the first embodiment. Therefore, the same components of the liquid crystal display device (LCD) of the second embodiment as those of the liquid crystal display device (LCD) of the first embodiment shown in "3A" and "3B" are denoted by the same reference numerals. Moreover, the portion of the second embodiment that is different from the first embodiment will be mainly described.

Referring to FIG. 9A and FIG. 9B, a liquid crystal display device (LCD) according to a second embodiment of the present invention causes the drain 117b of a thin film transistor TFT and the first common line 430 not to cross each other. Therefore, the liquid crystal display device (LCD) of the second embodiment can easily perform a pixel repair process.

Among the pixel regions in which the thin film transistor TFT is formed, the first common line 430 is parallel to the gate line 101. The first common line 430 has a bent portion 440 at a position where the drain 117b of the thin film transistor TFT is formed. The curved portion 440 does not overlap the drain 117b.

As described above, if the first common line 430 does not overlap with the drain 117b, a storage capacitor can be formed among the pixel regions. In order to solve this problem, the liquid crystal display device (LCD) of the second embodiment allows a first storage electrode 441 to be formed in the pixel region opposite to the curved portion 440 of the first common line 430. The first storage electrode 441 and the first common line 430 are formed as a single body.

Moreover, the second storage electrode 249 is formed to overlap the first common line 430 and the first storage electrode 441. The second storage electrode 249 and the source/drain electrodes 117a and 117b are formed of the same metal layer.

Moreover, a first pixel electrode 219 is parallel to the gate line 101 and the first common line 430. The first pixel electrode 219 includes a first extension portion 229 and a second extension portion 239 at both ends thereof. The first expanded portion 229 is electrically connected to the drain 117b through a first contact hole 230 and is formed not to overlap the curved portion 440 of the first common line 430.

In this manner, the liquid crystal display device (LCD) of the second embodiment allows the first extension portion 229 (the first extension portion 229 is a portion of the first pixel electrode 219 and is electrically connected to the drain electrode 117b). The center of the cutting line C1 for pixel repair is spaced from the curved portion 440 of the first common line 430. Therefore, even in the case where the first pixel electrode 219 and the second pixel electrode 139 are cut along the cutting line C1 by a laser beam to repair the pixels, the first common line 430 is not connected to the first pixel electrode 219 (or Bungee 117b) Electrical short circuit.

Further, the first and second pixel electrodes 219 and 139 are arranged on the organic insulating film. Therefore, there is no need for a repair process for opening the organic insulating film. In other words, the liquid crystal display device (LCD) of the second embodiment of the present invention allows the repair process to be performed without removing the organic insulating film, and in the pixel repair process of the prior art, before cutting the bungee The case where the organic insulating film must be removed is different.

The second extension portion 239 included in the second embodiment of the present invention is formed to extend from the first pixel electrode 219 and overlap the first storage electrode 441. The second extension portion 239 is electrically connected to the second storage electrode 249. Therefore, the liquid crystal display device (LCD) of the second embodiment of the present invention includes a storage capacitor formed between the first common line 430, the first storage electrode 441, and the second storage electrode 249.

"10th" to "13th" is a cross-sectional view of a cross section of a thin film transistor substrate along the V-V' and VI-VI' lines in "FIG. 9A" for explaining the present invention. A method of manufacturing a thin film transistor array substrate of the second embodiment.

The manufacturing method of the thin film transistor array substrate of the second embodiment is performed in the same manner as the first embodiment of "4A to 4G". Therefore, the central portion of the manufacturing method of the second embodiment which is different from the first embodiment shown in "Fig. 3B" will be described.

Referring to FIG. 9A and FIG. 10, the method of manufacturing a thin film transistor of the second embodiment allows the first common line 430 and the drain 117b of the thin film transistor TFT to be formed so as not to overlap each other. Thus, any overlapping portions are not present between the drain 117b and the curved portion 440, wherein the curved portion 440 and the first common line 430 are formed as a single body.

The first expanded portion 229 of the first pixel electrode 219 electrically connected to the drain 117b is also formed so as not to overlap the curved portion 440. The first extension portion 229 is configured to include a top extension layer 229a and a bottom extension layer 229b.

As shown in FIG. 10, the first expanded portion 229, the second pixel electrode 139, and a first pixel electrode 219 (not shown) are formed over the organic insulating film 150. Therefore, the second pixel electrode 139 and the first pixel electrode 219 can be cut without removing the organic insulating film 150 to repair a black spot.

"Fig. 11" shows an organic insulating film formed to have different thicknesses in one display region of a liquid crystal display device (LCD) and a non-display region. In other words, an organic insulating film pattern 150a is formed in the gate pad region of the non-display area and the thickness of the data pad, which is different from the thickness of the organic insulating film 150 in the display region. In detail, the organic insulating film pattern 150a in the non-display area in which the gate and the data pad are formed has a smaller thickness than the organic insulating film 150 in the display region. This can be achieved by applying a halftone mask and a diffractive reticle to the third mask process for forming the contact hole in the manufacturing method shown in "Fig. 4A" to "4G".

Thus, the height of the organic insulating film pattern 150a in the pad region is lowered from the fact that the organic insulating film 150 is thicker than the protective film 109 and the gate insulating film 102. If the organic insulating film 150 is formed to have a uniform thickness in the display and non-display regions, contact defects with the terminals of the external driving integrated circuit can be generated.

Therefore, a liquid crystal display device (LCD) having a reduced organic insulating film in the pad region can easily form an electrical contact with the terminal of an externally driven integrated circuit.

In "Fig. 12", a structure in which the organic insulating film 150 is completely removed from the gate and the data pad region is shown. Thus, when a gate contact electrode 310 is formed over the protective film 109, the gate contact electrode 310 is electrically connected to the gate 110. Similarly, when a data pad contact electrode 320 is formed over the protective film 109, the material pad contact electrode 320 is electrically connected to the data pad 120.

The thin film transistor array substrate of the second embodiment shown in Fig. 13 allows the organic insulating film 150, the protective film 109, and the gate insulating film 102 to be completely removed from the gate pad region. Similarly, the organic insulating film 150 and the protective film 109 are completely removed from the data pad area.

As a result, the gate pad contact electrode 310 is formed directly on the base substrate 100. The gate pad contact electrode 310 completely covers the gate pad 110. The data pad contact electrode 320 is formed to surround the gate insulating film 102, the channel layer pattern 114a, and the data pad 120 over the base substrate 100. Similarly, the material pad contact electrode 320 completely covers the data pad 120, the channel layer pattern 114a, and the gate insulating film 102.

In this manner, the manufacturing method of the second embodiment does not require an additional mask process, and a different structure can be realized on a liquid crystal display device (LCD).

Fig. 14A is a schematic view showing a pixel area in a liquid crystal display device (LCD) according to a third embodiment of the present invention. "Fig. 14B" is a cross-sectional view of a liquid crystal display device (LCD) along the X-X' and XI-XI' lines of "Fig. 14A".

The liquid crystal display device (LCD) of the third embodiment includes a modified pixel structure obtained from the second embodiment.

Referring to FIG. 14A and FIG. 14B, the liquid crystal display device (LCD) according to the third embodiment of the present invention has an open region OR in the third common electrode 333 formed on the data line 103. In the third embodiment, the pixels and the common electrode included in the liquid crystal display device (LCD) are formed of an opaque metal capable of shielding light. Therefore, it is difficult for these electrodes to recognize the disconnection of the data line 103 generated in a pixel region during a process.

The liquid crystal display device (LCD) of the third embodiment is based on the liquid crystal display device (LCD) of the second embodiment. Further, the liquid crystal display device (LCD) of the third embodiment removes a portion of the third common electrode 333 opposite to the data line 103 to make the data line 103 visible. The open area OR is preferably formed to have a width equal to or narrower than the data line 103. Although not shown in the drawings, reference numerals 〞 333a 〞 and 〞 333b 未 which are not explained respectively denote a top common electrode layer and a bottom common electrode layer.

Moreover, although not shown, a black matrix is formed over the color filter array substrate opposite the data line 103 and the third common electrode 333 is removed from the color filter array substrate. The structure of the color filter array substrate shown in "Fig. 7" and "Fig. 8" can be applied to the liquid crystal display device (LCD) of the third embodiment. This stems from the fact that the data line 103 opposite the open area OR is also formed by the opaque metal and shields the light entering from the surface after the base substrate 100.

When the second common line 132, the second common electrode 134, the first pixel electrode 219, and the second pixel electrode 139 are formed, an open region among the third common electrodes 333 is simultaneously formed.

The liquid crystal display device (LCD) of such a third embodiment can be applied to the first and second embodiments or other embodiments which will be described later.

"15A" to "15C" are cross-sectional views of spacers formed on the areas corresponding to the lines VII-VII', VIII-VIII', and IX-IX' of "Fig. 9A". . The liquid crystal display device (LCD) of these embodiments can contain two types of spacers. One type of spacer is a gap spacer that constantly maintains a cell gap between a color filter array substrate and a thin film transistor array substrate. And another type of spacer is a suppression spacer for preventing damage to the gap spacer that is pressed through the outside.

"Fig. 15A" and "Fig. 15C" show a suppression spacer and "Fig. 15B" shows a gap spacer. Since the spacer is not limited to its position, the position of the gap spacer and the suppression spacer can be freely changed. "15A" to "15C" mainly show a color filter array substrate having a black matrix, but a liquid crystal display device (LCD) having two types of spacers can be applied to have a "Fig. 7" A color filter array substrate having a black matrix.

Referring to FIG. 15A, a gate line 101 is formed on a base substrate 100. A gate insulating film 102, a protective film 109, and an organic insulating film 150 are sequentially formed over the gate line 101.

On the other hand, a red (R) filter layer 203a and a green (G) filter layer 203b are formed on the top substrate 200 opposite to the base substrate 100. Further, an overcoat layer 209 can be formed over the red (R) filter layer 203a and the green (G) filter layer 203b. Further, a suppression spacer 500 is formed on the overcoat layer 209 opposite to the gate line 101 formed on the base substrate 100.

Further, a groove G is formed on the organic insulating film 150 opposite to the suppression spacer 500.

Similarly, as shown in FIG. 15C, a second storage electrode 249 is formed on the gate insulating film 102 opposite to a first common line 430. The second storage electrode 249 is located above the first common line 430. Moreover, another suppression spacer 500 is formed on the overcoat layer 209 opposite to the second storage electrode 249. Further, a first pixel electrode 219 is formed on one of the other grooves G and the organic insulating film 150 in such a manner as to overlap with a portion of the first common line 430.

Referring to FIG. 15B, a first common electrode 131 is formed on the base substrate 100, and a data line 103 is formed on the gate insulating film 102 at the center of the first common electrode 131. The data line 103 is located above the first common electrode 131. Further, a third common line 133 is formed on the organic insulating film 150 opposite to the data line 103. The third common electrode 133 is located above the data line 103.

A gap spacer 501 and a third common electrode 133 are formed on the outer coating layer 209 of the color filter substrate. Although not clearly shown in "Fig. 15B", an alignment film is formed on the top substrate 200 having the gap spacers 501. And another alignment film is formed over the base substrate 100 having the third common electrode 133.

Thus, the gap spacer 501 is in contact with the color filter array substrate and the thin film transistor array substrate and constantly maintains a cell gap between the two substrates. In other words, the liquid crystal display device (LCD) of the present embodiment constantly maintains the cell gap between the color filter array substrate and the thin film transistor array substrate through the gap spacer 501. However, when a portion of the display area is pressed by an external force that is more bearable than the gap spacer 501, the gap spacer 501 is broken or loses its recovery ability.

In order to solve this problem, the liquid crystal display device (LCD) of the present embodiment includes a plurality of suppression spacers 500 as shown in "Fig. 15A" and "Fig. 15C". More specifically, when the two combined substrates are pressed by an external force, only the gap spacer 501 first maintains the cell gap. The strength of the external force maintained only by the gap spacer 501 corresponds to the force that causes the end of the spacer 500 to be in contact with the bottom surface of the groove G above the organic insulating film 150. In the case where the end portion of the suppression spacer 500 is in contact with the bottom surface of the groove G, the gap spacer 501 together with the suppression spacer 500 maintains the cell gap between the two substrates.

The suppression spacer 500 can be formed to the same height as the gap spacer 501 or a lower height than the gap spacer 501. If the suppression spacer 500 and the gap spacer 501 are formed at different heights, the groove G opposed to the suppression spacer 500 can be removed from the organic insulating film 150.

Moreover, the suppression spacers 500 and the gap spacers 501 having different heights can be formed by a mask process using one of a halftone mask or a diffractive mask.

The spacers shown in "15A" to "15C" can be applied to all embodiments of the present invention.

Fig. 16A is a schematic view showing a pixel region in a liquid crystal display device (LCD) according to a fourth embodiment of the present invention. "Fig. 16B" is an enlarged view of a thin film transistor in "Phase 16A".

The liquid crystal display device (LCD) of the fourth embodiment shown in "16A" and "16B" is arranged in the same manner as "FIG. 9A". Therefore, the same elements in the liquid crystal display device (LCD) of the fourth embodiment as those in the second embodiment in "Ath 9A" and "9B" are denoted by the same reference numerals. Moreover, portions of the fourth embodiment that are different from the second embodiment will be mainly described.

Referring to "FIG. 16A" and "FIG. 16B", a liquid crystal display device (LCD) according to a fourth embodiment of the present invention includes an improved structure which makes the pixel repair process more comparable to the structure of the second embodiment. easily.

Among the pixel regions in which the thin film transistor TFT is formed, the first common line 430 is parallel to the gate line 101. The first common line 430 is formed to include a bent portion 440 at a position where the drain 117b of the thin film transistor TFT is formed. The curved portion 440 does not overlap the drain 117b.

As described above, if the first common line 430 does not overlap with the drain 117b, a storage capacitor cannot be formed in the pixel area. In order to solve this problem, the liquid crystal display device (LCD) of the fourth embodiment of the present invention allows a first storage electrode 441 to be formed in the pixel region opposite to the curved portion 440 of the first common line 430. The first storage electrode 441 and the first common line 430 are formed as a single body. In other words, the curved portion 440 is formed at one end of the first common line 430, and the first storage electrode 441 is formed at the other end of the first common line 430.

Moreover, the second storage electrode 249 is formed to overlap the first common line 430 and the first storage electrode 441. The second storage electrode 249 is formed in the same metal as the source/drain electrodes 117a and 117b.

Moreover, a first pixel electrode 219 is parallel to the gate line 101 and the first common line 430. The first pixel electrode 219 includes a first extension portion 229 and a second extension portion 239 at both ends thereof. More specifically, the liquid crystal display device (LCD) of the fourth embodiment of the present invention allows the first pixel electrode 219 and the first extension portion 229 to be in contact with each other in the center of a connection portion 289 adjacent to the drain 117b. Interval.

The first pixel electrode 219 is formed to be bent at the connecting portion 289 so as to overlap with the curved portion 440 of the first common line 430. The first expanded portion 229 is formed in a direction parallel to the gate line 101 and is electrically connected to the drain 117b through a first contact hole 230.

Therefore, the pixel repair process of the liquid crystal display device (LCD) of the fourth embodiment of the present invention is realized by cutting the connection portion 289 along a cutting line C2. Thus, the liquid crystal display device (LCD) of the fourth embodiment of the present invention is easier to repair a pixel than the liquid crystal display device (LCD) of the second embodiment, similar to the second embodiment, and the fourth embodiment of the present invention The liquid crystal display device (LCD) can repair the pixels by performing a cutting operation without removing the organic insulating film 150.

Fig. 17A is a schematic view showing a pixel area in a liquid crystal display device (LCD) according to a fifth embodiment of the present invention. "Fig. 17B" is an enlarged view of a thin film transistor in "Phase 17A".

The fifth embodiment of the present invention is applied to a fringe field switching type (FFS) liquid crystal display device (LCD). The liquid crystal display device (LCD) of the fifth embodiment is arranged in a similar manner to the second embodiment of "Fig. 9A" and "Fig. 9B", but is different from the pixel in the pixel region of the second embodiment. The structure of the electrodes is different. Therefore, the same elements of the liquid crystal display device (LCD) of the fifth embodiment as those of the second embodiment of the "Ath 9A" and "9B" are denoted by the same reference numerals. Moreover, portions of the fifth embodiment that are different from the second embodiment will be mainly described.

Referring to FIG. 17A and FIG. 17B, a liquid crystal display device (LCD) according to a fifth embodiment of the present invention includes a pixel region defined by a gate line 101 and a data line 103 intersecting each other. A thin film transistor TFT is formed at the intersection of the gate line 101 and the data line 103. In the liquid crystal display device (LCD) of the fifth embodiment of the present invention, a first common line 430 is formed to include a bent portion 440 which is parallel to the gate line 101 and does not overlap with a drain 117b. Overlapping. Moreover, the liquid crystal display device (LCD) of the fifth embodiment of the present invention allows additional storage electrodes for a storage capacitor to be not formed in the first common line 430.

Moreover, the first common electrode 431 branched from the first common line 430 is parallel to the data line 103. The first common electrode 431 is positioned adjacent to the data line 103.

Moreover, a pixel electrode 419 is formed in the pixel area. The pixel electrode 419 is formed in a panel structure and electrically connected to the drain 117b through a first contact hole 230. Such a pixel electrode 419 can be formed of a transparent conductive material such as indium tin oxide (ITO), indium tin zinc oxide (ITZO), and one of indium zinc oxide (IZO).

The pixel electrode 419 overlaps the first common line 430 to form a storage capacitor. In detail, the first common line 430 and the curved portion 440 serve as one of the storage capacitor electrodes. The pixel electrode 419 overlapping the first common line 430 and the curved portion 440 serves as the other electrode of the storage capacitor.

Further, a second common line 432, a second common electrode 434, and a third common electrode 433 are formed over the pixel electrode 419. The second common electrode 434 is formed to include a plurality of strips branched from the second common line 432. The third common electrode 433 is formed to overlap the data line 103.

The drain 117b and the curved portion 440 of the first common line 430 are spaced apart so as not to overlap each other. Therefore, a pixel repair process is performed by cutting the pixel electrode 419 formed between the curved portion 440 and the drain 117b.

Figure 18 is a cross-sectional view along the XII-XII' and XIII-XIII' lines in Figure 17.

Referring to "FIG. 17A", "FIG. 17B", and "18th", a gate 101a and a bent portion 440 which are formed as a single body with the first common electrode 430 are formed on the base substrate 100. A gate pad 110 branched from the first common line 430 and a first common electrode 431 are also formed on the base substrate 100. Since the gate 101a functions as one of the electrodes of a thin film transistor TFT, the gate 101a has a wider width than that of the gate line 101.

A channel layer 114 and source/drain electrodes 117a and 117b are formed on the gate 101a at the center of a gate insulating film 102. The data line 103 is formed over the gate insulating film 102 between the first common electrodes 131 (see the cross section along the line XII-XII').

A protective (or passivation) film 109 is formed over the base substrate 100 having source/drain electrodes 117a and 117b and data lines 103. A pixel electrode 419 is formed on the protective film 109. The pixel electrode 419 is electrically connected to the drain 117b through the first contact hole 230.

The pixel electrode 419 can be realized by adding a contact hole forming process and a pixel electrode forming process to the manufacturing method of the first embodiment after the protective film 109 is formed.

A second common electrode 434 and a third common electrode 433 are formed on the pixel electrode 419 at the center of an organic insulating film 150. In other words, the manufacturing method of the liquid crystal display device (LCD) of the fifth embodiment of the present invention allows only the common electrode to be formed over the organic insulating film 150. The second common electrode 434 is formed to include a plurality of strips arranged above the pixel area.

Therefore, the liquid crystal display device (LCD) of the fifth embodiment of the present invention is driven by a vertical electric field formed on the pixel electrode 149 formed under the organic insulating film 150 and the second layer formed on the organic insulating film 150. Between the third common electrodes 434 and 433.

In the liquid crystal display device (LCD) of the fifth embodiment of the present invention, the pixel electrode 419 is formed in a panel structure, but it is only an example. Alternatively, the pixel electrode 419 can be formed over the protective film 109 in the same manner as the second embodiment. In other words, the pixel electrode 419 can be formed to include a plurality of strips.

Further, the pixel electrode 419 is formed on the protective film 109, but is not limited thereto. In a different manner, the pixel electrode 419 can be positioned above the base substrate 100 or over the gate insulating film 102 in the pixel region.

The third common electrode 433 is formed on the organic insulating film 150 opposite to the data line 103.

Further, a gate pad 110 connected to the gate line 101 is formed in a gate region. The gate insulating film 102, the protective film 109, and the organic insulating film 150 are sequentially formed. The gate pad contact electrode 310 is electrically connected to the gate pad 110 through the second contact hole 231, and the gate pad contact electrode 310 is formed over the organic insulating film 150.

Further, a gate insulating film 102 is formed over one of the material pad regions of the base substrate 100. A data pad 120 extending from the data line 103 is formed over the gate insulating film 102. The protective film 109 and the organic insulating film 150 are sequentially formed on the data pad 120. The data pad contact electrode 320 is electrically connected to the material pad 120 through the third contact hole 232, and the material pad contact electrode 320 is formed over the organic insulating film 150.

After the organic insulating film 150 is formed, the formed second common electrode 434, the third common electrode 433, the gate electrical contact electrode 310, and the material pad contact electrode 320 each have a double metal layer structure. Thus, the second common electrode 434 includes a top common electrode layer 434a and a bottom common electrode layer 434b. The third common electrode 433 includes a top common electrode layer 433a and a bottom common electrode layer 433b.

While the embodiments of the present invention have been described above by way of exemplary embodiments, those skilled in the art will recognize that the present invention can be practiced without departing from the spirit and scope of the invention disclosed in the appended claims. Modifications and retouchings are within the scope of patent protection of the present invention. In particular, different variations and modifications of the components and/or combinations may be made in the specification, the drawings and the accompanying claims. In addition to variations and modifications in the component parts and/or combinations thereof, those skilled in the art should also be aware of the alternate use of the components and/or combinations.

1. . . Gate line

1a. . . Gate

3. . . First common line

3a. . . First common electrode

5. . . Data line

6. . . First storage electrode

7. . . Second storage electrode

7a. . . Pixel electrode

10. . . Bottom substrate

12. . . Gate insulating film

13. . . Second common line

13a. . . Second common electrode

13b. . . Third common electrode

19. . . Protective film

20. . . Top substrate

twenty one. . . Black matrix

25a. . . Red filter layer

25b. . . Green filter

29. . . Overcoat

100. . . Bottom substrate

101. . . Gate line

101a. . . Gate

102. . . Gate insulating film

103. . . Data line

109. . . Protective film

110. . . Gate pad

114. . . Channel layer

114a. . . Channel layer pattern

117a. . . Source

117b. . . Bungee

119. . . First pixel electrode

120. . . Data pad

124. . . Semiconductor layer

127. . . Source/drain metal film

129. . . Second storage electrode

129a. . . Top storage electrode layer

129b. . . Bottom storage electrode layer

130. . . First common line

131. . . First common electrode

132. . . Second common line

133. . . Third common electrode

133a. . . Top common electrode layer

133b. . . Bottom common electrode layer

134. . . Second common electrode

134a. . . Top common electrode layer

134b. . . Bottom common electrode layer

139. . . Second pixel electrode

139a. . . Top pixel electrode layer

139b. . . Bottom pixel electrode layer

140. . . First storage electrode

150. . . Organic insulating film

150a. . . Organic insulating film pattern

180. . . Metal film

200. . . Top substrate

203a. . . Red filter layer

203b. . . Green filter

204. . . Black matrix

209. . . Overcoat

219. . . First pixel electrode

229. . . First extension

229a. . . Top extension layer

229b. . . Bottom extension layer

230. . . First contact hole

231. . . Second contact hole

232. . . Third contact hole

233. . . Fourth contact hole

239. . . Second extension

249. . . Second storage electrode

289. . . Connecting part

300. . . Mask

310. . . Gate pad contact electrode

310a. . . Top gate pad contact electrode layer

310b. . . Bottom gate pad contact electrode layer

320. . . Data pad contact electrode

320a. . . Top data pad contact electrode layer

320b. . . Bottom data pad contact electrode layer

333. . . Third common electrode

333a. . . Top common electrode layer

333b. . . Bottom common electrode layer

419. . . Pixel electrode

430. . . First common line

431. . . First common electrode

432. . . Second common line

433. . . Third common electrode

433a. . . Top common electrode layer

433b. . . Bottom common electrode layer

434. . . Second common electrode

434a. . . Top common electrode layer

434b. . . Bottom common electrode layer

440. . . Curved part

441. . . First storage electrode

500. . . Inhibition spacer

501. . . Gap spacer

TFT. . . Thin film transistor

C1, C2. . . Cutting line

G. . . Groove

L1, L2. . . width

S1. . . First inclined surface

S2. . . Second inclined surface

P1. . . Transmissive zone

P2. . . Non-transmission zone

OR. . . Open area

1 is a schematic diagram of a pixel structure in a planar switching (IPS) type liquid crystal display device (LCD) of the prior art;

Figure 2 is a cross-sectional view of the pixel structure along the line I-I' of Figure 1;

3A is a schematic view showing a pixel area of a liquid crystal display device (LCD) according to a first embodiment of the present invention;

Figure 3B is a cross-sectional view of the liquid crystal display device (LCD) along the II-II' line and the III-III' line of Figure 3A;

4A to 4G are cross-sectional views of a thin film transistor substrate along lines II-II' and III-III' of Fig. 3A, and are used to explain a method of manufacturing a thin film transistor array substrate;

5A and 5B are schematic views for explaining problems caused by the etching method of the prior art applied to the contact hole manufacturing process of the present embodiment;

6A to 6C are schematic views for explaining an etching process during the manufacture of one of the contact holes of the embodiment;

7 and 8 are schematic views showing a cross-sectional structure of a color filter substrate corresponding to the IV-IV' line in Fig. 3A;

9A is a schematic view showing a pixel region in a liquid crystal display device (LCD) according to a second embodiment of the present invention;

Figure 9B is an enlarged view of a thin film transistor shown in Figure 9A;

10 to 13 are cross-sectional views of cross sections of the thin film transistor substrate taken along lines V-V' and VI-VI' in Fig. 9A for explaining the film of the second embodiment of the present invention. a method of manufacturing a transistor array substrate;

14A is a schematic view showing a pixel region in a liquid crystal display device (LCD) according to a third embodiment of the present invention;

Figure 14B is a cross-sectional view of a liquid crystal display device (LCD) along the X-X' and XI-XI' lines of Figure 14A;

15A to 15C are cross-sectional views of spacers formed on regions corresponding to lines VII-VII', VIII-VIII', and IX-IX' of Fig. 9A;

16A is a schematic view showing a pixel region in a liquid crystal display device (LCD) according to a fourth embodiment of the present invention;

Figure 16B is an enlarged view of a thin film transistor of Figure 16A;

17A is a schematic view showing a pixel area in a liquid crystal display device (LCD) according to a fifth embodiment of the present invention;

Figure 17B is an enlarged view of a thin film transistor of Figure 17A;

Figure 18 is a cross-sectional view of the liquid crystal display device (LCD) along the XII-XII' and XIII-XIII' lines in Figure 17A.

101. . . Gate line

101a. . . Gate

103. . . Data line

110. . . Gate pad

119. . . First pixel electrode

120. . . Data pad

129. . . Second storage electrode

130. . . First common line

131. . . First common electrode

132. . . Second common line

133. . . Third common electrode

134. . . Second common electrode

140. . . First storage electrode

139. . . Second pixel electrode

230. . . First contact hole

231. . . Second contact hole

232. . . Third contact hole

233. . . Fourth contact hole

310. . . Gate pad contact electrode

320. . . Data pad contact electrode

TFT. . . Thin film transistor

Claims (23)

A thin film transistor array substrate comprises: a substrate defined as a display area and a non-display area; a gate line and a data line interlaced with each other to be in the display area of the substrate Defining a pixel area; a first common line is formed parallel to the gate line and intersecting the data line; a plurality of first common electrodes are formed on both sides of the data line and are self-contained a first common line extending parallel to the data line; a switching element disposed at an intersection of the gate line and the data line; a first pixel electrode formed to be opposite to the gate line Parallel; a second pixel electrode extending from the first pixel electrode and parallel to the data line; a second common line opposite to the first common line in the pixel region; a second common electrode extending from the second common line toward the pixel region; a third common electrode extending from the second common line and overlapping the data line, the third common electrode being covered by the Organic insulating film between the third common electrode and the data line And spaced apart between the data line and the first common electrodes; a first storage electrode extending from the first common line into the pixel region; and a second storage electrode formed as Overlapped with the first storage electrode. The thin film transistor array substrate of claim 1, further comprising a curved portion, the curved portion being formed as a single body with the first common line and not overlapping with one of the switching elements. The thin film transistor array substrate of claim 2, wherein the first storage electrode and the first common line are formed as a single body and opposite to the curved portion; and the second storage electrode is associated with the data A metal layer of the same line is formed. The thin film transistor array substrate of claim 3, wherein the first pixel electrode further comprises: a first extension portion formed at one end of the first pixel electrode and coupled to the switching element The drain electrode is connected; and a second extension portion is formed at the other end of the second pixel electrode and connected to the second storage electrode. The thin film transistor array substrate of claim 4, wherein the curved portion of the first common line is spaced apart from the drain of the switching element. The thin film transistor array substrate of claim 4, wherein the curved portion of the first common line is spaced apart from the first expanded portion adjacent to the drain. The thin film transistor array substrate of claim 1, further comprising an open area that removes a portion of the third common electrode corresponding to the data line. The thin film transistor array substrate of claim 7, wherein the open region is formed to have the same width as the data line or a narrower width than the data line. The thin film transistor array substrate of claim 1, further comprising a gate pad formed in the non-display area of the substrate; a gate pad contact electrode formed on the gate pad and The gate pads are connected; a data pad is formed in the non-display area of the substrate; and a data pad contact electrode is formed on the data pad and connected to the data pad. The thin film transistor array substrate of claim 9, wherein the organic insulating film formed in the non-display area has a smaller thickness than the organic insulating film formed in the display region. The thin film transistor array substrate of claim 9, wherein the organic insulating film is completely removed from the non-display area where the gate pad and the data pad are formed. The thin film transistor array substrate according to any one of the items 1 to 9, wherein the second storage electrode, the second common electrode, the third common electrode, the gate pad contact electrode, and the The data pad contact electrodes are arranged to each have a double metal layer structure. The thin film transistor array substrate of claim 12, wherein the top layer of the bimetal layer is a low reflectivity metal layer having copper (Cu). The thin film transistor array substrate of claim 1, wherein the organic insulating film is formed to be thicker as a driving frequency becomes higher. The thin film transistor array substrate of claim 14, wherein the organic insulating film is formed to have a thickness ranging from 2.5 to 3.5 micrometers (μm) when the driving frequency is 120 Hz. The thin film transistor array substrate of claim 14, wherein the organic insulating film is formed to have a thickness ranging from 5.5 to 6.5 micrometers (μm) when the driving frequency is 240 Hz. The thin film transistor array substrate of claim 1, wherein the third common electrode is further configured to have an opening along the data line and exposing the data line. A method for fabricating a thin film transistor array substrate, comprising the steps of: providing a substrate defining a display region and a non-display region; forming a first metal layer on the substrate and passing through a first mask a process, the first metal layer is patterned into a gate, a gate line, and a first common electrode arranged on the display area, and a gate pad arranged on the non-display area; Forming a gate insulating film, a semiconductor layer, and a second metal layer on the substrate and forming a source/drain, a second storage from the second metal layer and the semiconductor layer through a second mask process An electrode, a channel layer, and a data line; sequentially forming a protective film and an organic insulating film on the substrate, and forming a pattern of the organic insulating film by performing an exposure and development step according to a third mask process; The first etching step and the second etching step are sequentially performed on the gases having different oxygen content ratios, and the patterned organic insulating film is used as an etch in the first etching step and the second etching step a reticle for forming a plurality of contact holes in a drain region, a gate pad region, and a data pad region; and sequentially forming a third metal layer and a fourth metal layer to have the contact holes And over the organic insulating film, and then patterning the third metal layer and the fourth metal layer into a pixel electrode and a second common electrode through a fourth mask process, wherein the fourth mask process A third common electrode that is allowed to overlap the data line is formed over the organic insulating film. The method of manufacturing a thin film transistor array substrate according to claim 18, wherein the third mask process uses one of a halftone mask and a diffractive mask, and the organic insulating film is over the non-display area. There is a thickness smaller than that of the organic insulating film over the display region. The method of manufacturing a thin film transistor array substrate according to claim 18, wherein the fourth metal layer is a low reflectivity metal layer containing copper (Cu). The method for manufacturing a thin film transistor array substrate according to claim 18, The third common electrode is further configured to have an opening formed along the data line and exposing the data line. The method for fabricating a thin film transistor array substrate according to claim 18, wherein a flow ratio of the SF ₆ :O ₂ etching gas used in the first etching step can be in a range of 1:2.0-1:3.0 . The method for fabricating a thin film transistor array substrate according to claim 18, wherein a flow ratio of the SF ₆ :O ₂ etching gas used in the second etching process can be in a range of 1:2.0-1:3.0 .