TWI264810B - Structure and method of forming a multiple leadframe semiconductor device - Google Patents
Structure and method of forming a multiple leadframe semiconductor device Download PDFInfo
- Publication number
- TWI264810B TWI264810B TW92109716A TW92109716A TWI264810B TW I264810 B TWI264810 B TW I264810B TW 92109716 A TW92109716 A TW 92109716A TW 92109716 A TW92109716 A TW 92109716A TW I264810 B TWI264810 B TW I264810B
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- Taiwan
- Prior art keywords
- lead frame
- lead
- semiconductor
- semiconductor device
- semiconductor die
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 31
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Classifications
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Description
1264810 玖、發明說明: 【發明所屬之技術領域】 本專利係於2002年4月26日提出的美國專利申請,專利申 請案號為1 0/1 33,527。 本發明一般而言係涉及半導體裝置的包裝,更特言之, 係涉及形成一具有一個以上的引線框和内含一個以上裝置 的半導體裝置。 【先前技術】 一般而了,當代的電子裝置,在設計時都會考慮到例如 像大小、重量和電力耗損等重要的設計準則。這類準則不 断減少,因為設計變得更複雜,以便達成更多的功能。對 進階功能和效能的需求,使得組件製造商將以不同技術為 基礎的裝置整合至單一包裝中。 方法之一是將兩個或以上的裸露半導體晶粒置放在具有 傳導性網路的基板上,以形成多晶片模組或MCM,其中該 網路可提供晶粒的電互連。MCM上使用的基板通常是多層 的印刷電路板’其中一些互連位於模組之外,用以連接至 客戶的印刷電路板。然後MCM的基板以一蓋子或密封劑覆 蓋,形成完成封裝的裝置。 "又足成一電壓調整器的先前技術多晶片模組5 0 0範例,如 圖1所不。如圖所示,MCM電壓調整器500包括一支援複數 個晶粒540和542的印刷電路板520,其中晶粒以拉線560、 561焊接到印刷電路板的信號線530-532。 使用混合的晶粒技術實現裝置5 00的許多MCM的典型中 84745 1264810 ,晶粒542是功率M0SFET技術的傳動電晶體,而且晶粒54〇 是類比技術的一個電壓調整器開關。因此,功率m〇sfet^ 粒542傳送大電流所需要的拉線焊接,是由大量的鋁或鋁合 金線(例如直徑125微米)所製造,類比晶粒54〇用於快速信號 傳送和低衰減率所需的拉線焊接,是由少量的金或金合金 所製造(例如直徑5 0微米)。 焊接金線工具的焊接頭直徑約二百五十微米,而用於鋁 線的直徑大約是四千微米。使用不同的拉線焊接材料,需 要信號線具有以最佳效能和可靠性黏附拉線焊接的相容表 面材料。在這個範例中,信號線532和信號線531的部份534 ’鍵有至少部份的銀鎳合金,以幫助金線焊接黏附。用於 功率MOSFET的鋁焊接線561,黏附信號線53〇和信號線53ι 的銅區域533。㈣焊接在金線焊接之前進行,因為用來坪 接金線的高溫會氧化銅信號線,而導致鋁焊接具有品質不 佳的強度和可靠性。 k號線另連接到完成的MCM的外部引線5丨〇,以提供電連 接給一具有連接間距或距離503的客戶印刷電路板。 在烊接引線之間必須有距離501,以允許在清除所有拉線 和裝置的拉線焊接流程期間,用來容納支撐基板的窗框(未 顯示)。如上所述所提供的距離,導致在類比開關54〇的晶粒 墊871和傳動電晶體542的晶粒墊872之間產生一長的有效 傳導路徑502。長的有效傳導路徑,特別是在需要快速電響 應或傳送小電流的應用中,會使信號傳送降級。 曰 孩模組使用密封劑590密封起來與環境隔絕,以形成—完 84745 1264810 成的多晶片模組。MCM因此形成,但是成本很昂貴,在空 間運用上是高度有效的,並較放置在客户電路板上,需要 較少的印刷電路板空間。 多晶片模組的可靠性對製造商和使用者非常重要。各種 不同的半導體晶粒使用的完整功能性測試,特別是高速測 武和抵燒後的測試,是確保可靠性的基本技術。多晶片模 組的一個缺點是他們極難測試,因為只有半導體晶粒的一 些接點塾可以利用從包裝延伸的引線,轉合至一外部測試 器。測試的另-個棘手問題是,當半導體晶粒尚未固定至 基板之前,很難能夠進行完整的測試。甚至,一旦各種不 同的半導體晶粒彼此連接,他們的特性會受到修改;互連 建立的寄生變成雖然不是不可能,但是很難測量。在高速 下更是特別難測試。因此,多晶片模組裡的整合晶粒晶片 的功能不㈣被完整地測試,因4沒有方㈣合—測試器 到在個別半導體晶粒上的個別接點墊。 此外,要製造出MCM十非昂貴,如同當作基板使用的多 ㈢印刷電路板製作起來很複雜是—樣的。除此之外,在模 組之内不同類型的晶粒需要不同的組合設備、材料和方法 才能把他們貼附到基板上。貼附作業更導致其他問題。由 於焊接流程期間必須使用窗框在拉線燁接時限制基板和焊 接工具頭的大小’因此這些元件引線間必須有足夠空間允 =拉線焊接’因而限制了密度。—般而言,除了用來限制 基板的窗框之外’焊接線越大’晶粒周圍需要設定 就越大。 84745 1264810 MCM印刷笔路板的另一個問題 缚煜技,W *丄\ 要追蹤不同材料的拉 、、泉綷接,成本十分昂貴且工序複 拉嗖焊接5 例如,功率裝置較妤 拉、、泉浮接土大且厚的信號線,以執 * tp ^ W ^ ^ 4' ^ , 丁大私和高熱,而類 比衣置較好拉線焊接至薄且短 ㊉要的、条命Λ, 就線,以配合類比裝置 而要勺速度。MCM的這些問題已經 因此,較好有—㈣成半化成低^ “成本。 槿夫女土目女 风千寸把衣置的結構和方法,該結 構和万法具有允許多重半導體 ΛΛ ^ », π η, 釭正《土早—封裝裝置内 的優點’同時又能避免先前技術的問題。 【發明内容】 本發明揭示-種半導體裝置(2〇),其具有—第一引線框 (200)’有—第一半導體晶粒(7〇)電耦合至其引線盆中之一。 一第二半導體晶粒(13〇)固定至-第二引線框(300),該引線 框具有一第一引線(35、15〇)電搞合至該第二半導體晶粒以 及-弟二引線(3〇、35)固定至該第—引線框的該引線。 【貫施方式】 一圖2為一橫斷面圖,顯示包括一被封裝的半導體組件或一 半導體包裝21中所容納的裝置23〇和半導體晶粒13〇的半導 眼組件或裝置20。封裝的半導體裝置230固定在引線框3〇〇 的區域160中,而且一半導體晶粒13〇固定在引線框3〇〇的區 域170。引線框3〇〇、封裝的半導體晶粒23〇和半導體晶粒no 佈滿一密封材料10,以形成半導體裝置2〇成品。在一具體 貫施例中,半導體裝置2〇設定為一電壓調整器,有封裝的 半導體裝置230作為一類比開關,以及半導體晶粒13〇包括 一功率電晶體。 84745 -10- 1264810 封裝的半道_ 定並泰幸八豆日曰粒23(3包含有一半導體裝置或晶粒70,固 側向S =1、_QG ’具有—厚度99敎來提供一小的 "隙49。類比開關應用的厚度99通常大約是- 百微米。引紿>、 ^疋一 rr, , π扛^00藉由圖案化和蝕刻一金屬製的薄板所 /成^ ’移p令夫士划、 P %隔離引線和其他特性。也就是說,杏 :二屬材料形成引線框2〇〇時’應特別注意與引線4〇和二 ::㈣有關的引線框2〇〇的厚度99。引線框的厚梅質 上決走可以古4土 kzL 1 曰^ π 特性相似的引線40和90或旗標80之間形成的 取小間隙49。捫Ψ τ η ^ 7 程姓刻特性莘 側向尺寸需要厚度99根據使用的流 、t例地減少。因此用於小的間距或側向尺寸 時’厚度99會因而減少。一丄 I而5,製造有減少側向尺寸 的^泉框/那些具有較大側向尺寸更昂貴。 曰曰权70疋使用一黏著劑或軟焊料(未 80,並藉由焊接線5 s 柄口毛 ▲ 4 線40。焊接線55像本技術中 -w 接工具(未頭示)黏附在晶粒70的 弟置然後拉到引線40處,其中該引線以熱熔方式黏 附至一部份81,然後移聞τ目 〜万式黏 、 、 ’、。引線4 0的邵份8 1包括一鐘 銀合金塗料,以增進焊接線 ” 程的期間,窗框(未顯示)限 ^接/儿 期間不會移動。當從晶粒俨垃&力^ 卞接机私 + 、 田攸曰曰粒詠接到引線的時候,窗框有一開
口或冒口可供拉線焊接工且確士、 rJ 、 “〜、在冒框的冒内移動一個距離 4 8。拉線悍接工具頭的直徑 ^ , 二大、、々疋10¾、爾(千分之一英 。同樣地,一坪接線5 6舛θ ,、 大" 果6攸晶粒70連接至引線90。在—且_ 實施例中,焊接線55和56包括全 一 枯至材科。在一具體實施例中 84745 1264810 、卞接、、泉5 5和5 6形成為小於五十微米的直徑,這對焊接線 而口疋小的直從。廷類小直徑金線,用來增強在拉線焊接 55-56上所攜帶信號的傳輸特性。—具體實施例中的引線框 2〇0佈滿一密封材料21〇,形成封裝的半導體晶粒230。 來自如上所描述流程的封裝半導體晶粒23〇具有密度高 石4L k成本低的優點。此外,封裝的半導體晶粒η ◦在固定 二引線框300上之前,通常必須接受完整的功能性和參數測 4如此,才能知迢封裝的半導體晶粒230是否是好的裝置 :如果應用需要屏隔或熱吸收,封裝的半導體晶粒23〇可以 成〃有局#屏隔或熱凹陷(未顯示),或給定應用的其他特 朱化特丨生。應压意’上述的局部屏隔或凹&,將會比如果 這類特性在實際上較大的半導體裝置20上提供的情況的成 要低特刎s所有元件都不需要屏隔或凹陷時更是如此 。在其他具體實施例中,封裝的半導體晶粒23G包括帶引線 的、雙重内歲、球柵陣列、接針或其他類型的封裝半導體 裝置。 寸缸 、半導體晶粒1 3 〇固定及/或電耦合至-引線框3 0 0的引線或 旗標1 4 0。在一且香曲♦ μ山 豆貝她例中,半導體晶粒130包括一功率 迅日日^或其他功率消散裝置,形成的引線框具有大約五 百微米的高厚度98 ’有助於熱移除。厚度98比厚度99厚, 因為半導體晶粒13〇產生熱,並較封裝的半導體晶粒^做 更夕的功。當触刻金屬材料形成引線框则時,應特別注竞 ”引、泉3 0 J 5、1 5 0和旗標丨4〇有關的引線框的厚度。因 此’大側向尺寸或間距47的需求,根據使用流程的蝕刻特 84745 1264810 性,等比例地增加厚度98。目此料 時,厚度98會因而增加。—$ 或侧向尺寸 叙而5,製造有增力 的引線框’比那些具有較小側向尺寸的成本更低尺寸 +導體晶粒130是使用-黏著劑或軟焊料(未顯二… /或熱耦合旗標140,並藉由焊接線11〇耦合至引線:以電及 線U0像本技術中典型的方式使用大拉線烊接工且:焊接 黏附在晶粒130的第—位置120然後拉到引線35處,/中^ 引線以超音波方式黏附至—部份”,然後移開工且弋:: 35猶37包括銅或銘,如-典型的触刻引線框。。同= ,焊接線115從半導體晶粒13〇連接至引線15〇 : 料在黏附銘焊接線例如像焊接線m和U5時H入 所以引線框綱並未塗佈有鎳銀合金材料。因此,m 可以低的製造成本形成。 主引線框200和300較印刷電路板更容易製造且成本較不产 貴,其中印刷電路板由連續的電介質和傳導性或全^材: 的層板組成,並触刻該金屬層留下基礎介電層支援、各作 電信號線或引線使用的金屬區。相對地,所形成的引、:框 ’由敍刻、乳製、切割或移除金屬薄板上的材料形成傳道 性信號線。當信I㈣成時,並沒有基礎介電材料支援; 所以不需要轆成薄片的流程,因此引線框比較容易製造並 且實質上具有較低的成本。 引線框300通常形成為具有空洞45,以及引線鎖31,如引 、、泉150、140、35和3 0所示。各種不同尺寸的?丨線鎖可以藉 由移除引線框300材料厚度97形成,通常包括矩形、凹角、 84745 l2648l〇 凸角,或圓角。 此外,如上所述,在拉線焊接流程的期間,窗框(未顧示) 限制引線框’ €它在拉線焊接流程期間不會移動。當從晶 粒焊接到引線的時候,窗框有一窗口可供拉線焊接工具頭 在窗框的窗内移動-個距離47。纟—具體實施例中,焊接 線1 1 0或1 1 5包括鋁材料。 —在-個具體實施例中,烊接線11〇或115包括形成直徑大於 三百五十微米的焊接線。這類大直徑的錯線,需要傳遞半 w & 1 30所產生的大電流。冑#直徑三百五十微米的鋁 、、泉’典型的拉線焊接工具頭大約是直徑四千微米。 一旦半導體晶粒130固定到如上所述的引線框3〇〇,使用 ]戈文于球或"錫霄50,將封裝的半導體晶粒230固定或電 ,、口 土引線框300。、焊錫膏流程能夠與固定或電賴合半導體 :^⑽至引線框'以及與用來黏附焊接線11G和11 5的流 並仃也就疋說,機械和電特性不會改變。然後引線框 a〇G以在封劑1〇覆蓋形成半導體裝置20。半導體裝置20有一 1 :寸或間距46,用於耦合到客戶的印刷電路板。尺寸 疋在客戶電路板的田比連引線之間最小的間隔距離,通常 3大於側向尺寸48或47中較小的那一邊。 所述开y成半導體裝置2〇的優點之一為:形成的引線 匡200可以具有較薄的金屬以達成一細距,縮小電路寄生並 曰 的傳送,同時引線框300可利用較厚的材料製造, 夂用铋作半導體晶粒1 30所需的低熱和電阻。也就是說, 不同厚度的引線框可以用來配合具有不同包裝需求的 84745 14 1264810 半導體晶粒,例如像熱管理、固定技術、成本、功能性剛 減包屏隔或拉線焊接。在上述範例中,用來固定傳動電 晶:::線框厚度,比類比開關的厚度要厚很多,因為: 動私日曰,相較於類比開關傳導大的電流並消耗更多的功 〇 每些引線框也可以利用廣為人知的技術形成,具有半蝕 刻的引線部份以形成互連各種不同引線的信號線,不需要 K金封劑(未顯示)中向外延伸。 此外由於半導體晶粒13 0如上所述在拉線焊接至一引線 2時需要一窗框(未顯示),在固定封裝的半導體晶粒230之 月”可放下窗框日寺,可使距離59變,】、,以纟許半導體 1 3 0的拉線焊接。 丄 —半導體裝置20的另一優點是,在拉線焊接期間,由於不 需要窗框側向保留空間,因此距離298可以更進一步地減少 。排除窗框保留空間允許半導體裝置的外部尺寸299變小。 另仫,點疋封裝半導體裝置2〇的複雜度會比客戶的印刷電 :王機板更高。因此客戶可以減少成本,#由不必提供昂 :局部的高密度區’或改變厚度印刷電路,以直接容衲目 前包含在封裝半導體裝置2〇内各種不同的晶粒。圖3是圖2 電壓調整,顯示封裝半導體晶粒壓調整器 ,具有一類比開關70的輸出881,藉由短傳導路徑87〇,耦 =到傳動電晶體130的閘輸入882,該短傳導路徑位在調整 2〇内邯,通常由焊接線56、引線9〇、引線35和焊接線11〇 所形成。 7 84745 15- 1264810 、、士。斤述,藉由縮減提供給在先前技術個別晶粒拉線焊 j泰裎’、月間、用來限制引線框窗框拉線焊接之間額外空間 、、:這個路徑會進一步地縮短。這造成傳導路徑870會 〜,技術的路徑更短(芩見圖1)。由於這個路徑比先前技 術^ S此傳動電日%體可以更快速地開啟和關,使切換 速度更快,因而改良操作。 ^ 一 $而言,電壓調整器20的客戶用途包括耦合半導體晶 。接地8 5 0,以及耦合至來自輸出8 8 0的反饋迴圈8 1 〇 傳動私日日骨豆13〇耦合至接地85〇和變壓器“Ο。變壓器83〇 这過一極體820耦合至輸出88〇。電容器84〇係耦合至接地 850並耦合至當做儲存裝置的輸出880以過濾噪音。 、圖4疋在製造階段半導體裝置2〇的俯視圖,說明用來黏附 才泉綷接11 0和11 5到半導體晶粒丨3 〇的引線框3〇〇和一窗框 620在知封裝半導體晶粒230固定到區域160之前,調低窗 框620以與引線框3〇〇接觸,且拉線焊接ιι〇和ιΐ5在窗框62〇 、視i 635之内進行。窗框62〇如圖所示被壓入引線框3〇〇内 ,以便在拉線焊接流程期間限制或固定引線框3〇〇。應注意 ά t 620重宜區域丨6〇,該區係保留供固定封裝的半導體 曰曰粒230义用,以允許封裝半導體晶粒23〇的所在位子,較 若是裸晶固定在區域16〇時,更靠近半導體13〇。 圖5疋在製造階段半導體裝置2〇的俯視圖,進一步說明當 作引線框矩陣650 —部份的引線框3〇〇,並包括半導體晶粒 1 30和封裝的半導體晶粒23〇。在所有半導體裸晶(包括半導 體晶粒130)都固定到他們個別引線框,而且相關的拉線焊接 84745 -16- 1264810
麦 :5:綠冬巨唾0递:^ 砬.:::Μ…會固定氣Η,:缘牛匡:三;ϋυ : 131 ^ ^ yfil Will ΐ/'Λ 秦去r 辱“ i ’ 口著 X \半、面來回移動,以 车導體裝置20 : ·' —薄層密:封流程|在該流程期 $封::在密:封之後,引線裎6 Μ 嚯足司時.形成引線..65 1和封裝的 圖6顯示半導體裝置20替代具體實施例的橫斷面圖,包括 兩個或更多的封裝半導體晶粒2 3 〇和2 3丨固定或電耦合至引 線框300並以密封劑1〇密封。封裝的半導體晶粒23〇包含有 一晶粒70,固定並電連接到?丨線框2〇〇,並如上以密封劑21〇 復盍。封裝的半導體晶粒23丨包含有一晶粒1 34,固定並電 連接到引線框133,並如上以密封劑211覆蓋。雖然圖中顯示 的是具有類似的封裝類型,但封裝的半導體晶粒23〇和231 可以疋有其他封裝及/或晶粒類型,包括固定到一引線框的 晶粒,例如像球柵陣列、雙内嵌封裝、接針柵陣列等等。 在封裝半導體晶粒230和23 1之間的距離777,可以因上述許 夕理由成為極短的距離,包括形成的每個封裝半導體晶粒 2 3 0或2 3 1具有最小側向%度7 7 4或7 7 5。 此外,雖然未顯示,封裝的半導體裝置23〇及/或231可以 包括像半導體裝置20的半導體裝置,或改為使用不同的固 定或耦合技術,例如像引線框架、球柵陣列、接針引線等 等。 、 圖5半導體裝置2 〇的另一優點是,當不需要保留窗框且不 執行拉線焊接來整合或固定該兩個半導體裝置時,距離777 可以進一步地縮短。這個進一步縮減允許半導體裝置的外 84745 1264810 部尺寸776相較於先前技術為最小值 此外,封裝半導體裝置2〇的複雜度較客卢 、、、 J丨刷電跋i 機板的複雜度要高,但因此客戶可以藉由不必提供昂主。 部的高密度印刷電路區,或較厚的金屬信號線二直:二, 目前包含在封裝半導體裝置20内各種不同的晶•立,= 成本。 本封裝半導體裝置20另一個勝過先前技術的優點是,它 使彳于包含多個晶粒、各種不同的晶粒技術、各種不同的晶 粒尺寸,晶粒間距和互連技術、在單一包裝内形成的系統 万業,變得有成本效率。其他的先前技術系統方案包括將 不同晶粒製造技術整合為單一矽半導體方案,該方案即昂 ”操作困難且會導致晶粒成為侧向比大於上述封裝半導 體裝置20的側向比。 【圖式簡單說明】 圖1是先前技術多晶片模組的橫斷面圖; 圖2是半導體裝置的橫斷面圖; 圖3是套用至一電壓調整器的半導體裝置的具體實施例 之示意圖; 圖4是圖2半導體裝置的俯視圖; 圖5是圖2半導體裝置的第二俯視圖;以及 圖6是半導體裝置另一具體實施例的橫斷面圖。 【圖式代表符號說明】 10 密封材料 20 半導體裝置 84745 -18 - 1264810 21 半導體包裝 30 引線 3 1 引線鎖 35 引線 37 部份 40 引線 45 空洞 46 尺寸或間距 47, 48 丑巨離 49 間隔或間隙 50 焊錫球或焊錫膏 55, 56 焊接線 59 在巨離 60 第一位置 70 晶粒 80 旗標 81 部份 90 引線 97, 98, 99 厚度 110 焊接線 115 焊接線 120 第一位置 130 半導體晶粒 133 引線框 84745 -19- 1264810 134 晶粒 140 旗標 150 引線 160, 170 區域 200 引線框 210 密封材料 211 密封劑 230, 23 1 封裝的半導體裝置 298 ί巨離 299 外部尺寸 300 引線框 500 多功能晶片模組 501 距離 502 傳導路徑 503 間距或距離 510 外部引線 520 印刷電路板 530 電路板信號線 531, 532 信號線 533 銅區域 534 部份 540 晶粒 542 功率MOSFET晶粒 560 拉線 84745 - 20 - 1264810 561 鋁焊接線 590 密封劑 620 窗框 635 窗口 650 引線框 651 引線 774 最小側向寬度 775 寬度 776 外部尺寸 777 在巨離 810 反饋迴圈 820 二極體 830 變壓器 840 電容器 850 接地 870 傳導路徑 871, 872 晶粒塾 880, 881 輸出 882 閘輸入 84745 -21 -
Claims (1)
1264810 拾、申請專利範圍·· 1. 一種半導體裝置,其包括: 一第一引線框; 一第一半導體晶粒電耦合至該第一引線框的一引線; 一第二半導體晶粒;以及 一第二引線框,具有一第一引線,用於電耦合到該第 二半導體晶粒,以及一第二引線,用於固定到該第一引 線框的該引線。 2. 如申請專利範圍第1項之半導體裝置,進一步包括一第 一密封材料覆蓋該第一引線框。 3. 如申請專利範圍第2項之半導體裝置,進一步包括一第 二密封材料覆蓋該等第一和第二引線框。 4. 如申請專利範圍第3項之半導體裝置,進一步包括一第 一焊接線,以一第一材料形成,用於電搞合該第一半導 體晶粒至該第一引線框的該引線。 5. 如申請專利範圍第4項之半導體裝置,進一步包括一第 二焊接線,以一第二材料形成,用於電耦合該第二半導 體晶粒至該第二引線框的該第一引線。 6. 如申請專利範圍第4項之半導體裝置,其中該第一材料 包括金。 7. 如申請專利範圍第5項之半導體裝置,其中該第二材料 包括鋁。 8. 如申請專利範圍第6項之半導體裝置,其中該第一拉線 焊接材料形成為小於0.0 02英吋的直徑。 84745 1264810 9.如申請專利範圍第7項 坪接材料形成為大於“ ^裝置’其中該第二拉線 引線 I。 _如"專利範園第〗項之丰=:1直徑。 、 半寸骨豆裝置,其中該第 框包括一鎳銀合金冷 〃丄枓,用於黏附該金線焊接。 II. 如申請專利範圊 引線 巳圍弟1项心半導體裝置,其中該第 框包括—銅或錯,用於黏附該錯線焊接。 引線 1 2·如申Μ專利乾園第1項之半導體裝置,JL中該第· 框具有-厚度小於該第二引線框。 1 3 ·如申請專利筋囹楚 、 、, 、 靶Ν罘1項 < 半導體裝置,其中一材料的厚 度從該第二弓丨線框的一部份移除,用以形成一引線鎖。 14.如申請專利範園第丨項之半導體裝置,其中一材料的厚 度從一第四引線移除,以形成一互連線。 15_ —種半導體裝置,其包括: 第一引線框; 接針 弟半導體晶粒電轉合至該第一引線框的 以及 一第二引線框,用於固定到該第一引線框。 16.如申請專利範圍第15項之半導體裝置,其中該第一引線 框接針具有一間距小於該第二引線框接針的間距。 1 7· —種用於容納多重半導體晶粒的包裝,包栝: 一具有一區域的第一引線框,用於固定一第一半導體 晶粒,以及 一具有一旗標的第二引線框,用於固定一第二半導 體晶粒,其中該第二引線框固定到該第一引線框的一 84745 l2648l〇 線。 18 19. 20. 21. 22. 23. 24· 25. 26. ,種半導體包裝,包括具有-第-區域的-第一引線框 〜^万;固疋—半導體晶粒,以及一第二區域,用於固定 〜第二引線框。 —種形成-半導體組件之方法,包括: =一第一半導體晶粒固定到一第一引線框; ^第—半導體晶粒固定到一第二引線框;以及 將該第一引線框固定到該第二引線框。 :申睛專利範園第19項之方法,進一步包括將一第一密 、材料置於該等第n引線框之上的步驟。 ^申請專利範園㈣項之方法,進—步包括將—第二密 、才料置於孩第一引線框之上的步驟。 ::申請專利範圍第19項之方法,進一步包括將一 封材料置於該莘裳—在 t罝万、及寺弟一和弟二半導體晶粒之上 如申請專利範圍第π項之太本.彳.一本 封材料置於該第—半導,日;、π將—第二密 ^ 千寸晶粒之上的步驟。 二!,園第19項之方法,其中將該第-半導體晶 疋土 $罘—引線框的步驟進一步包括: ^鎳銀合金塗佈該第—引線框的一部份;以及 柏知一金線焊接從該第―半導體晶粒黏附至塗佈有兮 錄銀合金的該第一引線框的部份。 “ ,申請專利範園第19項之方法,進一步包括將該第一引 、泉框的一引線電耦合至該第二引線框的一引線。 如申請專利範圍第19項之方法,其中將該第二半導體晶 ^745 1264810 粒固定至該第二引線框的步驟進一步包括電耦合該第 二半導體晶粒至該第二引線框。 27. 如申請專利範圍第19項之方法,其中該第一引線框形成 具有一第一厚度’以及該第二引線框形成具有一第二厚 度。 28. 如申請專利範圍第27項之方法,其中該第一引線框厚度 小於該第二引線框厚度。 29. 如申請專利範圍第28項之方法,進一步包括將材料從該 第二引線框的一引線移除,以形成一引線鎖的步驟。 3 0. —種形成一半導體組件之方法,包括: 將一第一半導體晶粒固定到一第一引線框; 將一封裝半導體晶粒固定到該第一引線框;以及 在將該封裝半導體晶粒固定到該第一引線框之後,密 封該第一引線框。 3 1. —種半導體組件,包括·· 一具有一第一厚度的第一引線框; 一第一半導體晶粒電耦合至該第一引線框; 一第二半導體晶粒;以及 一具有一第二厚度的第二引線框,電耦合至該第二半 導體晶粒和該第一引線框。 3 2.如申請專利範圍第3 1項之半導體組件,其中該第一引線 框厚度小於該第二引線框厚度。 3 3 . —種半導體組件,包括: 一第一引線框; 84745 -4- 1264810 一第一半導體晶粒電耦合至該第一引線框的一引線; 一第二引線框; 一第二半導體晶粒電耦合至該第二引線框的一引線 ;以及 一具有一第一引線的第三引線框,用於固定到該第 一引線框,以及一第二引線,用於電耦合到該第二引 線框。 3 4.如申請專利範圍第33項之半導體組件,進一步包括一第 一密封材料覆蓋該第一引線框。 35.如申請專利範圍第34項之半導體組件,進一步包括一第 二密封材料覆蓋該第二引線框。 3 6.如申請專利範圍第35項之半導體組件,進一步包括一第 三密封材料覆蓋該等第一、第二和第三引線框。 3 7. —種半導體包裝,包括一第一引線框,具有一第一區域 ,用於固定一第二引線框,以及一第二區域,用於固定 一第三引線框。 3 8 · —種積體電路,包括: 一第一引線框; 一半導體裝置,用於固定在該第一引線框上; 一半導體組件;以及 一第二引線框,具有一第一區域,用於固定該半導體 組件,以及一第二區域,用於固定該第一引線框。 84745
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US6833290B2 (en) | 2004-12-21 |
TW200306657A (en) | 2003-11-16 |
CN100397639C (zh) | 2008-06-25 |
US6677672B2 (en) | 2004-01-13 |
CN1458691A (zh) | 2003-11-26 |
US20030201520A1 (en) | 2003-10-30 |
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