[go: up one dir, main page]

CN1458691A - 形成多引线框半导体器件的结构和方法 - Google Patents

形成多引线框半导体器件的结构和方法 Download PDF

Info

Publication number
CN1458691A
CN1458691A CN03123276A CN03123276A CN1458691A CN 1458691 A CN1458691 A CN 1458691A CN 03123276 A CN03123276 A CN 03123276A CN 03123276 A CN03123276 A CN 03123276A CN 1458691 A CN1458691 A CN 1458691A
Authority
CN
China
Prior art keywords
lead frame
lead
semiconductor element
wire
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN03123276A
Other languages
English (en)
Other versions
CN100397639C (zh
Inventor
詹姆斯·霍华德·克纳普
斯蒂芬·St·格尔梅恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Publication of CN1458691A publication Critical patent/CN1458691A/zh
Application granted granted Critical
Publication of CN100397639C publication Critical patent/CN100397639C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

半导体器件(20)具有第一引线框(200)，第一半导体管芯(70)与其引线之一电耦连。第二半导体管芯(13)装配到第二引线框(300)上，后者的第一引线(35、150)与第二半导体管芯电耦连，而第二引线(30、35)装配到第一引线框的引线上。

Description

形成多引线框半导体器件的结构和方法
技术领域
本发明一般涉及半导体器件封装以及，更特定地，涉及形成具有不止一个引线框并包含不止一个器件的半导体器件。
背景技术
一般地，同时代的电子器件在设计时总要想着严格的设计标准，例如尺寸、重量和功耗。这样的标准连续地减少，因为，为了实现更强的功能，设计变得越来越复杂。对增强的功能和性能的需求导致元件厂家在单个封装中根据不同技术来集成器件的尝试。
一种方法是在具有导电网络的衬底上安置两块或更多块未封装的半导体管芯，导电网络提供管芯之间的电互连以形成多芯片模块，或MCM。MCM中所用的衬底通常为多层印刷电路板。然后用盖子或密封剂将MCM的衬底盖上，形成完成的封装器件。
在图1中给出了作为电压调节器的现有技术多芯片模块500的一个实施例。如图所示，MCM电压调节器500包括支撑许多管芯540和542的印刷电路板520，其中这些管芯通过导线560、561线焊在印刷电路板迹线530-532上。
在使用混合管芯技术来实现器件500的许多MCM中，典型地，管芯542为功率MOSFET技术的驱动晶体管，而管芯540为模拟技术的电压调节器开关。这样，功率MOSFET管芯542承载大电流所需的线焊为大的铝或铝合金线(例如直径一百二十五微米)，而模拟管芯540的高速信号传输和低衰减所需的线焊为小的金或金合金(例如直径五十微米)。
工具上用来焊接金线的焊头直径大约为两百五十微米，而用于铝线的焊头直径大约为四千微米。所用的不同线焊材料要求迹线具有兼容的表面材料以使和线焊的连接具有最佳的性能和可靠性。在该实施例中，迹线532和迹线531的一部分534至少部分镀上银镍合金以便于和金线焊的连接。功率MOSFET所用的铝焊线561与迹线530和迹线531的铜区533相连。铝线焊在金线焊之前形成，因为焊接金线所用的高温会氧化铜迹线，这将使铝焊具有差的强度和可靠性。
迹线进一步与完成的MCM的外引线510相连，以提供和具有连接间距或距离503的用户印刷电路板的电互连。
在焊接引线之间必须有一个距离501，使得在线焊过程中用于支持衬底的窗框(未示出)不接触所有导线和器件。如上给出的距离导致了模拟开关540的管芯焊点871和驱动晶体管542的管芯焊点872之间长的有效导电路径502。长的有效导电路径降低了信号传输，尤其在需要快速电响应的应用或携带小电流的应用中更是如此。
使用密封剂590将模块与环境隔离以形成完成的多芯片模块。这样形成的MCM尽管价格昂贵，但是空间效率很高，相对于置于用户电路板上个别单独封装的器件来说，它只需要更少的印刷电路板空间。
对于厂商和使用者来说多芯片模块的可靠性是非常重要的。对所用的各个半导体管芯进行功能测试，尤其是高速测试和老化之后的测试是保证可靠性的基本方法。多芯片模块的一个缺点就在于它们非常难以进行测试，因为在这些半导体管芯的接触焊点中只有一些能够通过从封装中延伸出来的引线而与外部测试装置连接。测试还有进一步的问题，因为很难或者不可能在半导体管芯装配到衬底上之前对它们进行完全的测试。此外，一旦各种半导体管芯互相连接起来，它们的特征就改变了；要测量互连产生的寄生效应变得困难——即使并非不可能。在高速时测试尤其困难。这样就无法完全测试多芯片模块中集成管芯芯片的功能，因为无法将测试装置与单个半导体管芯上的单个接触焊点相连。
此外，制作MCM非常困难，因为生产用作衬底的多层印刷电路板很复杂。另外，模块中不同类型的管芯需要不同的组装设备、材料和方法来将它们连接到衬底上。连接引入了进一步的问题。尽管是线焊，但由于在焊接过程中必须使用来压制衬底的窗框以及焊接工具头的尺寸，必须在引线之间为它们留下空间来进行线焊，而这反过来限制了密度。通常，焊线越大，就必须在管芯周围为用来压制衬底的窗口留下更大的面积。
MCM印刷电路板的另一个问题在于它很昂贵，而且要为线焊制作不同材料的迹线的话很复杂。例如，功率器件最好线焊到大而厚的迹线上以传导大的电流和热量，而因为模拟器件所需的速度，模拟器件最好线焊到薄而短的迹线上。MCM的这些问题导致了低产出高成本。
因此，如果有一种形成半导体器件的结构和方法，这种半导体器件具有能使多个半导体管芯集成到单个封装器件中同时又避免现有技术的问题，将是很有利的。
附图说明
图1为现有技术的多芯片模块的剖面图；
图2为一半导体器件的剖面图；
图3为用于电压调节器的半导体器件某一实施方案的示意图；
图4为图2的半导体器件的俯视图；
图5为图2的半导体器件的第二俯视图；以及
图6为半导体器件的一个替代实施方案的剖面图。
具体实施方式
图2中的剖面图示出包括已封装半导体元件或器件230和嵌入半导体封装的半导体管芯130的半导体元件或器件20。已封装半导体器件230装配在引线框300的区域160中而半导体管芯130装配在引线框300的区域170中。用密封剂材料10覆盖引线框300、已封装半导体管芯230以及半导体管芯130来形成完成的半导体器件20。在某一实施方案中，半导体器件20作为电压调节器，已封装半导体器件230为模拟开关而半导体管芯130包括功率晶体管。
已封装半导体管芯230由装配在引线框200上并与其电耦连的半导体器件或管芯70组成，选择引线框200厚度99以提供小的侧向间距或缝隙49。对模拟开关应用来说，厚度99通常为大约两百微米。通过构图并腐蚀金属片来移除材料以电绝缘引线和其它部件，由此形成引线框200。也就是说，相对于引线40和90以及标记(flag)80来说，在腐蚀金属材料来形成引线框200时，要特别注意引线框200的厚度99。引线框的厚度99基本决定了像引线40和90或标记80这些部件之间可以形成的最小缝隙49。因此，由于所用工艺的腐蚀特征，小的侧向尺寸需要厚度99也成比例减小。这样对于小的间距或侧向尺寸，厚度99因此而减小。通常，相对于具有更大侧向尺寸的引线框来说，制造具有减少的侧向尺寸的引线框代价更大。
管芯70通过使用粘合剂或焊料(未示出)与标记80电耦连，通过焊线55与引线40电耦连。与本技术中通常所用的一样，用小的线焊工具(未示出)将焊线55连在管芯70上的第一位置60上，然后将其拉至引线40处并将其与某一部分81热连接，并移开工具。引线40的部分81包括镀上来提高焊线附着力的镍银合金。另外，在线焊过程中，窗框(未示出)压制引线框以使其在线焊过程中不会移动。窗框具有一个开口或窗口，允许线焊工具头在焊接时在窗框的窗口中从管芯向引线移动一个距离48。线焊工具头直径大约为10密耳。类似地，焊线56从管芯70连到引线90。在某一实施方案中，焊线55和56包括金材料。在某一实施方案中，焊线55和56的直径小于五十微米，对于焊线来说，这被认为是一个小的直径。这样的小直径金线是用来提高线焊55-56上承载的信号的传输特性。某一实施方案中的引线框200被密封剂材料210覆盖来形成已封装半导体管芯230。
上述工艺使已封装半导体管芯230具有高密度、低生产成本的优点。此外，通常将已封装半导体管芯230在装配到引线框300上之前进行完整的功能和参数测试。从此可知已封装半导体管芯230是好的器件。如果应用时需要屏蔽或热沉，可使已封装半导体管芯230具有局部的屏蔽或热沉(未示出)，或对于给定的应用，具有其它专门部件。应当注意，上述局部的屏蔽或热沉比将这样的部件装在体积更大的半导体器件20上更节省成本，尤其是在所有元件都不需要屏蔽或热沉的情况下更是如此。在其它实施方案中，已封装半导体管芯230包括引出式、双列直插式、球栅列阵式、引脚式或其它类型的已封装半导体器件。
半导体管芯130装配在引线框300的引线或标记140上并/或与其电耦连。在半导体管芯130包括功率晶体管或其它功耗器件的实施方案中，引线框300的厚度98很大，约为五百微米，以利于散热。厚度98大于厚度99，因为半导体管芯130比已封装半导体管芯230产生更多的热量、传导更多的功率。在腐蚀金属材料以形成引线框300时，与引线30、35、150或标记140的形成相比，更要注意引线框的厚度98。大侧向尺寸或间距47的要求成比例地增加了厚度98，这是由于所用工艺的腐蚀特性。这样，对于大的间距或侧向尺寸，厚度98随之增加。通常，制造具有更大侧向尺寸的引线框比制造具有更小侧向尺寸的引线框更节省成本。
半导体管芯130通过使用粘合剂或焊料(未示出)与标记140电和/或热耦连，并通过焊线110与引线35电和/或热耦连。与本技术中通常所用的一样，用大的线焊工具(未示出)将焊线110连在管芯130上的第一位置120上，然后将其拉至引线35处并将其与某一部分37通过超声作用而连接，并移开工具。引线35的一部分37包括铜或铝，就像腐蚀了的引线框一样。类似地，焊线115将半导体管芯130与引线150相连。引线框300没有镀上镍银合金材料，因为对于连接像焊线110和115这样的铝焊线来说无需这样的镀层。因此，可以低成本生产引线框300。
引线框200和300比印刷电路板更简单且制造成本更低，因为印刷电路板是这样形成的：相继叠加电介质层和导电或金属材料层并腐蚀金属层，留下作为导电迹线或引线且由下层电介质层支撑的金属区域。与之相反，引线框是这样形成的：腐蚀、研磨、压印或反过来从金属薄片上去掉材料以形成导电迹线。在形成迹线时，没有下层电介质材料来支撑它们，并且无需叠加过程，因此引线框更易制造且具有相对较低的成本。
如图所示，通常引线框300在引线150、140、35和30上具有空白45以及引线锁(leadlock)31。通过从引线框300上去掉厚度97的材料，可形成各种尺寸的引线锁，通常包括矩形、凹角形、尖角形或圆形。此外，如上所述，在线焊过程中，窗框(未示出)压制引线框，以使其在线焊过程中不会移动。窗框具有一个窗口，允许线焊工具头在焊接时在窗框的窗口中从管芯向引线移动一个距离47。在某一实施方案中，焊线110或115包括铝材料。
在某一实施方案中，焊线110或115包括直径超过三百五十微米的焊线。这样大直径的铝线是承载半导体管芯130产生的大电流所必须的。对于直径三百五十微米的铝线，通常线焊工具头的直径大约为四千微米。
一旦半导体管芯130如上所述装配到引线框300上，则利用，例如，焊球或焊膏50将已封装半导体管芯230装到引线框300上或与其电耦连。焊膏工艺与将半导体管芯130装到或电耦连到引线框300上是兼容的，与用于连接焊线110和115的工艺也是兼容的，也就是说，机械和电学特性都没有改变。然后用密封剂10覆盖引线框300来形成半导体器件20。半导体器件20具有用于和用户印刷电路板相连的侧向尺寸或间距46。尺寸46为用户的电路板上相邻引线之间的最小间距，且通常大于侧向尺寸48或47中的较小者。
如上形成半导体器件20的一个优点在于：可用更薄的金属来形成引线框200以获得精细间距，最大限度地减小了电路寄生效应并提高了信号的传输；而引线框300可用更厚的材料来制造，利用了使半导体管芯130工作所需的低的热阻和电阻。也就是说，可利用不同厚度的引线框来适应具有不同封装要求——例如热导设计、装配技术、成本、功能测试、电屏蔽或线焊——的半导体管芯。在上面的实施例中，用来装配驱动晶体管的引线框的厚度比模拟开关的厚度大的多，因为与模拟开关相比，驱动晶体管传导大电流且消耗更多的功率。
这些引线框也可像本技术中熟知的那样具有引线的半腐蚀部分，以形成将各个引线互连而又不从密封剂(未示出)向外延伸的迹线。
此外，半导体管芯130需要上面提到的窗框(未示出)用于和引线框之间的线焊，因此，由于可在装配已封装半导体管芯230之前向下安放窗框来进行半导体管芯130的线焊，从而可将距离59做得较小。
半导体器件20的又一优点在于，由于在线焊过程中无需窗框侧向预留空间，可进一步减小距离298。取消窗框预留空间使得半导体器件的外部尺寸299变小。另一优点在于已封装半导体器件20的复杂度可高于用户的印刷电路母板。这样，用户无需提供昂贵的局部高密度或改变厚度的印刷电路的区域即可直接适应现在容纳在已封装半导体器件20中的各个管芯，从而节省了成本。图3为图2的电压调节器的示意图，示出已封装半导体管芯或电压调节器20，其模拟开关70的输出881与驱动晶体管130的栅极输入882通过在调节器20内部通常由焊线56、引线90、引线35以及焊线110形成的短导电通路870相连。
如上所述，通过消除在线焊之间为现有技术的单管芯线焊工艺中用于压制引线框的窗框给出额外空间的需要，可进一步缩短该通路。这给出了远短于现有工艺的通路(参见图1)的导电通路870。由于该通路短于现有工艺，驱动晶体管可进行更快的开关，使得更快的开关速度和改进的工作成为可能。
通常，用户对电压调节器20的使用包括将半导体管芯70与地线850耦连，并从输出880与反馈环810耦连。驱动晶体管130与地线850和变压器830耦连。变压器830通过二极管820与输出880耦连。电容840与地线850和输出880耦连，作为存储器件并用于过滤噪声。
图4为半导体器件20在某一制造步骤中的俯视图，示出引线框300以及用于将线焊110和115与半导体管芯130相连的窗框620。在将已封装半导体管芯230装配到区域160上之前，降下窗框620使其与引线框300相触，在窗框620的窗口635中制作线焊110和115。如图所示，窗框620被压在引线框300上以便在线焊过程中压制或保护引线框300。注意到窗框620与为已封装半导体管芯230的装配而预留的区域160重叠，与在区域160中装配裸管芯相比，这使得已封装半导体管芯230可以更靠近半导体130。
图5为半导体器件20在某一制造步骤中的俯视图，进一步示出作为引线框矩阵650一部分的引线框300，其中包括半导体管芯130和已封装半导体管芯230。在所有未封装半导体管芯(包括半导体管芯130)装配到它们相应的引线框上并且相关的线焊都已形成之后，已封装半导体管芯230装配导引线框300上。
然后对引线框矩阵650进行密封剂涂敷工艺，期间，用密封剂10密封引线框300。在密封之后，沿X和Y平面将引线框650切割成单个，同时形成引线651和已封装半导体器件20。
图6示出半导体器件20的一个替代实施方案的剖面图，该替代实施方案包括两个或更多个装配在引线框300上或与其电耦连并且用密封剂10密封的已封装半导体管芯230和231。已封装半导体管芯230由装配在引线框200上并与其电耦连且像上面那样用密封剂210覆盖的管芯70组成。已封装半导体管芯231由装配在引线框133上并与其电耦连且类似于上面那样用密封剂211覆盖的管芯231。尽管所示的已封装半导体管芯230和231具有类似的封装类型，它们可以是其它封装和/或管芯类型，它们包括装配到引线框——例如球栅列阵、双列直插封装、引脚栅列阵——上的管芯。由于上面的原因——包括每个已封装半导体管芯230或231都具有最小侧向宽度774或775，已封装管芯230和231之间的距离777可以极小。
此外，尽管没有示出，但是已封装半导体器件230和/或231都可包括像半导体器件20那样的半导体器件，或者使用不同的装配或连接技术——例如引出框、球栅列阵、引脚引线等。
图5的半导体器件20的另一优点在于，由于无需进行线焊来集成或装配这两个半导体器件，故而无需预留窗框，因此可以进一步减小距离777。这使得半导体器件的外部尺寸776与现有技术相比为最小。
此外，已封装半导体器件20的复杂度可高于用户的印刷电路母板，用户无需提供昂贵的局部高密度印刷电路板的区域或更厚的金属迹线即可直接适应现在容纳在已封装半导体器件20中的各个管芯，从而节省了成本。
已封装半导体器件20相对于现有技术的又一优点在于，它使得由多管芯、不同管芯技术、不同管芯尺寸、管芯间距以及互连技术组成的系统解决方案能够以尽量低的成本形成在单个封装中。其它现有技术的系统解决方案包括将各种管芯生产技术集成到单个硅半导体解决方案中，这既费钱又困难，而且还会导致侧向比例大于上述已封装半导体器件20的管芯。

Claims (38)

1.一种半导体器件，其特征在于：
第一引线框；
第一半导体管芯，与第一引线框的引线电耦连；
第二半导体管芯；以及
第二引线框，具有用于和第二半导体管芯电耦连的第一引线，以及用于装配到第一引线框的引线上的第二引线。
2.根据权利要求1的半导体器件，进一步包括覆盖第一引线框的第一密封材料。
3.根据权利要求2的半导体器件，其特征进一步在于，覆盖第一和第二引线框的第二密封材料。
4.根据权利要求3的半导体器件，其特征进一步在于，由第一材料形成的第一焊线，用于将第一半导体管芯与第一引线框的引线电耦连。
5.根据权利要求4的半导体器件，其特征进一步在于，由第二材料形成的第二焊线，用于将第二半导体与第二引线框的第一引线电耦连。
6.根据权利要求4的半导体器件，其中第一材料包括金。
7.根据权利要求5的半导体器件，其中第二材料包括铝。
8.根据权利要求6的半导体器件，其中第一焊线材料形成小于0.002英寸的直径。
9.根据权利要求7的半导体器件，其中第二焊线材料形成大于0.014英寸的直径。
10.根据权利要求1的半导体器件，其中第一引线框包括镍银合金镀层，用于连接金线焊。
11.根据权利要求1的半导体器件，其中第二引线框包括铜或铝，用于连接铝线焊。
12.根据权利要求1的半导体器件，第一引线框的厚度小于第二引线框。
13.根据权利要求1的半导体器件，其中从第二引线框的一部分上去掉一定厚度的材料用于形成引线锁。
14.根据权利要求1的半导体器件，其中从第四引线上去掉一定厚度的材料以形成互连线。
15.一种半导体器件，其特征在于：
第一引线框；
第一半导体管芯，与第一引线框的一个引脚电耦连；以及
第二引线框，用于装配到第一引线框上。
16.根据权利要求15的半导体器件，其中第一引线框引脚的间距小于第二引线框的引脚的间距。
17.一种封装，用于容纳多个半导体管芯，其特征在于：
第一引线框，具有用于装配第一半导体管芯的区域；以及
第二引线框，具有用于装配第二半导体管芯的区域，其中第二引线框装配到第一引线框的一个引线上。
18.一种半导体封装，其特征在于，第一引线框，具有用于装配半导体管芯的第一区域和用于装配第二引线框的第二区域。
19.一种形成半导体元件的方法，其特征在于：
将第一半导体管芯装配到第一引线框上；
将第二半导体管芯装配到第二引线框上；以及
将第一引线框装配到第二引线框上。
20.根据权利要求19的方法，其特征进一步在于，在第一和第二引线框上配置第一密封材料的步骤。
21.根据权利要求20的方法，其特征进一步在于，在第一引线框上配置第二密封材料的步骤。
22.根据权利要求19的方法，其特征进一步在于，在第一和第二半导体管芯上配置第一密封材料的步骤。
23.根据权利要求22的方法，其特征进一步在于，在第一半导体管芯上配置第二密封材料的步骤。
24.根据权利要求19的方法，其中将第一半导体管芯装配到第一引线框上的步骤进一步包括：
用镍银合金涂镀第一引线框的一部分；以及
将金线焊从第一半导体管芯连接到第一引线框镀有镍银合金的部分。
25.根据权利要求19的方法，其特征进一步在于，将第一引线框的一个引线与第二引线框的一个引线电耦连。
26.根据权利要求19的方法，其中将第二半导体管芯装配到第二引线框上的步骤进一步包括将第二半导体管芯与第二引线框电耦连。
27.根据权利要求19的方法，其中第一引线框形成为具有第一厚度，第二引线框形成为具有第二厚度。
28.根据权利要求27的方法，其中第一引线框厚度小于第二引线框厚度。
29.根据权利要求28的方法，其特征进一步在于，从第二引线框的一个引线上移除材料以形成引线锁的步骤。
30.一种形成半导体元件的方法，其特征在于：
将一个第一半导体管芯装配到第一引线框上；
将一个已封装半导体管芯装配到第一引线框上；以及
在将已封装半导体管芯装配到第一引线框上之后密封第一引线框。
31.一种半导体元件，其特征在于：
第一引线框，具有第一厚度；
第一半导体管芯，与第一引线框电耦连；
第二半导体管芯；以及
第二引线框，具有第二厚度，与第二半导体管芯以及第一引线框电耦连。
32.根据权利要求31的半导体元件，其中第一引线框厚度小于第二引线框厚度。
33.一种半导体元件，其特征在于：
第一引线框；
第一半导体管芯，与第一引线框的一个引线电耦连；
第二引线框；
第二半导体管芯，与第二引线框的一个引线电耦连；以及
第三引线框，具有用于装配到第一引线框上的第一引线，以及用于和第二引线框电耦连的第二引线。
34.根据权利要求33的半导体元件，其特征进一步在于，第一密封材料，覆盖第一引线框。
35.根据权利要求34的半导体元件，其特征进一步在于，第二密封材料，覆盖第二引线框。
36.根据权利要求35的半导体元件，其特征进一步在于，第三密封材料，覆盖第一、第二和第三引线框。
37.一种半导体封装，其特征在于，第一引线框，具有用于装配第二引线框的第一区域，以及用于装配第三引线框的第二区域。
38.一种集成电路，其特征在于：
第一引线框；
半导体器件，用于装配在第一引线框上；
半导体元件；以及
第二引线框，具有用于装配半导体元件的第一区域，以及用于装配第一引线框的第二区域。
CNB031232760A 2002-04-26 2003-04-25 形成多引线框半导体器件的结构和方法 Expired - Lifetime CN100397639C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/133,527 US6677672B2 (en) 2002-04-26 2002-04-26 Structure and method of forming a multiple leadframe semiconductor device
US10/133,527 2002-04-26

Publications (2)

Publication Number Publication Date
CN1458691A true CN1458691A (zh) 2003-11-26
CN100397639C CN100397639C (zh) 2008-06-25

Family

ID=29248994

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031232760A Expired - Lifetime CN100397639C (zh) 2002-04-26 2003-04-25 形成多引线框半导体器件的结构和方法

Country Status (3)

Country Link
US (2) US6677672B2 (zh)
CN (1) CN100397639C (zh)
TW (1) TWI264810B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100378934C (zh) * 2004-01-07 2008-04-02 飞思卡尔半导体公司 倒装芯片四方扁平无引脚封装方法
US7551455B2 (en) 2006-05-04 2009-06-23 Cyntec Co., Ltd. Package structure
CN100505244C (zh) * 2006-05-12 2009-06-24 乾坤科技股份有限公司 封装结构
CN1855477B (zh) * 2005-03-29 2010-05-26 三洋电机株式会社 电路装置
CN102812551A (zh) * 2009-12-10 2012-12-05 美国国家半导体公司 用于多引线框堆叠封装的导流条和模空腔条结构
CN105118818A (zh) * 2015-07-20 2015-12-02 东南大学 一种方形扁平无引脚封装结构的功率模块
CN111933534A (zh) * 2019-05-13 2020-11-13 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
WO2025020417A1 (zh) * 2023-07-26 2025-01-30 达尔科技股份有限公司 半导体芯片封装件及其制造方法

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2385984B (en) * 2001-11-07 2006-06-28 Micron Technology Inc Semiconductor package assembly and method for electrically isolating modules
CN1937223A (zh) * 2002-02-21 2007-03-28 松下电器产业株式会社 半导体装置
US6734044B1 (en) * 2002-06-10 2004-05-11 Asat Ltd. Multiple leadframe laminated IC package
JP4283514B2 (ja) 2002-09-24 2009-06-24 株式会社日立製作所 電子回路装置
JP2004237658A (ja) * 2003-02-07 2004-08-26 Minolta Co Ltd 電気機器
US6927483B1 (en) * 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
CN100490140C (zh) * 2003-07-15 2009-05-20 飞思卡尔半导体公司 双规引线框
TWI233674B (en) * 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof
US6859951B1 (en) * 2003-09-09 2005-03-01 Toilet accessory concealment and toilet bowl evacuation apparatus
JP2005116687A (ja) * 2003-10-06 2005-04-28 Renesas Technology Corp リードフレーム、半導体装置及び半導体装置の製造方法
US7230321B2 (en) * 2003-10-13 2007-06-12 Mccain Joseph Integrated circuit package with laminated power cell having coplanar electrode
US7557433B2 (en) 2004-10-25 2009-07-07 Mccain Joseph H Microelectronic device with integrated energy source
WO2005057617A2 (en) * 2003-12-02 2005-06-23 Great Wall Semiconductor Corporation Bond wireless package
WO2005059957A2 (en) * 2003-12-12 2005-06-30 Great Wall Semiconductor Corporation Metal interconnect system and method for direct die attachment
US20060138631A1 (en) * 2003-12-31 2006-06-29 Advanced Semiconductor Engineering, Inc. Multi-chip package structure
TWI283467B (en) * 2003-12-31 2007-07-01 Advanced Semiconductor Eng Multi-chip package structure
US7262494B2 (en) * 2005-03-16 2007-08-28 Freescale Semiconductor, Inc. Three-dimensional package
US8120153B1 (en) 2005-09-16 2012-02-21 University Of Central Florida Research Foundation, Inc. High-temperature, wirebondless, injection-molded, ultra-compact hybrid power module
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8310060B1 (en) * 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8067271B2 (en) * 2006-09-15 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with encapsulation lock
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US8125077B2 (en) * 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US9761435B1 (en) * 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US7768105B2 (en) * 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US7598123B2 (en) * 2007-03-02 2009-10-06 Semiconductor Components Industries, L.L.C. Semiconductor component and method of manufacture
US8237268B2 (en) 2007-03-20 2012-08-07 Infineon Technologies Ag Module comprising a semiconductor chip
US7683463B2 (en) * 2007-04-19 2010-03-23 Fairchild Semiconductor Corporation Etched leadframe structure including recesses
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
US8063470B1 (en) * 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
US9947605B2 (en) * 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
DE102008051928A1 (de) * 2008-10-16 2010-04-22 Osram Opto Semiconductors Gmbh Elektrischer Anschlussleiter für ein Halbleiterbauelement, Halbleiterbauelement und Verfahren zur Herstellung eines elektrischen Anschlussleiters
US8367476B2 (en) * 2009-03-12 2013-02-05 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US20100252918A1 (en) * 2009-04-06 2010-10-07 Jiang Hunt H Multi-die package with improved heat dissipation
US9449900B2 (en) 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US8222716B2 (en) * 2009-10-16 2012-07-17 National Semiconductor Corporation Multiple leadframe package
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8368189B2 (en) 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US8871571B2 (en) 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
JPWO2012011210A1 (ja) * 2010-07-22 2013-09-09 パナソニック株式会社 半導体装置及びその製造方法
US8519519B2 (en) * 2010-11-03 2013-08-27 Freescale Semiconductor Inc. Semiconductor device having die pads isolated from interconnect portion and method of assembling same
US10522518B2 (en) * 2010-12-23 2019-12-31 Bench Walk Lighting, LLC Light source with tunable CRI
US8501517B1 (en) 2012-04-09 2013-08-06 Freescale Semiconductor, Inc. Method of assembling pressure sensor device
JP2013219213A (ja) * 2012-04-10 2013-10-24 Shinko Electric Ind Co Ltd 積層型半導体装置及びその製造方法
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
DE102014114933B4 (de) 2014-10-15 2021-08-12 Infineon Technologies Austria Ag Halbleiterbauelement
KR102376119B1 (ko) * 2015-03-19 2022-03-17 인텔 코포레이션 이면 도전성 플레이트를 가진 무선 다이 패키지
US10269686B1 (en) 2015-05-27 2019-04-23 UTAC Headquarters PTE, LTD. Method of improving adhesion between molding compounds and an apparatus thereof
US9917038B1 (en) 2015-11-10 2018-03-13 Utac Headquarters Pte Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
US12243911B2 (en) * 2019-12-09 2025-03-04 Texas Instruments Incorporated Integrated circuit package for isolation dies

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471151A (en) * 1990-02-14 1995-11-28 Particle Interconnect, Inc. Electrical interconnect using particle enhanced joining of metal surfaces
US5147815A (en) * 1990-05-14 1992-09-15 Motorola, Inc. Method for fabricating a multichip semiconductor device having two interdigitated leadframes
US5280193A (en) * 1992-05-04 1994-01-18 Lin Paul T Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate
US5243498A (en) 1992-05-26 1993-09-07 Motorola, Inc. Multi-chip semiconductor module and method for making and testing
WO1996006459A1 (en) 1994-08-25 1996-02-29 National Semiconductor Corporation Component stacking in multi-chip semiconductor packages
JPH0922980A (ja) * 1995-07-05 1997-01-21 Toshiba Corp マルチチップモジュールおよびその製造方法
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6284570B1 (en) 1998-12-28 2001-09-04 Semiconductor Components Industries Llc Method of manufacturing a semiconductor component from a conductive substrate containing a plurality of vias
KR100379835B1 (ko) 1998-12-31 2003-06-19 앰코 테크놀로지 코리아 주식회사 반도체패키지및그제조방법
JP3876088B2 (ja) 1999-01-29 2007-01-31 ローム株式会社 半導体チップおよびマルチチップ型半導体装置
TW415056B (en) 1999-08-05 2000-12-11 Siliconware Precision Industries Co Ltd Multi-chip packaging structure
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지
KR100336481B1 (ko) * 2000-08-11 2002-05-15 윤종용 재생가능한 멀티 칩 패키지와 그를 이용한 메모리 카드
JP2002076216A (ja) * 2000-08-29 2002-03-15 Sony Corp 半導体装置パッケージ及びその作製方法
TW565925B (en) * 2000-12-14 2003-12-11 Vanguard Int Semiconduct Corp Multi-chip semiconductor package structure process

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100378934C (zh) * 2004-01-07 2008-04-02 飞思卡尔半导体公司 倒装芯片四方扁平无引脚封装方法
CN1855477B (zh) * 2005-03-29 2010-05-26 三洋电机株式会社 电路装置
US7551455B2 (en) 2006-05-04 2009-06-23 Cyntec Co., Ltd. Package structure
CN100505244C (zh) * 2006-05-12 2009-06-24 乾坤科技股份有限公司 封装结构
CN102812551A (zh) * 2009-12-10 2012-12-05 美国国家半导体公司 用于多引线框堆叠封装的导流条和模空腔条结构
CN102812551B (zh) * 2009-12-10 2015-07-22 美国国家半导体公司 用于多引线框堆叠封装的导流条和模空腔条结构
CN105118818A (zh) * 2015-07-20 2015-12-02 东南大学 一种方形扁平无引脚封装结构的功率模块
CN105118818B (zh) * 2015-07-20 2018-08-21 东南大学 一种方形扁平无引脚封装结构的功率模块
CN111933534A (zh) * 2019-05-13 2020-11-13 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN111933534B (zh) * 2019-05-13 2023-01-24 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
WO2025020417A1 (zh) * 2023-07-26 2025-01-30 达尔科技股份有限公司 半导体芯片封装件及其制造方法

Also Published As

Publication number Publication date
US20030209804A1 (en) 2003-11-13
US6833290B2 (en) 2004-12-21
TW200306657A (en) 2003-11-16
CN100397639C (zh) 2008-06-25
TWI264810B (en) 2006-10-21
US6677672B2 (en) 2004-01-13
US20030201520A1 (en) 2003-10-30

Similar Documents

Publication Publication Date Title
CN100397639C (zh) 形成多引线框半导体器件的结构和方法
CN100352047C (zh) 用于半导体器件的非铸模封装
CN100433300C (zh) 封装组件和半导体封装
CN1065662C (zh) 半导体芯片封装及其制造方法
KR0153595B1 (ko) 반도체 장치와 반도체 장치의 생산방법 및 반도체 모듈
US8472196B2 (en) Power module
US6956741B2 (en) Semiconductor package with heat sink
CN1833317A (zh) 用于引线接合焊球阵列的接地拱顶
US20100270667A1 (en) Semiconductor package with multiple chips and substrate in metal cap
CN101060087A (zh) 电极及其制造方法,以及具有该电极的半导体器件
CN110176451A (zh) 功率模块及其封装方法
US10068819B2 (en) Semiconductor device
CN101924046A (zh) 在半导体器件中形成引线键合的方法
CN1355567A (zh) 将电路和引线框的功率分布功能集成到芯片表面上的电路结构
CN101794760B (zh) 高电流半导体功率器件小外形集成电路封装
CN114388490A (zh) 智能功率模块的封装结构及其封装方法
CN1113608A (zh) 用于半导体器件的引线框架
CN112885804A (zh) 贴片式光伏旁路模块及其封装工艺
CN1134839C (zh) 引线框架及涂敷引线框架的方法
CN101179034A (zh) 无引脚扁平封装类密脚型器件的锡膏印刷钢网开口方法
CN215680689U (zh) 一种Micro LED封装结构
CN101026133A (zh) 具有散热片的半导体封装结构及其制造方法
CN1577824A (zh) 制造一种直接芯片连接装置及结构的方法
US20070126106A1 (en) Multi-chip semiconductor connector and method
US11227820B2 (en) Through hole side wettable flank

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20080625

CX01 Expiry of patent term