TWI224367B - HV device with improved punch through voltage and a method integrated with a LV device process for forming the same - Google Patents

Abstract

A HV device with improved punch through voltage and a method integrated with a LV device process for forming the same. A semiconductor silicon substrate has a HV device region and a LV device region, and a gate structure is formed within the HV device region. A lightly doped area is formed in the silicon substrate and in a lateral area of the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped area is formed in the lightly doped area and in a lateral area of the spacer. A transverse interval is kept between the heavily doped area and the adjacent lightly doped area.

Description

1224367 V. Description of the invention (1) The technical field to which the invention belongs: The present invention relates to an integrated manufacturing process of low-voltage components and high-voltage components, and in particular, to a manufacturing method of matching low-voltage components of high-voltage components in line reduction design, It is possible to increase the high voltage element = punch through voltage and bulk-drain voltage (VBD). ○ Previous technology: In today's semiconductor technology, in order to achieve the operation of a single-chiP system It integrates the controller, memory, low-voltage operation circuit, and pressure operation power components on a single chip. The research and development of power components include vertical = rate metal-oxide-semiconductor (VDM0S), insulation gate There are several types of bipolar transistor (IGBT) and lateral power transistor (LDM0S). The research and development purpose is to improve the power conversion efficiency to reduce energy loss. Since it is necessary to simultaneously promote high-voltage components and low-voltage components with different breakdown voltage requirements on a single chip, how to integrate the semiconductor process so that the high-voltage component process can be matched with the low-voltage component process has become an important issue at present. In the traditional high-voltage device manufacturing process, a polycrystalline silicon gate on a silicon substrate is used as a mask to form a self-aligned source / drain region in the Shixi substrate, which is provided as a double diffusion drain (d 〇uble diffused drain (DDD) ... Generally, in order to suppress the hot electron effect and increase the breakdown voltage of the source / drain region, a light doped drain (LDD) structure is formed below the source / drain region of the silicon substrate. The DDD structure is then completed by a south temperature-driven process. However, in high voltage components as well as low

1224367 V. Description of the invention (2) In the process integration of 7L parts, because the structure and thermal budget of the two are different, the process of high-temperature driving the LDD structure in the high-voltage component area to form the ODD structure will affect the process. The diffusion region of the low-voltage element region cannot ensure the stability of its electrical quality. U.S. Patent No. 6,509,2 43 proposes an integrated process of low-voltage components and high-voltage components. The following is a detailed description with reference to the attached diagrams A through E. As shown in FIG. 1A, a semiconductor silicon substrate 10 has a high-voltage element region 12H and a low-voltage element region 12L defined on the surface. First, a silicon nitride insulating layer 6 is deposited on the surface of the semiconductor silicon substrate 10, and then the pattern of the silicon nitride insulating layer 16 is defined within the range of the high-voltage element region 12h and the low-voltage element region to expose a predetermined isolation region. . Then, an oxidation layer is formed on the exposed predetermined isolation region of the semiconductor silicon substrate 10 to form an oxidation isolation region 14 which can isolate the high-voltage element region 12 and the low-voltage element region 12 L. Then, as shown in FIG. 1 β, a surface of the semiconductor silicon substrate 10 is covered with a photoresist layer 18 to expose only the predetermined source / drain region of the high-voltage element region 12 2 Η. Then, an ion implantation process is performed to form a lightly doped region 20 on the surface of the semiconductor silicon substrate 10 in the exposed region of the high-voltage element region 12 ′. Next, as shown in FIG. 1C, after the photoresist layer 18 and the silicon nitride insulating layer 16 are sequentially removed, a high-temperature driving process is performed to promote the lightly doped region 20 to diffuse down into the semiconductor silicon substrate 10 and The lateral diffusion is below the field oxidation isolation region 14 and becomes a gradient diffusion region 20a. Then, as shown in FIG. 1D, a gate structure 26Η of a high voltage element and a gate structure 26Η of a high voltage element are formed in the high voltage element region 2H and the low voltage element region 12L, respectively.

1224367 V. Description of the invention (3) = piezo element, gate structure 26L, where each gate structure is composed of Η, 2 gate system oxide layer 22, and a polycrystalline silicon gate layer 24, and The gradient diffusion region 20a is located in the semiconductor silicon 2 ^ 10 around the gate structure 26H. Next, as shown in FIG. 1E, after the high-voltage element region 12H is shielded with a photoresist, the gate structure 26L is used as a cover The curtain is subjected to a lightly doped ion implantation process to form an LDD structure 28 in the semiconductor silicon substrate 10 in the low-voltage element region 12L. Subsequently, after removing the light-blocking mask of the high-voltage element region 12H, the gate structures are respectively 2 6 A side wall 30 is formed on the side walls of 26 and 26L, and then gate structures 26H, 26L, and side wall 30 are used as a mask to perform a heavily doped ion implantation process, which can be used in the gradient diffusion region 20a of the high-voltage element region 12L. A heavily doped region 32H can be formed in the LDD structure, and a source / drain diffusion region 32L can be simultaneously formed in the LDD structure 28 of the low voltage element region 12L. In this way, in the high voltage element region 12L1, the gradient diffusion region 20a and the heavy diffusion region Doped region 3 The 2H combination system is constituted as a DDD structure. However, under the design of reducing the line width of the local voltage component, the above-mentioned technology simultaneously performs the heavy doped ion implantation process of the high-voltage component area 12H and the low-voltage component area 12L, which is not easy. Controls the bulk-drain voltage (VBD) of the high-voltage components. Moreover, as the channel length becomes shorter, if the process of the high-voltage components cannot be improved to increase the effective source / drain distance, electronic penetration will also be encountered. The problem of punch through. Summary of the invention: In view of this, the object of the present invention is to provide a high-voltage component applied to a line width reduction design and a manufacturing method matching the process of the low-voltage component, which can perform the high-voltage component in different steps. Heavy doping from low voltage components

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Case No. 1224367 V. Description of the invention (5) The heavily doped region formed in the high-voltage element region of the gate junction low-voltage element region; the layer 'covers the surface; the first and second heavily-doped wall subregions are formed in the region , Where the first loose spacing. Removing the second automatic alignment layer, and performing a lightly doped region to a metalloid silicide embodiment _a 92106485 on the sidewall of the structure to perform a first sidewall sub-side removal of the two low-resistance element photoresist layers The hybrid ion implanted photoresist protects the oxygen and the heavily doped year; forms a lightly doped photoresist layer with a first heavily doped off-edge; the morphology and the surface cover the low process to the side of the chemical layer The shape region and the adjacent photoresist layer; in the desiliconization process, a photoresist layer is exposed in the region, and a photoresistive holding element area is formed in the impurity region of the sub-planting process; the south pressure element forms a second-heavy sidewall; In addition to the photoresistor, it is guaranteed to form a cover on the surface of the gate, so that the entire table of the protective oxide and the doping interval on the side of the entrance area maintain the protective oxidation structure, and the automatic pairing In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings, and the detailed description is as follows: Please refer to FIGS. 2A to 2E, which show This invention is low Process sectional element integrated with the high pressure member of Fig. First, as shown in FIG. 2A, a semiconductor silicon substrate 40 is provided, a low-voltage element region 42L and a high-voltage element region 42A are defined on the surface, and a field oxidation isolation region is included to separate the high-voltage element region 4 2 42 Low-voltage component area 42L. And in the low element area 42L and the high voltage element area

0516-9425TWFl (nl); 91011; cherry.ptc 1224367 Case No. 92106485 V. Description of the invention (6) On the surface of the semiconductor dream substrate 4G in the domain 42H, the open structure of the part is 50L and the second part of the high voltage component-low 7 The semiconductor stone substrates around the structures 50L and 50H are divided into 20H and 2 = heteroregions 52, such as N-ion doped regions. Wherein, each = 50L, 50Η is composed of: the gate insulating layer 46 and a gate conductive layer; and the side wall of the gate structure 50L, 50Η is made with an isolated field oxidation isolation region 44 according to the present invention. Second doped region: the fabrication method of the structure 50L, 50 侧壁 and the side wall 54, the sequence M,, M, and M, and then 'as shown in Figure 2B' on the semiconductor silicon substrate 40 Table 2 a first photoresist The layer 56 is used to cover the high-voltage element region 4A, and the pressure element region 42L. Subsequently, a first heavy ^ = low 57 is performed. For example, an ion doping process is performed using a low pressure element Γ domain to form a first heavy doping region 58 ;; such as = of the = field. So-I, in the low-voltage element region 42L, the first heavy region is used as a source and region, and the lightly doped region is used as the second region. Then, as shown in FIG. 2C, the first The photoresist layer 56 removes a photoresist protection oxide (RP0) layer 60 deposited on the surface of the semiconductor silicon substrate 40 to cover the low-voltage element 42L and the high-voltage element region 42H. Then, as shown in the figure, a second photoresist layer 62 covers the low-voltage device region 42L, and then a one-on-one, heavy ion implantation process 63 is performed, for example, an N + ion doping process, using The pole structure 50H, the side wall 54 and the _ part of the Rp〇 layer 60W mask can be formed in the lightly doped region 5 2 in the exposed part of the region — a month of the correction domain to form a weight of 0516-9425 ™ Fl (nl); 91011; cherry.ptc Page 10, 1224367, Amendment No. 921064 Milk 5. Description of the invention (7) Doped region 64, for example, N + ion doped region secret. Bowl a (RPO denslfy), I ^ ^ ^ ^ ,: to achieve. #Purpose is to densify the oxide layer of the RP0 layer. 2) The force, the selectivity of the process, and the high-temperature drive system; homogenize and restore the substrate lattice damage caused by ion implantation, and simultaneously activate (Active) A doped region of both the chirped element and the low voltage element. Such an RP0 layer 60 on the surface of the wall 54 can be used as a mask for the second heavy ion implanted plutonium. Therefore, the effective distance L of the second heavily doped region 64 as the source / electrode region will follow the Rp0 layer. The thickness of 60 is increased and the length is increased. I increases the effective channel length, thereby improving the punch through voltage of the high-voltage component and the bulk-drain voltage (VBD). Finally, as shown in FIG. 2E, after the second photoresist layer 62 and the Rp0 layer 60 are sequentially removed, an automatic alignment silicidation process (sal icidat ion process) is performed. A self-aligned metal silicide (self-aligned 31 丨 10: 1 (16, commonly referred to as 1 丨 (: 丨 (^)) layer 66 is formed on the exposed surfaces of the electrode regions 52 and 64 to reduce the resistance value. For example, when the material of the gate conductive layer 4 g is polycrystalline, a metal layer can be sputtered on the surface of the semiconductor silicon substrate 40 with a thickness ranging from 300 to 800 A. The material can be Cobalt or titanium is selected to cover the exposed surfaces of the gate conductive layer 48, the side walls 54 and the source / drain regions 52, 64. Then, a heat treatment process is performed on the metal layer to diffuse the metal atoms of the metal layer downwards' And silicidation reaction with polycrystalline silicon and silicon atoms on the silicon substrate. As a result, TiSi2 4c〇Si2 material will be formed at the exposed surface. As it did not happen 1 Page 11 0516-9425TWFl (nl); 91011; cherry.ptc 1224367 5 2. Description of the invention (The metal layer of the phantom reaction is removed by selective etching) ^ Compared with the conventional technology, the technology of the present invention has the following advantages. First, referring to FIG. 2E, the RPO layer 60 on the surface of the side wall 54 can be used as a cover for the second ion implantation process 63. Therefore, the second heavily doped region 64 and the adjacent ^ sidewalls 54 maintain a lateral distance L !, which can increase the lateral distance of the gate structure 50h two times: twice the lateral distance of the heavily doped region 64. It can effectively improve the increase of the penetration voltage (punch thrugh voltage) and the bulk-drain voltage (Vbd) of the high-voltage components. Second, in the present invention, the first of the low-voltage component regions 42L is performed first. The heavily doped region 58 and the second heavily doped region 64 of the high-voltage element region 42 进 can avoid the disadvantages of performing the heavy ion doping process of the high-voltage element and the low-voltage element at the same time. Although the present invention has been better implemented The example is disclosed as above, but it is not = the person skilled in the art is familiar with this art, without departing from the scope of the present :: when you can make a few changes and retouching, so the present invention :: The patent attached to Qianwei Dangshi The range is defined. °

1224367 Brief Description of Drawings Figures 1A to 1E show schematic cross-sectional views of the conventional integration process of low-voltage components and high-voltage components. Figures 2A to 2E are schematic cross-sectional views showing a process of integrating a low-voltage component and a high-voltage component according to the present invention. Explanation of symbols: semiconductor silicon substrate ~ 10; high-voltage element region ~ 12H; low-voltage element region ~ 12L; field oxidation isolation region ~ 14;

Silicon nitride insulation layer ~ 16; photoresist layer ~ 18; lightly doped region ~ 20; gradient diffusion region ~ 20a; gate structure ~ 26H, 26L; LDD structure ~ 28; side wall ~ 30 Heavyly doped region ~ 32H; source / drain diffusion region ~ 32L.

Semiconductor silicon substrate ~ 40; low voltage element area ~ 4 2 L; high voltage element area ~ 42H; field oxidation isolation area ~ 44; gate insulating layer ~ 4 6;

0516-9425TWF (nl); 91011; cherry.ptd Page 13 1224367 The diagram briefly illustrates the gate conductive layer ~ 4 8; gate structure ~ 50L, 50H; lightly doped region ~ 52; side wall ~ 5 4; A photoresist layer ~ 56; first heavily doped region ~ 58; photoresist protective oxide layer ~ 60; second photoresist layer ~ 62; second heavily doped region ~ 64;

Automatic alignment of metal silicide layer ~ 6 6.

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Claims (1)

1224367 Case No. 92106485 6. Scope of patent application 1. A semiconductor silicon substrate and a gate structure can be added, which is a lightly doped region inside the silicon substrate; a side wall is heavily doped therein, and a lateral pitch is included. 2. Rushen ’s high-voltage components are of the same conductivity type 3. Rushen ’s high-voltage components are conductively layered 4. Rushen ’s high-voltage components are in the element area area and 5. Rushen ’s high-voltage components are the gate structure 6. A pair of Making formulas, system-shaped hetero-regions ^ The heavy doping is patented, and the dopants of this formula are patented, where the structure. Patent patents, including this, and including the high-voltage element patent patents, and more, the lightly doped high-voltage components that can increase the penetration method, including the penetration voltage of high-voltage components, including:, a high-voltage component area is defined on the surface; formed in the In the area of the south pressure element, the semiconductor formed on the side of the gate structure is formed on the side wall of the gate structure; and is formed on the side of the side wall of the gate structure; a region is maintained between the area and the adjacent side wall A lightly doped region with increased penetration voltage as described in item 1 and a heavily doped region with an increased penetration voltage as described in item 1 is provided with a gate insulating layer and One of the gates described in item 1 above can increase the penetration voltage, and a low-oxide isolation region is defined on the surface of the semiconductor silicon substrate to isolate the low-voltage component region. The one described in item 1 above can increase the penetration voltage. An auto-aligned metal oxide compound is formed on the surface of the impurity region and the heavily doped region. The manufacturing process of high-voltage components and low-voltage components that pass voltage is as follows: 0516-9425TWFl (nl); 91011; cherry.ptc Page 15 1224367 Case No. 92106485 Amendment VI. The scope of the patent application provides a half-domain and a high-voltage component area where the gate is formed in the side area of the shape entry area; In the side field of the south pressure-shaped entrance field, a silicon structure with a polarized structure is distinguished from the side of the gate structure, and the side of the gate structure is formed into a row and a photoresistor. The low-voltage element region is defined on the surface. The low-voltage element region and the gate structure, and a lightly doped region are formed in the semiconductor silicon substrate and on a sidewall sub-shaped wall; a layer covers the high-voltage element region; a hybrid ion implantation process, In order to form a first heavily doped region in the lightly doped region of the low-voltage element region, the first photoresist layer is divided into a light element region into a first row and a first sub-mirror region, which holds a lateral gap 7. Steps for applying high-voltage components and rows: performing a high removal, removing the light, and performing a self-resistance protective oxide layer covering the entire surface of the low-voltage component area and the domain Two photoresist layers cover the low-voltage element area; and a double-doped ion implantation process to form a second heavily doped second heavily doped side of the photoresist protection oxide layer on the high-voltage element area. The distance between the area and the adjacent side wall. A manufacturing method that can increase the penetration voltage of the low-voltage component manufacturing process described in item 6 of the patent scope, further includes a low temperature driving process; two photoresist layers; a resist protective oxide layer; and a dynamic alignment silicidation process for the Gate structure, lightly doped 0516-9425TWFl (nl); 91011; cherry.ptc Page 16 1224367 Case No. 92106485 _η Amendment 6. Scope of patent application An auto-aligned metal petrochemical is formed on the impurity region and the exposed surface of the heavily doped region. 8. A method for manufacturing a high-voltage device capable of increasing the penetration voltage and a low-voltage device as described in item 6 of the scope of the patent application, wherein the surface of the semiconductor silicon substrate includes an oxidized isolation region to separate the low-voltage device. Area and the south pressure element area. 9. A manufacturing method for matching the manufacturing process of a high-voltage component and a low-voltage component as described in item 6 of the scope of the patent application, wherein the gate structure is composed of a gate insulating layer and a gate conductive layer . 10. The manufacturing method of matching the process of the high-voltage component and the low-voltage component capable of increasing the penetration voltage according to item 6 of the scope of the patent application, wherein the lightly doped region and the heavily doped region have the same conductivity type. quality. 0516-9425TWFl (nl); 91011; cherry.ptc Page 17 1224367 Case No. 092106485 May 18, 1993 Amendment 12L 12H ^ 20a Figure 1C 12H 12L ——A-- t-Λ- 26Η 26L 24 24 Figure 1D 1224367 42H 60 42L people 42L 42H _ __A_ Figure 2D