JPS60173875A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the difference in pattern conversion by a method wherein a semiconductor layer formed on an insulation substrate is selectively removed by etching by using an oxidation resistant film as a mask, thus forming a semiconductor layer pattern; then, only its side wall is provided with a conductive material film, and next oxidizing treatment is carried out after removal of the oxidation resistant film pattern. CONSTITUTION:After an Si layer and the first SiO2 film are formed on a sapphire 21, an SiO2 film pattern 23 and an Si layer pattern 24 are formed by selectively removing this film and this layer by using an Si nitride film 22 as a mask. Next, the second SiO2 film 25 is formed on the side surface of the Si layer pattern 24 by thermal oxidizing treatment. Then, a polycrystalline Si film 26 doped with an impurity at a high concentration is formed over the surface including the nitride film 22. A polycrystalline Si film 27 is left only on the side walls of the nitride film 22, SiO2 film pattern 23, and Si layer pattern 24 by etching the Si film 26 by RIE. Finally, thermal oxidizing treatment is carried out after removal of the nitride film 22 and the SiO2 film pattern 23.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which elements are formed in a semiconductor layer on an insulating substrate.

[Technical background of the invention and its highlights]

As is well known, SOS (Silicon OnSapp) is a silicon layer formed on a sapphire blue insulating substrate.
MO8 type transistors with the following structure are known.

Conventionally, such an L transistor has a silicon layer 2 on a sapphire 1 as shown in FIG. After that, a field exposure film 3 is formed by the so-called coplanar method, and the heights of the oxide film 3 and the island-shaped silicon layer 2 separated by this oxide 1193 are made equal, and the r-to electrode 4 is further insulated by dirt. membrane 5
Then, using the dirt' electrode 4 as a mask, the silicon If! It is manufactured by ion-implanting impurities into 2 to form source and drain regions (not shown in the drawings).

However, according to this manufacturing method, when forming the field branching film 3, a horse's mouth-shaped region, so-called bird's beave, is formed at the edge portion (dotted line portion) 6 of the island-shaped silicon layer 2, which is not designed. A conversion difference occurs between the channel length and the actual channel length. In addition, since a thick field fermentation film 3 is formed on the island-shaped silicon layer 2, many [1
When operated in an environment exposed to radiation as shown in Fig. 1, a large amount of traps are generated in the field hostile film 3, which changes the threshold voltage of the MOS run mask. After forming an island-shaped silicon layer 2 on the sapphire 1, the entire surface is exposed to form a dirt insulating film 7 on the surface of the silicon layer 2, and a dirt electrode 8, source and drain regions (respectively) are formed. A typical method for manufacturing an MO8 type transistor is known. According to this method, as compared with the case of the transistor shown in FIG. 1 described above, almost no difference in conversion occurs, and the transistor has excellent environmental resistance. However, when the dirt insulating film 7 is formed, the thickness of the dirt insulating film 7 on the side surface of the island-shaped silicon layer 2 near the sapphire 1 is thinner than that on other parts, so there is a problem that the dirt breakdown voltage decreases. will occur. Furthermore, when a voltage is applied to the dirt electrode 8, the edge portion 1 of the island-shaped silicon layer 2
At zero, electric field concentration occurs and the threshold voltage decreases, a phenomenon called the so-called reverse narrow channel effect.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce the turn conversion difference, improve the dirt breakdown voltage, and increase the threshold voltage. It is.

[Summary of the invention]

The present invention involves a process of selectively etching and removing a semiconductor layer (silicon layer) formed on an insulating substrate (for example, sapphire) using an oxidation-resistant film as a mask to form a semiconductor layer pattern, and a process for forming a semiconductor layer pattern. a step of forming an insulating film on the substrate, a step of forming a conductive material film, such as a polycrystalline silicon film draped with impurities at a high concentration, on the entire surface of the substrate including the oxidation-resistant film, and an anisotropic treatment of the ultrasonic material. a step of etching the conductive material film to leave it only on the sidewalls of the semiconductor layer pattern and the oxidation-resistant film; and after removing the oxidation-resistant film pattern, oxidation treatment is performed on the surface of the remaining conductive material film. The method is characterized by comprising a step of insulating the material, thereby achieving the above-mentioned object.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to FIGS. 3(a) to 3(f) and FIG. 54 regarding the case where the present invention is applied to the manufacture of an MO8 type transformer (mask) having an SO8 structure.

[1] First, a silicon layer (semiconductor layer), a first
After forming the 8102 film, the SiO2 film and the silicon layer are selectively removed by reactive ion etching (R process E) using the silicon nitride film 22 as an oxidation-resistant film as a mask, and the S i 0211Q Ha9- A turn 23 and a silicon layer (turn 24) were formed (as shown in FIG. 3(a)).The 5io2 film pattern 23 serves to prevent distortion during thermal oxidation in the next step. A thermal oxidation treatment is applied to the side surface of the silicon layer pattern 24 to a thickness of 100 mm.
A second 8i02 film 25 of ~500X was formed (
FIG. 3(b) (illustrated). Next, a polycrystalline silicon film (rod material film) 26 doped with n-type impurities such as phosphorus or arsenic at a high concentration was formed on the entire surface including the silicon nitride film 22 (as shown in FIG. 3(C)).

(2) Next, the polycrystalline silicon film 26 was removed by etching using RI RV, leaving the polycrystalline silicon film 27 only on the side walls of the silicon nitride IF+ 22.5ho2 film pattern 23 and the silicon layer pattern 24 (see Fig. 3). (
d) As shown). Next, after etching and removing the silicon nitride film 22 using hot phosphoric acid,
Turn 23 was removed by etching. At this time, the remaining polycrystalline silicon film 27 was also etched to some extent (Fig. 3 (
e) As shown). Next, a dirt insulating film 28 is formed on the exposed silicon layer 24 by thermal oxidation treatment, and at the same time,
An oxide film 29 was also formed on the surface of the remaining polycrystalline silicon film 27. Thereafter, a dirt electrode 30 made of, for example, polycrystalline silicon or silicide such as MOS + 2 was formed on the dirt insulating film 28 .

Furthermore, using the dirt F4F pole 30 as a mask, an n-type impurity such as phosphorus is ion-implanted into the silicon layer pattern 24 under predetermined conditions to form an N-type source and drain region 3.
1, ,? 2 was formed to manufacture an MO8 type transistor (as shown in FIGS. 3(f) and 4). Here, the fourth
The figure is a plan view of FIG. 3(f).

According to the present invention, the silicon layer pattern 24 is formed on the sapphire 21 using the silicon nitride film 22 as a mask.
After forming the 5i02 film pattern 23 and leaving the polycrystalline silicon layer 27 only on these side walls, the silicon nitride film 22, slo, and film pattern 23 are removed, and then heat treatment is performed to form the dirt insulating film 28. , oxide film 2
Since the structure is 9"y, it is possible to fabricate submicron devices without causing P-turn displacement as in the case of the transistor shown in FIG.

Further, when forming the gate insulating film 28, the side wall of the silicon 1m pattern 24 is surrounded by the remaining polycrystalline silicon y*¥1-22 via the second 5in2 film 25,
Moreover, since the oxidation rate of this polycrystalline silicon layer 27 is higher than that of the silicon layer pattern 24, the sapphire 1
Uniform oxide film 29 up to the polycrystalline silicon layer 27
is formed. Therefore, the initial breakdown voltage is improved compared to the transistor shown in FIG.

Furthermore, a second 8i02 in contact with the silicon layer pattern 24
Since the thickness of the film 25 can be reduced by more than an order of magnitude (100 to 500X) compared to the case of the transistor using the coplanar method shown in FIG. 1, there is no influence of radiation such as γ-rays, and a decrease in the threshold voltage can be prevented. . Further, a polycrystalline silicon R odor 2 which is a conductive material film is provided between the silicon layer pattern 24 and the oxide film 29.
7 is sandwiched between them, the electric field generated when a voltage is applied to the dart electrode 30 is shielded by the polycrystalline silicon layer 27 and does not reach the sides of the silicon layer pattern 24.
．． Therefore, it is possible to prevent the threshold voltage from decreasing.

In the above embodiment, a polycrystalline silicon film heavily doped with an n-type impurity such as phosphorus or arsenic was used as the conductive material film, but the present invention is not limited to this. In addition, this polycrystalline silicon vein was doped with the n-type impurity at a high concentration in advance, but after the step shown in FIG. You can make it a dawg.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to provide a method for manufacturing a highly reliable semiconductor device that can improve gate breakdown voltage, reduce pattern exchange difference, and improve threshold voltage. .

[Brief explanation of drawings]

FIGS. 1 and 2 are cross-sectional views of conventional MO8 transistors with an SO8 structure, and FIGS. 3(a) to (fj) show a method for manufacturing an MO8 transistor with an SOS structure according to an embodiment of the present invention. Cross-sectional views shown in the order of steps, Figure 4 is a plan view of Figure 3 (dog). 21°°° Sapphire (insulating substrate), 22... silicon nitride film (oxidation resistant film), 23... 5in2 film Pattern, 24...Silicon layer nog turn, 25...5IO
2 film, 26. 27... Polycrystalline silicon film (conductive material film), 28... Dirt insulating film, 29... Oxide film, 3
0: gate electrode, 3: N-type source region,
32...N type drain region.

Claims (2)

[Claims] (1) The process of selectively etching and removing the semiconductor layer formed on the insulating substrate 2 using the oxidation resistance pattern 1 as a mask to form semiconductor 1yQ/9 turns, and the process of forming the semi-conductor layer and turns. A step of forming an insulating film on the side surface, a step of forming a conductive material pattern 1 on the entire surface of the substrate including the oxidation-resistant film, and anisotropic etching of this conductive material film to form a semiconductor layer pattern and an antioxidation layer pattern. The surface of the remaining conductive material film is insulated by performing an oxidation treatment after removing the oxidation resistance 1 [So 1], and insulating the surface of the remaining conductive material film. 1. A method for manufacturing a semiconductor device, comprising the steps of: (2)! 2. The method of manufacturing a semiconductor device according to claim 1, wherein a polycrystalline silicon film doped with impurities at a high concentration is used as the electrostatic material film.