CN1271702C - High-voltage component capable of increasing breakthrough voltage and its manufacturing method matched with low-voltage component process - Google Patents

Abstract

A high voltage component capable of increasing penetration voltage and a manufacturing method thereof matched with a low voltage component process are provided. A semiconductor silicon substrate has a high voltage device region defined on its surface. A gate structure formed in the high voltage device region. A lightly doped region formed in the semiconductor silicon substrate at the side of the gate structure. A spacer formed on the sidewall of the gate structure. And a heavily doped source/drain region formed in the lightly doped region at the side of the spacer, wherein a lateral distance is maintained between the heavily doped source/drain region and the adjacent spacer.

Description

High-voltage component capable of increasing breakthrough voltage and its manufacturing method matched with low-voltage component process

technical field

The present invention relates to an integrated process of low-voltage components and high-voltage components, in particular to a high-voltage component applied to the design of reduced line width and a manufacturing method matching the process of the low-voltage component, which can increase the penetration voltage (punch) of the high-voltage component through voltage) and body-drain voltage (bulk-drainvoltage, V _BD ).

Background technique

In today's semiconductor technology, in order to achieve the operation of a single-chip system, the controller, memory, low-voltage operating circuits, and high-voltage operating power components are highly integrated on a single chip, and the research and development types of power components include There are several types of vertical power metal oxide semiconductor transistors (VDMOS), insulated gate bipolar transistors (IGBT), and lateral power transistors (LDMOS). The purpose of their research and development is to improve power conversion efficiency and reduce energy loss. Since high-voltage components and low-voltage components with different breakdown voltage requirements need to be provided on a single chip at the same time, how to integrate semiconductor processes so that the high-voltage component process can match the low-voltage component process has become an important issue at present.

In the traditional high-voltage device process, the polysilicon gate on the silicon substrate is used as a mask to form a self-aligned source/drain region in the silicon substrate, which serves as a doublediffused drain (DDD) structure. Generally speaking, in order to suppress the thermal electron effect and increase the breakdown voltage of the source/drain region, a lightly doped drain (LDD) structure is first formed under the source/drain region of the silicon substrate, Then the DDD structure is completed by a high temperature driving process. However, in the process integration of high-voltage components and low-voltage components, because the structure and thermal budget of the two are different, the low-voltage component area will be affected during the high-temperature driving process of the LDD structure in the high-voltage component area to form the DDD structure. The diffusion area cannot ensure the stability of its electrical quality.

US Patent No. 6,509,243 proposes an integration process of a low-voltage component and a high-voltage component, which will be described in detail below with reference to FIGS. 1A to 1E . As shown in FIG. 1A , a high-voltage component region 12H and a low-voltage component region 12L are defined on the surface of a semiconductor silicon substrate 10 . Firstly, a silicon nitride insulating layer 16 is deposited on the surface of the semiconductor silicon substrate 10, and then the pattern of the silicon nitride insulating layer 16 is defined in the range of the high-voltage device region 12H and the low-voltage device region 12L to expose a predetermined isolation region. Then, an oxidation process is performed to grow an oxide layer on the exposed predetermined isolation region of the semiconductor silicon substrate 10 as a field oxidation isolation region 14 , which can isolate the high-voltage device region 12H and the low-voltage device region 12L. Then, as shown in FIG. 1B , a photoresist layer 18 is covered on the surface of the semiconductor silicon substrate 10 to expose only the predetermined source/drain region of the high voltage device region 12H. Then, an ion implantation process is performed to form a lightly doped region 20 on the surface of the semiconductor silicon substrate 10 in the exposed region of the high voltage device region 12H. Next, as shown in FIG. 1C , after removing the photoresist layer 18 and the silicon nitride insulating layer 16 in sequence, a high-temperature driving process is performed to promote the lightly doped region 20 to diffuse downward into the semiconductor silicon substrate 10 and laterally Diffused to below the field oxide isolation region 14 to form a gradient diffusion region 20a.

Then, as shown in FIG. 1D, a gate structure 26H of a high-voltage device and a gate structure 26L of a low-voltage device are respectively formed in the high-voltage device region 12H and the low-voltage device region 12L, wherein each gate structure 26H, 26L is composed of a The gate oxide layer 22 and a polysilicon gate layer 24 are formed, and the gradient diffusion region 20 a is located in the semiconductor silicon substrate 10 around the gate structure 26H. Next, as shown in FIG. 1E , after masking the high-voltage component region 12H with a photoresist, a lightly doped ion implantation process is performed using the gate structure 26L as a mask, so as to implant the semiconductor silicon substrate 10 in the low-voltage component region 12L. An LDD structure 28 is formed. Subsequently, after removing the photoresist mask of the high-voltage device region 12H, sidewalls 30 are formed on the sidewalls of the gate structures 26H and 26L respectively, and then the gate structures 26H, 26L and the sidewalls 30 are used as masks to Performing a heavily doped ion implantation process can form a heavily doped region 32H in the gradient diffusion region 20a of the high-voltage device region 12L, and simultaneously form a source/drain diffusion region 32L in the LDD structure 28 of the low-voltage device region 12L. In this way, in the high voltage device region 12H, the combination of the gradient diffusion region 20 a and the heavily doped region 32H constitutes a DDD structure.

However, under the design of narrowing the line width of the high-voltage component, the above-mentioned technology performs the heavily doped ion implantation process on the high-voltage component region 12H and the low-voltage component region 12L at the same time, and it is difficult to control the bulk-drain voltage of the high-voltage component. V _BD ). Moreover, as the channel length becomes shorter, if the high-voltage device process cannot be improved to increase the effective distance between the source and the drain, the problem of electron punch through will also be encountered.

Contents of the invention

In view of this, the object of the present invention is to provide a manufacturing method for high-voltage components and its matching process with low-voltage components, which can be used in different steps to perform heavily doped ion implantation of high-voltage components and low-voltage components. process, and can increase the effective distance of the source/drain of the high-voltage component to lengthen the effective channel distance, thereby increasing the punch through voltage (punch through voltage) and the body-drain voltage (bulk-drain voltage, V _BD ) of the high-voltage component .

To achieve the above object, the present invention provides a high-voltage component capable of increasing the breakthrough voltage and a manufacturing method thereof that matches the process of the low-voltage component. A semiconductor silicon base defines a high-voltage component area on its surface. A gate structure is formed in the high voltage device area. A lightly doped region is formed in the semiconductor silicon substrate at the side of the gate structure. A pair of sidewalls are formed on the sidewalls of the gate structure. A heavily doped source/drain region is formed in the lightly doped region on the sides of the pair of sidewalls, and a lateral distance is maintained between the heavily doped source/drain region and adjacent sidewalls.

Wherein, the lightly doped region and the heavily doped source/drain region have dopants of the same conductivity type, and the gate structure is composed of a gate insulating layer and a gate conducting layer. A low-voltage device area is further defined on the surface of the semiconductor silicon base, and includes an oxidation isolation area for separating the low-voltage device area and the high-voltage device area. A self-aligned metal silicide is formed on the surface of the gate structure, the lightly doped region and the heavily doped source/drain region.

In order to achieve the above-mentioned purpose, the present invention provides a method for manufacturing a high-voltage component and a low-voltage component that can increase the breakthrough voltage and process matching, comprising the following steps: providing a semiconductor silicon substrate, defining a low-voltage component region and a high-voltage component region on its surface , wherein a gate structure is fabricated in the low-voltage device region and the high-voltage device region, a lightly doped region is formed in the semiconductor silicon substrate on the side of the gate structure, and a sidewall is formed in the gate structure On the sidewall; form a first photoresist layer to cover the high-voltage component region; perform a first heavily doped ion implantation process to form in the lightly doped region on the sidewall sub-side of the low-voltage component region a first heavily doped source/drain region; removing the first photoresist layer; forming a photoresist protective oxide layer covering the entire surface of the low voltage component region and the high voltage component region; forming a second photoresist an adhesive layer covering the low-voltage device region; and performing a second heavily doped ion implantation process to form in the lightly doped region on the side of the photoresist-protected oxide layer on the sidewall subsurface of the high-voltage device region A second heavily doped source/drain region, wherein a lateral distance is maintained between the second heavily doped source/drain region and the adjacent sidewalls. removing the second photoresist layer; removing the photoresist protection oxide layer; and performing a self-aligned silicidation process for the gate structure, the lightly doped region, and the heavily doped source/drain region A self-aligned metal silicide is formed on the exposed surface.

Description of drawings

1A to FIG. 1E are cross-sectional schematic diagrams showing the integration process of conventional low-voltage components and high-voltage components.

2A to 2E are schematic cross-sectional views showing the integration process of the low-voltage component and the high-voltage component of the present invention.

Description of figure number

Semiconductor Silicon Substrate 10 High Voltage Component Area 12H

Low-voltage component area 12L Field oxidation isolation area 14

Silicon nitride insulating layer 16 photoresist layer 18

Lightly doped region 20 Gradient diffusion region 20a

Gate structure 26H, 26L LDD structure 28

Sidewall Sub 30 Heavily Doped Source/Drain Region 32H

Source/Drain Diffusion Area 32L

Semiconductor Silicon Substrate 40 Low Voltage Component Area 42L

High voltage component area 42H Field oxidation isolation area 44

Gate insulation layer 46 Gate conductive layer 48

Gate Structure 50L, 50H Lightly Doped Region 52

Sidewalls 54 The first photoresist layer 56

First heavily doped source/drain region 58 Photoresist protection oxide layer 60

Second Photoresist Layer 62 Second Heavily Doped Source/Drain Region 64

Self-aligned metal silicide layer 66

Detailed ways

Please refer to FIG. 2A to FIG. 2E , which are schematic cross-sectional views of the integration process of the low-voltage component and the high-voltage component of the present invention.

First, as shown in FIG. 2A , a semiconductor silicon substrate 40 is provided, a low-voltage device region 42L and a high-voltage device region 42H are defined on its surface, and a field oxidation isolation region 44 is used to separate the high-voltage device region 42H from the low-voltage device region. 42L. Moreover, on the surface of the semiconductor silicon substrate 40 in the low-voltage component region 42L and the high-voltage component region 42H, a gate structure 50L of a low-voltage component and a gate structure 50H of a high-voltage component are fabricated respectively, and the semiconductors around the gate structures 50L and 50H A lightly doped region 52 , such as an N ⁻ ion doped region, is respectively formed in the silicon substrate 40 . Wherein, each gate structure 50L, 50H is composed of a gate insulating layer 46 and a gate conductive layer 48 , and sidewalls 54 are formed on the sidewalls of the gate structures 50L, 50H. The present invention does not limit the fabrication method, sequence and material of the field oxidation isolation region 44 , the lightly doped region 52 , the gate structures 50L, 50H and the sidewalls 54 .

Then, as shown in FIG. 2B , a first photoresist layer 56 is provided on the surface of the semiconductor silicon substrate 40 to cover the high-voltage device region 42H and expose the low-voltage device region 42L. Subsequently, a first heavily doped ion implantation process 57 is performed, for example: N ⁺ ion doping process, using the gate structure 50L of the low-voltage device and the sidewalls 54 as a mask, the exposed portion of the lightly doped region 52 can be A first heavily doped source/drain region 58 is formed in a portion of the region, for example, an N ⁺ ion doped region. Thus, in the low-voltage device region 42L, the first heavily doped source/drain region 58 functions as a source/drain region, and the lightly doped region 52 functions as an LDD structure.

Next, as shown in FIG. 2C , after the first photoresist layer 56 is removed, a photoresist protection oxide (RPO) layer 60 is deposited on the surface of the semiconductor silicon substrate 40 to cover the low-voltage device area. 42L and high voltage component area 42H. Then, as shown in FIG. 2D, a second photoresist layer 62 is first provided to cover the low-voltage component region 42L, and then a second heavy light ion implantation process 63 is performed, such as: N ⁺ ion doping process, using the high-voltage component The gate structure 50H, the sidewalls 54 and a part of the RPO layer 60 are used as a mask to form a second heavily doped source/drain region 64 in the exposed part of the lightly doped region 52, for example: N ⁺ ion doped regions. A high temperature driving process may then be performed to promote the lightly doped region 52 to diffuse downward into the semiconductor silicon substrate 40 and laterally diffuse below the field oxide isolation region 44 to form a gradient diffusion region 52 a. In this way, in the high voltage device region 42H, the combination of the gradient diffusion region 52a and the second heavily doped source/drain region 64 constitutes a DDD structure. Since the RPO layer 60 on the surface of the sidewall 54 can be used as a mask for the second heavy light ion implantation process 63, the effective distance L of the second heavily doped source/drain region 64 as the source/drain region will vary with As the thickness of the RPO layer 60 increases and becomes longer, the effective channel length can be increased, thereby improving the punch through voltage and bulk-drain voltage (V _BD ) of the high-voltage device.

Finally, as shown in FIG. 2D , after removing the second photoresist layer 62 and the RPO layer 60 in sequence, an automatic alignment silicidation process (salicidation process) can be performed on the gate conductive layer 48 and the source/drain region 52 A self-aligned silicide (salicide) layer 66 is formed on the exposed surface of , 64 to reduce the resistance value. For example, when the material of the gate conductive layer 48 is polysilicon, a metal layer can be sputtered on the surface of the semiconductor silicon substrate 40, and its thickness ranges from 300 to 800 Å, and the material can be selected from cobalt or titanium to cover the gate. The exposed surfaces of the electrode conductive layer 48 , the sidewalls 54 and the source/drain regions 52 and 64 . Then, a heat treatment process is performed on the metal layer, which can make the metal atoms in the metal layer diffuse downwards and produce silicidation reaction with the polysilicon and the silicon atoms in the silicon substrate. As a result, the exposed surface will react to form TiSi ₂ or CoSi ₂ material, and the unreacted metal layer is removed by selective etching.

Compared with the conventional technology, the technology of the present invention has the following advantages. First, please refer to FIG. 2E, the RPO layer 60 on the surface of the sidewall sub 54 can be used as a mask for the second heavy light ion implantation process 63, so that the second heavily doped source/drain region 64 and the adjacent sidewall sub 54 maintains a lateral spacing L ₁ , which can increase the lateral spacing of the two heavily doped source/drain regions 64 of the gate structure 50H to twice the L ₁ , which can effectively improve and increase the punch through voltage (punch through voltage) and body-drain voltage (bulk-drainvoltage, V _BD ). Second, in the present invention, the first heavily doped source/drain region 58 of the low-voltage component region 42L is performed first, and then the second heavily doped source/drain region 64 of the high-voltage component region 42H is performed, thereby avoiding simultaneous high-voltage component Disadvantages of the heavy ion doping process with low voltage components.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall be defined by the scope of the appended patent application.

Claims (10)

1. A high-voltage component that can increase the breakthrough voltage, including: A semiconductor silicon substrate, defining a high-voltage device region on its surface; a grid structure formed in the high-voltage component region; a lightly doped region formed in the semiconductor silicon substrate at the side of the gate structure; a pair of sidewalls formed on the sidewalls of the gate structure; and a heavily doped source/drain region formed in the lightly doped region on the sub-sides of the pair of sidewalls; Wherein, a lateral distance is maintained between the heavily doped source/drain region and adjacent sidewalls. 2 . The high-voltage device capable of increasing breakthrough voltage as claimed in claim 1 , wherein the lightly doped region and the heavily doped source/drain region have dopants of the same conductivity type. 3 . 3 . The high-voltage device capable of increasing breakthrough voltage as claimed in claim 1 , wherein the gate structure is composed of a gate insulating layer and a gate conductive layer. 4 . 4. A high-voltage component capable of increasing breakthrough voltage as claimed in claim 1, wherein a low-voltage component region is additionally defined on the surface of the semiconductor silicon substrate, and includes an oxidation isolation region for separating the low-voltage component area and the high voltage component area. 5. A high-voltage device capable of increasing breakthrough voltage as claimed in claim 1, further comprising a self-aligned metal silicide formed on the gate structure, the lightly doped region and the heavily doped source/drain on the surface of the polar region. 6. A method for manufacturing a high-voltage component capable of increasing the breakthrough voltage and a low-voltage component process matching, comprising the following steps: Provide a semiconductor silicon substrate, define a low-voltage component region and a high-voltage component region on its surface, wherein a gate structure is respectively fabricated in the low-voltage component region and the high-voltage component region, and a lightly doped region is formed on the side of the gate structure The side wall of the semiconductor silicon substrate and the side wall are formed on the side wall of the gate structure; forming a first photoresist layer covering the high-voltage component area; performing a first heavily doped ion implantation process to form a first heavily doped source/drain region in the lightly doped region at the sidewall subside of the low voltage device region; removing the first photoresist layer; forming a photoresist protective oxide layer covering the entire surface of the low-voltage component region and the high-voltage component region; forming a second photoresist layer covering the low voltage device area; and performing a second heavily doped ion implantation process to form a second heavily doped source/drain in the lightly doped region on the side of the photoresist protection oxide layer on the sidewall subsurface of the high voltage device region region, wherein a lateral distance is maintained between the second heavily doped source/drain region and the adjacent sidewalls. 7. A method for manufacturing a process-matched high-voltage component and low-voltage component that can increase the breakthrough voltage as claimed in claim 6, further comprising the following steps: removing the second photoresist layer; removing the photoresist protective oxide layer; and A self-aligned silicide process is performed to form a self-aligned metal silicide on the exposed surfaces of the gate structure, the lightly doped region, and the heavily doped source/drain region. 8. A manufacturing method capable of increasing the breakthrough voltage of high-voltage components and low-voltage components according to claim 6, wherein the surface of the semiconductor silicon substrate contains an oxide isolation region for separating the low-voltage components. component area and the high voltage component area. 9. A method for manufacturing a high-voltage component and a low-voltage component that can increase the breakthrough voltage according to claim 6, wherein the gate structure is composed of a gate insulating layer and a gate conductive layer . 10. A method for manufacturing high-voltage components and low-voltage components that can increase the breakthrough voltage according to claim 6, wherein the lightly doped region and the heavily doped source/drain region have the same Conductive dopant.

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