JPH08264766A - Field effect transistor and method of manufacturing the same - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a diffusion-type and depletion-type field-effect transistor having a higher breakdown voltage than ever before. An N ⁻ -type silicon substrate 11, a P-type diffusion region 13 formed on a part of the substrate 11, and a source formed at a depth shallower than a partial surface of the P-type diffusion region 13 Of the N ⁺ type diffusion region 15 for contact and the P type diffusion region 13;
The N ⁺ -type diffusion region 17 constituting the formed in the surface layer portion of the N ⁺ -type diffusion region 15 is the portion other than the forming portions for the source contact channel portion, formed on the N ⁺ -type diffusion region 17 In the depletion type field effect transistor including the gate insulating film 19, the P-type diffusion region 13 and the N ⁺ -type diffusion region 17 are arranged so that the lateral ends thereof are substantially coincident with each other. It is equipped with 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention, VD (V ertical D if
fusion: Vertical diffusion MOSFET (Metal Oxide Semicond)
The present invention relates to a structure of a diffusion type field effect transistor represented by uctor field effect transistor and a depletion type field effect transistor, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Diffusion type field effect transistors have been attracting attention as, for example, elements for high breakdown voltage (for example, Document I:
Electronic Technology 1989-6, pages 18-20). Such diffusion type field effect transistors are also of depletion type and enhancement type (page 29 to 31 of the above-mentioned document I), and these are properly used according to the application.

[0003]

As an example of a diffusion-type and depletion-type field effect transistor, for example, the sectional view of FIG. 9A and FIG. 9B showing the positional relationship of diffusion regions are shown. Those having the structures respectively shown in the plan views of the relevant parts of FIG. That is, the N ⁻ type silicon substrate 11 as a first conductive type semiconductor base, the P type diffusion region 13 as a second conductive type diffusion region formed in a part of the substrate 11, and the P type diffusion region. The N ⁺ type diffusion region 15 for source contact as a high-concentration first conductivity type diffusion region formed at a depth shallower than a partial surface of the region 13 and the source of the P type diffusion region 13. at least a portion of the surface layer portion of the N ⁺ -type portions other than the portion where the diffusion regions 15 are formed in the contact N ⁺ -type diffusion region 1 which constitutes the channel part is formed (total in this example)
7 and a gate insulating film 19 formed on the N ⁺ type diffusion region 17 are field effect transistors. In FIG. 9, 21 is a gate electrode, 23 is an intermediate insulating film, 25 is a wiring in this example, and 27 is a P ⁺ -type diffusion region mainly provided for reducing source contact resistance and improving withstand voltage. Shown respectively.

In the field-effect transistor described with reference to FIG. 9, when the lateral extension of the N ⁺ type diffusion region 17 forming the channel portion is smaller than that of the P type diffusion region 13, FIG. ), The P layer is included in a part of the channel portion (S in FIG. 10A).
(Refer to the portion indicated by (1)), no current flows between the source and the drain unless a voltage higher than a predetermined positive value is applied to the gate electrode 21 (that is, enhancement type V
It becomes a DMOSFET). Therefore, in order to prevent this, as shown in FIGS. 9 and 10B, the lateral extension of the N ⁺ type diffusion region 17 forming the channel portion is larger than that of the P type diffusion region 13 as compared with that of the P type diffusion region 13. I am trying to grow. Generally, in terms of mask rules,
The lateral end of the N-type diffusion region 17 forming the channel portion is projected by about 2 μm from the lateral end of the P-type diffusion region 13.

However, according to the research conducted by the inventor of the present application, when the lateral extension of the N ⁺ type diffusion region 17 forming the channel portion is larger than that of the P type diffusion region 13, it is found that It was found that it is not preferable in terms of improving the breakdown voltage of the diffusion type and depletion type field effect transistor (see FIG. 2 below). The reason is that if the lateral extension of the N ⁺ -type diffusion region 17 becomes larger than that of the P-type diffusion region 13 than necessary, FIG.
As can be understood from FIG. 11 in which the Q portion of (B) is enlarged, a considerable portion around the end portion 13x of the P-type diffusion region 13 becomes the high-concentration N-type diffusion region 17, so that the gate is formed. When a negative potential equal to or higher than the threshold value is applied to the electrode 21 (see FIG. 10) and a positive potential is applied to the drain (N ⁻ type silicon substrate 11), electric field concentration occurs at the end portion 13x of the P type diffusion region 13. it is conceivable that.

[0006]

According to the first invention of this application, therefore, a first conductive type semiconductor base, a second conductive type diffusion region formed in a part of the base, and a second conductive type diffusion region A high-concentration first-conductivity-type diffusion region formed at a depth shallower than a part of the surface of the second-conductivity-type diffusion region, and the high-concentration first conductivity of the second-conductivity-type diffusion region. A diffusion region of a first conductivity type which is formed on at least a part of a surface layer part other than a part where a diffusion region of
A depletion-type field effect transistor comprising: a gate insulating film formed on the diffusion region of the first conductivity type, wherein the diffusion region of the second conductivity type and the diffusion of the first conductivity type forming a channel portion are provided. It is characterized in that these diffusion regions are provided so that the lateral ends of the regions are substantially in agreement with each other.

According to the second invention of this application, in manufacturing the depletion type field effect transistor of the first invention, the second conductivity type diffusion region of the first conductivity type semiconductor base is formed on the base. And a step of forming a diffusion mask having an opening for exposing a portion corresponding to a region to be formed, and a diffusion region of the second conductivity type is formed on the semiconductor substrate of the first conductivity type on which the diffusion mask is formed. A step of introducing impurities for the purpose of, and a step of etching the diffusion mask after the step of introducing the impurities so that the opening size of the opening of the diffusion mask expands by a predetermined dimension, and the diffusion after the etching process. And a step of introducing an impurity for forming a diffusion region of the first conductivity type forming a channel portion into the semiconductor underlayer having the mask.

[0008]

According to the field effect transistor of the first invention of this application, the lateral ends of the diffusion regions of the second conductivity type and the diffusion regions of the first conductivity type forming the channel portion are substantially in agreement. Since we have these diffusion regions,
The extent to which the periphery of the end portion of the second-conductivity-type diffusion region becomes the high-concentration first-conductivity-type diffusion region is reduced as compared with the related art.

According to the method of manufacturing a field effect transistor of the second invention of this application, the diffusion of the diffusion mask itself used when forming the diffusion region of the second conductivity type is enlarged by a predetermined dimension by etching. The mask is used as a diffusion mask when forming the diffusion region of the first conductivity type that forms the channel portion. Therefore, the first conductivity type diffusion region forming the channel portion can be formed in a predetermined size relationship with the second conductivity type diffusion region in a self-aligned manner.

[0010]

Embodiments of the field effect transistor and the manufacturing method thereof according to the present application will be described below with reference to the drawings. However, the drawings used for the explanation are only shown schematically so that these inventions can be understood. Further, in each drawing, the same constituent components are denoted by the same reference numerals, and the duplicated description thereof may be omitted.

1. Description of structure 1-1. First Embodiment of Structure FIG. 1 (A) is a sectional view for explaining the structure of a field effect transistor of the first embodiment, and FIG. 1 (B) is a diffusion region 13, 15 in FIG. 1 (A). , 17, and 27 are plan views of relevant parts focusing on these diffusion regions so that the positional relationship between them can be understood.

The field effect transistor according to the first embodiment has an N ⁻ type silicon substrate 11, a P type diffusion region 13 formed in a part of the substrate 11, and a P type diffusion region 13.
The N ⁺ -type diffusion region 15 for source contacts formed at a shallow depth from the region 13 from the portion of the surface of the P-type diffusion region 13, N ⁺ -type diffusion region 15 for the source contact is formed The N ⁺ -type diffusion region 17 which is formed on at least a part of the surface layer portion other than the above-mentioned portion (all in the first embodiment) and constitutes the channel portion, and the N ⁺ -type diffusion region 17 which is formed on the N ⁺ -type diffusion region 17 And a gate insulating film 19.
Further, in the field-effect transistor of this embodiment, the P-type diffusion region 13 is formed into the first P-type diffusion region 13a and the first P-type diffusion region 13a.
The second P-type diffusion region 13b is formed in the surface layer portion of the P-type diffusion region 13a and has a deeper depth than the N ⁺ type diffusion region 17 forming the channel portion. And
Lateral termination of the P-type diffusion region 13 In this case, the lateral termination of the second P-type diffusion region 13b of the P-type diffusion region 13 and the lateral direction of the N ⁺ -type diffusion region 17 forming the channel portion. The diffusion regions 13b and 17 are provided on the substrate 11 so that the ends of the diffusion regions 13b and 17 substantially coincide with each other. In FIG. 1, 21 is a gate electrode, 23 is an intermediate insulating film, 25 is a wiring, in this case, a source electrode, and 27 is a P ⁺ -type diffusion region mainly provided for reducing source contact resistance and improving withstand voltage. Shown respectively.

Next, in the field effect transistor of the first embodiment, the lateral end of the second P-type diffusion region 13b and the lateral end of the N ⁺ -type diffusion region 17 forming the channel portion are formed. A description will be given of how much the range of substantially matching should be set. Therefore, N constituting the channel portion is formed with respect to the lateral end of the second P-type diffusion region 13b.
The overhanging dimension of the lateral ends of the ⁺ type diffusion region 17 was gradually changed from a state in which both ends are coincident to about 4 μm (specifically, the overhanging dimension is 0, 0.5, 0.8,
A plurality of field effect transistors for experiments are manufactured in the same manner except that they are different from each other (1, 2, 3, 4 μm), and the breakdown voltage of each is measured. In the experiment, as the N ⁻ type silicon substrate 11, one having an N type impurity concentration of 3.0 × 10 ¹⁵ ions / cm ³ or less, here 2 × 10 ¹⁴ ions / cm ³ is used. The breakdown voltage is measured by varying the applied voltage with the gate electrode 21 (see FIG. 10) being applied with a negative potential and the drain (N ⁻ type silicon substrate 11) being applied with a positive potential.

FIG. 2 shows the above-mentioned overhanging dimension on the horizontal axis.
FIG. 7 is a characteristic diagram showing the relationship between the two with the breakdown voltage taken on the vertical axis. As can be understood from FIG. 2, N ⁺ which constitutes a channel portion with respect to the lateral end of the second P type diffusion region 13b.
The overhanging dimension of the lateral end of the mold diffusion region 17 is 1 μm.
It can be seen that the effect of improving the breakdown voltage becomes remarkable when the content is within the range. On the other hand, in the case where the lateral end of the second P-type diffusion region 13b extends beyond the lateral end of the N ⁺ -type diffusion region 17 forming the channel portion, as described above with reference to FIG. In addition, there is a high risk that the device itself operates as an enhancement type field effect transistor.
From these points, in the case of this embodiment, N which constitutes the channel portion with respect to the lateral end of the second P-type diffusion region 13b.
The second region is formed so that the range from the state in which the lateral ends of the ⁺ type diffusion regions 17 are aligned to the state in which they are overhanging by 1 μm is
It can be seen that the P-type diffusion region 13b and the N ⁺ -type diffusion region 17 are preferably provided in the substrate 11.

The reason why the P-type diffusion region 13 is composed of two regions, the first P-type diffusion region 13a and the second P-type diffusion region 13b, is as follows. If it is attempted to form the P-type region 13 having a deep diffusion depth at one time, the concentration profile of the surface layer portion, particularly at the terminal end, tends to become unclear, so that the N ⁺ -type diffusion region 17 and the P-type region 13 forming the channel portion are formed. It becomes impossible to clarify the relationship. On the other hand, as in this embodiment, the P-type diffusion region 13 is formed in the first and second regions.
The second P-type diffusion regions 13a and 13b are preferable because the concentration profile in the surface layer portion of the P-type diffusion regions 13 can be made clear by the second P-type diffusion regions 13b.

In the field effect transistor of the first embodiment, no voltage is applied to the gate electrode 21, a positive voltage is applied, or a negative voltage higher than the threshold value is applied, and N as a drain is used. ^- when subjected to a positive voltage to the silicon substrate 11, as shown in FIG. 3 (a), N ^- silicon substrate 21, N ⁺ -type diffusion region 17 constituting the channel unit,
The current I flows through the path formed by the N ⁺ type diffusion region 15 and the source electrode 25. On the other hand, when a negative voltage equal to or higher than the threshold value is applied to the gate electrode 21, the N ⁺ type diffusion region existing under the gate electrode 21 is inverted as shown in FIG. Since it becomes a region, no current flows from the drain to the source.

1-2. Second Embodiment of Structure Although an example in which the drain region exists in the lower portion of the N ⁻ type silicon substrate 11 has been described in the above-mentioned first example, the drain region is formed from the channel portion of the N ⁻ type silicon substrate 11. The first invention can also be applied to a field effect transistor existing on a surface portion slightly apart. FIG. 4 is a sectional view showing an example of the structure. An example is shown in which the drain region 31 is provided on the surface portion of the N ⁻ type silicon substrate 11 slightly apart from the channel portion, and the drain electrode 33 is provided on the drain region 31. Although the plan view is omitted, the drain region 31 in this case is provided on the substrate 11 so as to surround the P-type diffusion region 13.

1-3. Third Embodiment of Structure In the above-described first embodiment, a channel portion is formed in the entire surface layer portion of the P-type diffusion region 13 other than the portion where the N ⁺ -type diffusion region 15 for the source contact is formed. Although the example including the N ⁺ type diffusion region 17 constituting the above has been described, the first invention can be applied to the structure including the N ⁺ type diffusion region 17 constituting the channel portion in a part of the surface layer portion. . FIG. 5 is a plan view and a sectional view used for the explanation. In particular, the plan view is a diagram of the main part focusing on the positional relationship of the diffusion regions. In the third embodiment, the P type diffusion region 1
3, N ⁺ type diffusion region 15 and P for source contact
Each of the ⁺ diffusion region 27, the gate insulating film 19 and the gate electrode 21 is provided on the N ⁻ type silicon substrate 11 in a square shape (see especially the plan view). The N ⁺ type diffusion region 17 forming the channel portion is provided only on the second P type diffusion region 13b located inside (see particularly the cross-sectional view).

2. Description of Manufacturing Method Next, an example of a method of manufacturing the field effect transistor according to the second invention will be described with reference to FIGS.
Here, FIG. 6 to FIG. 8 are process diagrams showing the state of the sample in the main steps of the manufacturing process of the embodiment by a cross-sectional view at the same position as in FIG.

First, as a first conductive type semiconductor base, N
^{A −} type silicon substrate 11 having an N type impurity concentration of 3.0 × 10 ¹⁵ ions / cm ³ or less, for example, a substrate having 2 × 10 ¹⁴ ions / cm ³ is prepared. Next, on this substrate 11, a diffusion mask 41 having an opening 41a exposing a portion corresponding to a region where the P-type diffusion region 13 of the substrate 11 is to be formed is formed (FIG. 6).
(A)). The diffusion mask 41 is formed by the following procedure in this embodiment. First, an oxide film (silicon oxide film) having a thickness of, for example, at least 300 nm is grown on the surface of the substrate 11 by, for example, a thermal oxidation method. Next, in this oxide film, an opening 41a exposing a portion of the substrate 11 corresponding to a region where the P-type diffusion region 13 is to be formed is formed by a known photolithography technique and etching technique.
As a result, the diffusion mask 41 is obtained.

Impurities for forming the P type diffusion region 13 are introduced into the substrate 11 on which the diffusion mask 41 has been formed.
This is done in the following procedure in this embodiment. First, substrate 1
An oxide film (not shown) having a film thickness of about 10 to 100 nm is formed as a diffusion control film on one surface. Next, using, for example, a resist pattern 43 having an opening narrower than the opening of the diffusion mask 41 as a mask, the substrate 11 is exposed to, for example, 5.0 × 10 ^12.
Boron, for example, is implanted at a dose of about 2.0 × 10 ¹⁴ ions / cm ² . Next, after removing the resist pattern, the sample is annealed, for example, 900 to 12
At a suitable temperature in the temperature range of 00 ° C. and for example 30 to 24
The first P-type diffusion region 13a is formed by performing a suitable time within the range of 0 minutes (FIG. 6 (B)). Next, an oxide film (not shown) having a film thickness of about 10 to 100 nm is formed again as a diffusion control film on the surface of this sample. Then, using the diffusion mask 41 as a mask, this sample is subjected to, for example, 1.0 × 10 ¹³
Boron, for example, is implanted at a dose of about 2.0 × 10 ¹⁴ ions / cm ² . Next, this sample is annealed at a suitable temperature in the temperature range of 900 to 1200 ° C. for a suitable time in the range of 30 to 240 minutes to form the second P-type diffusion region 13b. As a result, the first P-type diffusion region 13a and the second P-type diffusion region 1 are formed.
A P-type diffusion region 13 composed of 3b and 3b is obtained (FIG. 6C). When the P-type diffusion region 13 is formed separately for the first and second P-type diffusion regions 13a and 13b as described above, P having a clear concentration profile also in the surface layer portion.
The mold diffusion region 13 is easily obtained.

After the P-type diffusion region 13 is formed, the diffusion mask 41 is subjected to an etching treatment so that the opening dimension of the opening 41a of the diffusion mask 41 expands by a predetermined dimension. Therefore, in this embodiment, the diffusion mask 41 is etched with an etching solution using hydrofluoric acid so that the opening 41a of the diffusion mask 41 expands by a predetermined dimension in each direction. This predetermined dimension means that the lateral end of the N ⁺ type diffusion region for the channel portion to be formed in the surface layer portion of the P type diffusion region 13 is the second
This is a dimension that can be a diffusion mask that can be projected within 1 μm with respect to the lateral end of the P-type diffusion region 13b, and can be, for example, about 1.4 μm. Since it is possible to etch the silicon oxide film with an accuracy of 50 nm / min with good reproducibility by using a hydrofluoric acid-based etching solution in which the concentration and temperature are controlled, the opening 41a of the diffusion mask 41 is formed in a predetermined manner as described above. It is possible to spread with good dimensional control. Of course, the etching means may be any other suitable method. The diffusion mask 41 that has been subjected to the etching treatment is shown as 41x in the following figures.

Diffusion mask 41x that has been etched
Then, the first conductivity type diffusion region forming the channel portion is formed in the sample in the state of having. In this embodiment, this is performed according to the following procedure. First, an oxide film (not shown) having a thickness of about 10 to 100 nm is formed again as a diffusion control film on the surface of the sample having the diffusion mask 41x that has been subjected to the etching process. Next, using the diffusion mask 41x that has been subjected to the etching process as a mask, this sample is subjected to, for example,
Phosphorus, for example, is implanted at a dose amount of 0 × 10 ^{12 to} 2.0 × 10 ¹⁴ ions / cm ² . Next, the sample is annealed at a suitable temperature in the temperature range of, for example, 900 to 1200 ° C. and for a suitable time in the range of, for example, 30 to 240 minutes to form a diffusion region of the first conductivity type forming the channel portion. Forming an N ⁺ type diffusion region 17 as shown in FIG.
(A)). Diffusion mask 41x that has been etched
Is the one in which the opening 41a of the diffusion mask 41 is widened by a predetermined dimension (formed in a self-aligned manner), so that the lateral end of the N ⁺ type diffusion region 17 is the second P type diffusion region. The region 13b is formed so as to have a substantially coincident positional relationship with the lateral end of the region 13b. Therefore, the P-type diffusion region 13
Since it is possible to reduce the degree of the presence of the high-concentration N-type portion around the end portion of 1) as compared with the conventional case, the electric field concentration can be reduced as compared with the conventional case. As a result, a field effect transistor having an improved breakdown voltage can be manufactured with good reproducibility.

After that, N ⁺ for the source contact is formed by a known photolithography technique and ion implantation technique.
The type diffusion region 15 and the P ⁺ diffusion region 27 are formed (FIG. 7B). Next, the gate insulating film 19 and the gate electrode 21 are respectively formed by a known film forming technique and fine processing technique (FIG. 8A). Next, the intermediate insulating film 23 and the contact hole 23a are formed by a known film forming technique and fine processing technique, and then the wiring (source electrode) 25 is formed (FIG. 8B). The gate electrode 21 can be formed of, for example, polysilicon, and the wiring can be formed of, for example, aluminum.

Although the embodiments of the structure and manufacturing method of the field effect transistor of the present application have been described above, the present invention is not limited to the above embodiments.

For example, in each of the above-mentioned embodiments, the example of the N-channel type field effect transistor is shown, but both the first and second inventions can be applied to the P-channel type field effect transistor. In that case, in the configuration of the embodiment, all conductivity types may be opposite conductivity types.

Further, in the above-described embodiment of the manufacturing method, an example is shown in which the opening 41a of the diffusion mask 41 is widened by a predetermined dimension in all directions. This is the second P-type diffusion region 13b.
This is because the example in which the channel portion is formed in the entire surface layer portion other than the regions where the high-concentration diffusion regions 25 and 27 for the source contact are formed is considered. However, when forming a channel part in a part of the surface layer part of the second P-type diffusion region 13b (for example, in the case of the example shown in FIG. 5), it is only necessary to widen the dimension in the necessary direction. Good. In that case, it is preferable to mask a part of the second P-type diffusion region 13b in the implanter for forming the channel portion.

Further, in the above-mentioned embodiment of the manufacturing method, an example in which the diffusion control film is used in the implantation is shown, but by adjusting the dose amount and the annealing condition in the implantation, each diffusion control film is not used. It is also possible to form a diffusion region.

Further, in the above-mentioned embodiment of the manufacturing method, the example in which the grown oxide film is used as the material for forming the diffusion mask 41 is shown. However, the deposited oxide film, the grown nitride film, the deposited nitride film, the grown silicon oxynitride (oxynitride film), or the deposited silicon oxynitride is used as a diffusion mask forming material. Is also good.

[0030]

As is apparent from the above description, according to the field effect transistor of the first invention of this application,
Since these diffusion regions are provided so that the lateral ends of the diffusion regions of the conductivity type and the diffusion regions of the first conductivity type that form the channel portion are in substantially the same relationship, the diffusion regions of the second conductivity type are Since the extent to which the periphery of the end portion becomes the high-concentration first conductivity type diffusion region is reduced as compared with the related art, the electric field concentration at the end portion of the second conductivity type diffusion region is relaxed as compared with the related art. Therefore, it is possible to provide a diffusion-type and depletion-type field effect transistor having a higher breakdown voltage than before.

Further, according to the method of manufacturing a field effect transistor of the second invention of this application, the diffusion mask itself used for forming the diffusion region of the second conductivity type is diffused by a predetermined dimension by etching. The mask is used as a diffusion mask when forming the diffusion region of the first conductivity type that forms the channel portion. Therefore, the diffusion region of the first conductivity type forming the channel portion can be formed in a predetermined size relationship with the diffusion region of the second conductivity type in a self-aligned manner, so that the diffusion region of the second conductivity type and the channel portion can be formed. It is possible to easily provide the field effect transistor in which the lateral ends of the respective diffusion regions of the first conductivity type that are formed are in substantially the same relationship. Therefore, it is possible to provide a method capable of manufacturing a diffusion-type and depletion-type field-effect transistor, which has a higher withstand voltage than before, with good reproducibility and at low cost.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the first invention.

FIG. 2 is an explanatory diagram of the first invention, and is a diagram showing the relationship between the overhanging dimension of the channel portion and the breakdown voltage.

FIG. 3 is an operation explanatory diagram of the FET according to the first embodiment of the first invention.

FIG. 4 is an explanatory diagram of a second embodiment of the first invention.

FIG. 5 is an explanatory diagram of a third embodiment of the first invention.

6 (A) to 6 (C) are process drawings for explaining an example of a manufacturing method.

7A and 7B are process diagrams following FIG. 6 for explaining an example of a manufacturing method.

8A and 8B are process drawings following FIG. 7 for explaining an example of a manufacturing method.

FIG. 9 is an explanatory diagram (1) of the problem.

FIG. 10 is an explanatory diagram (2) of the problem.

FIG. 11 is an explanatory diagram (3) of the problem.

[Explanation of symbols]

11: First conductivity type semiconductor base (N ⁻ type silicon substrate) 13: Second conductivity type diffusion region (P type diffusion region) 13a: First second conductivity type diffusion region 13b: Second second Conductive type diffusion region 15: High-concentration first conductive type diffusion region (N ⁺ type diffusion region for source contact) 17: First conductive type diffusion region (N
⁺ Type diffusion region) 19: gate insulating film 21: gate electrode 23: intermediate insulating film 25: wiring (source electrode) 27: high-concentration second conductivity type diffusion region (P ⁺ type diffusion region for source contact) 41 : Diffusion mask 41x: Diffusion mask that has been etched

Claims (5)

[Claims] 1. A semiconductor substrate of the first conductivity type, a diffusion region of the second conductivity type formed in a part of the substrate, and a partial surface of the diffusion region of the second conductivity type and a depth shallower than the region. Of the high-concentration first-conductivity-type diffusion region and the second-conductivity-type diffusion region formed on the surface layer portion other than the portion where the high-concentration first-conductivity-type diffusion region is formed. A first-conductivity-type diffusion region which is formed in at least a part and constitutes a channel portion;
A depletion-type field effect transistor, comprising: a gate insulating film formed on the first-conductivity-type diffusion region, wherein the first-conductivity-type diffusion that constitutes the second-conductivity-type diffusion region and the channel portion. A field effect transistor characterized in that these diffusion regions are provided so that the lateral ends of the regions are substantially aligned with each other. 2. The field effect transistor according to claim 1, wherein the substantially coincident range is a diffusion region of the first conductivity type that forms a channel portion with respect to a lateral end of the diffusion region of the second conductivity type. A field-effect transistor, characterized in that the range from the state where the ends of the regions are aligned to the state where the region ends are extended by 1 μm. 3. The field effect transistor according to claim 1, wherein the diffusion region of the second conductivity type includes a diffusion region of a first second conductivity type and a diffusion region of the first second conductivity type. The electric field effect is characterized in that the electric field effect is formed by a second conductive type diffusion region formed in a surface layer part of the region and having a depth deeper than the first conductive type diffusion region forming the channel part. Transistor. 4. A first conductive type semiconductor base, a second conductive type diffusion region formed in a part of the base, and a partial surface of the second conductive type diffusion region having a depth shallower than the region. Of the high-concentration first-conductivity-type diffusion region and the second-conductivity-type diffusion region formed on the surface layer portion other than the portion where the high-concentration first-conductivity-type diffusion region is formed. A first-conductivity-type diffusion region which is formed in at least a part and constitutes a channel portion;
In manufacturing a depletion-type field effect transistor including a gate insulating film formed on the first-conductivity-type diffusion region, a first-conductivity-type semiconductor base is formed on the first-conductivity-type semiconductor base. A step of forming a diffusion mask having an opening that exposes a portion corresponding to a region where a diffusion region is to be formed, and a second conductivity type diffusion region on the first conductivity type semiconductor base on which the diffusion mask has been formed. A step of introducing impurities for forming, a step of performing an etching process so that the opening size of the opening of the diffusion mask is expanded by a predetermined size after finishing the step of introducing the impurities, and the etching process is completed. And a step of introducing an impurity for forming a first-conductivity-type diffusion region forming a channel portion into a semiconductor underlayer having a diffusion mask. Method of manufacturing a register. 5. The method of manufacturing a field effect transistor according to claim 4, wherein the impurities for forming the diffusion region of the second conductivity type are introduced to a deep depth of the base. A method of manufacturing a field effect transistor, comprising: performing a first step and a second step of introducing into the surface layer portion of the base in this order.