CN101621072A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, which are suitable for high-voltage operation, and the device comprises: a substrate having a first conductivity; a plurality of isolation structures disposed on a surface of the substrate; a well disposed in the substrate between the isolation structures, having a second conductivity opposite the first conductivity and an exposed surface; a body region disposed in a portion of the well, having a first conductivity that is the same as the substrate and a concave surface; a gate stack disposed on a portion of the substrate partially covering the exposed surface of the well and the recessed surface of the base region; a drain region disposed in another portion of the well and not covered by the gate stack, having the second conductivity; a source region disposed in a portion of the body region and having the second conductivity; and a body contact region disposed in another portion of the body region, having the first conductivity and adjacent to the source region.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to integrated circuit fabrication, and more particularly to a semiconductor device suitable for high voltage operation and its fabrication method.

Background technique

In recent years, with the development of semiconductor integrated circuit manufacturing technology, the demand for components such as controllers, memories, low-voltage operating circuits, and high-voltage operating circuits formed on a single chip has also increased, so as to produce higher integrated circuits. single chip system.

In a system-on-a-chip, high-voltage components such as double-diffused metal oxide semiconductor (DMOS) devices and power semiconductor devices (IGBTs) are usually used to improve power conversion efficiency and reduce power loss. DMOS devices have the advantages of low power loss and high-speed operation, making them one of the choices for high-voltage device applications.

The DMOS devices are roughly classified into two types: a lateral DMOS (lateral DMOS, LDMOS) device and a vertical DMOS (vertical DMOS, VDMOS) device. The fabrication of VDMOS devices usually involves the use of epitaxial processes, while the fabrication of LDMOS devices does not necessarily require the use of epitaxial processes and can use standard complementary metal-oxide-semiconductor (CMOS) processes, so it has better process integration. However, compared to VDMOS devices, LDMOS devices have higher on-resistance (Rds_on) and require larger device pitches. Therefore, with the shrinking trend of single chip system size, it is necessary to improve the high on-resistance and device pitch of the LDMOS device to enhance its applicability.

Please refer to FIG. 1 , which shows a cross-section of a known horizontal double-diffused metal-oxide-semiconductor (LDMOS) device.

As shown in FIG. 1 , the LDMOS device mainly includes a P-type silicon substrate 100 , a part of which is provided with an N-type well 102 . Field oxides (field oxide, FOX) 104 are respectively disposed on the surface of the junction of the N-type well 102 and the P-type silicon substrate 100 , thus the field oxides 104 roughly define the active region of the LDMOS device. These field oxides 104 are formed by known field oxide methods. A P-type body region 106 is disposed in the N-type well 102 between the field oxides 104 , which is formed in a part of the N-type well 102 and is generally adjacent to the field oxide 104 on the opposite left side. An N-region 113, an N+ region 114S, and a P+ region 116 are additionally provided in the P-type base region 106, wherein the N-region 113 is a lightly doped region, and the P+ region 116 is adjacent In the N+ region 114S, these two regions are exposed on the surface of the P-type body region 106 to serve as contact regions for the source and the body. An N+ region 114D is additionally provided in the N-type well 102 between the P-type body region 106 and the field oxide 104 on the right to serve as a drain. A gate stack G is formed on a part of the surface of the N-type well 102 interposed between the field oxide 104 to serve as a gate, which includes a gate dielectric layer 110 sequentially stacked on the surface of the N-type well 102 , Gate electrode 108 . Spacers 112 are disposed on the symmetrical sides of the gate dielectric layer 110 and the gate electrode 108 in the gate stack G. As shown in FIG. The gate stack G partially covers the P-type body region 106 and covers the N− region 113 here.

Herein, in the LDMOS device shown in FIG. 1 , the symbol L indicates the channel length, which is defined as the distance from the N-region 113 to the side of the P-type body region 106 under the gate stack G. In addition, the symbol P indicates the device pitch, which is defined as the distance from the junction of the N+ region 114S and the P+ region 116 to the midpoint of another N+ region 114D. However, the gate stack G disposed horizontally on the upper surface of the P-type substrate 100 may not be conducive to the reduction of the device pitch P, and thus is not conducive to the reduction of the on-resistance (Rds_on) of the LDMOS device.

Contents of the invention

The invention provides a semiconductor device and its manufacturing method, which are suitable for the application and preparation of high-voltage components.

According to an embodiment, the semiconductor device of the present invention includes:

a substrate having a first conductivity; a plurality of isolation structures arranged on the surface of the substrate; a well arranged in the substrate between the isolation structures and having a conductivity opposite to that of the first conductivity a second conductivity and an exposed surface; a body region disposed in a portion of the well having the same first conductivity as the substrate and a concave surface; a gate stack disposed on a portion of the substrate partially covering the exposed surface of the well and the concave surface of the base region; a drain region disposed in another portion of the well and not being the gate covered by the stack, having the second conductivity; a source region, disposed in a portion of the body region, having the second conductivity; and a body contact region, disposed in another portion of the body region A portion has the first conductivity and is adjacent to the source region.

According to another embodiment, the method for manufacturing a semiconductor device of the present invention includes:

providing a semiconductor substrate having a well disposed therein, wherein the semiconductor substrate has a first conductivity, and the well has a second conductivity opposite to the first conductivity and an exposed surface; at A plurality of isolation structures are formed on the surface of the semiconductor substrate, wherein one of the isolation structures is formed on the semiconductor substrate in the well; a patterned shielding layer is formed on the semiconductor substrate to expose the isolation structure located in the well; perform an ion implantation step, using the shielding layer as an etching mask to form a base region under the isolation structure in the well, The base region has a first conductivity; performing an etching step, using the shielding layer as an etching mask, etching and removing the isolation structure in the well to expose the base region, wherein the a base region having a concave surface lower than the adjacent semiconductor substrate; removing the shielding layer; forming a patterned gate stack partially covering the concave surface of the base region and The surface of the well; a source region and a drain region are respectively formed in a part of the base region and a part of the well, wherein the source region and the drain region are not the a gate stack covering and having the second conductivity; and forming a body contact region in another portion of the body region, the body contact region being adjacent to the source region and not being the gate stack covered by an object and have the first conductivity.

The solution of the present invention is beneficial to the reduction of the device pitch P, and therefore also beneficial to the reduction of the on-resistance (Rds_on) of the LDMOS device.

Description of drawings

Figure 1 shows a cross-sectional view of a known horizontal double-diffused metal-oxide-semiconductor (LDMOS) device; and

2 to 7 are a series of schematic diagrams respectively showing the cross-sections of a horizontal double-diffused metal-oxide-semiconductor (LDMOS) device in different manufacturing steps according to an embodiment of the present invention.

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, together with the accompanying drawings, and is described in detail as follows:

Please refer to a series of schematic diagrams shown in FIGS. 2 to 7, respectively showing the fabrication of a horizontal double-diffused metal-oxide-semiconductor (LDMOS) device according to an embodiment of the present invention, so as to prepare a device with a lower on-resistance. LDMOS devices.

Referring to FIG. 2 , a semiconductor substrate 200 is provided first, and a well 202 is disposed therein. The conductivity of the well 202 is different from that of the substrate 200, and its doping concentration is, for example, between 10 ¹² and 10 ¹³ atoms/per square centimeter. Here, the semiconductor substrate 200 is, for example, an epitaxial layer substrate—a silicon-on-insulator (SOI) substrate or a bulk silicon substrate. The semiconductor substrate 200 has a first conductivity, such as P-type or N-type conductivity, and preferably P-type conductivity, and its doping concentration is, for example, 10 ¹¹ -10 ¹³ atoms/cm2. The well 202 can be formed by known ion implantation methods using a suitable mask (not shown). Next, a pad oxide layer 204 and a pad nitride layer 206 are formed overlying on the semiconductor substrate 200 , which are stacked on the semiconductor substrate 200 in sequence. Then, a plurality of openings are formed in the pad oxide layer 204 and the pad nitride layer 206 by a photolithography and etching step (both not shown), so as to partially expose the semiconductor substrate 200 thereunder respectively. Here, the openings are shown as the opening OP1 on both sides and the central opening OP2, wherein the size of the opening OP2 is slightly larger than the size of the opening OP1, but it is not limited thereto, and the size of the opening OP2 can also be equal to or smaller than Dimensions of opening OP1. The opening OP1 respectively exposes a part of the semiconductor substrate 200 and the well 202 thereunder, while the opening OP2 only exposes a part of the well 202 . The material of the pad oxide layer 204 is, for example, silicon dioxide, and the material of the pad nitride layer 206 is, for example, silicon nitride.

Referring to FIG. 3 , isolation structures 208 a and 208 b are formed in the opening OP1 and the opening OP2 respectively. After the formation of the isolation structures 208 a and 208 b , a patterned mask layer 210 is formed to expose the isolation structure 208 b and its adjacent pad nitride layer 206 . An ion implantation step 212 is then performed to form a body region 214 in the well 202 below the isolation structure 208b. The body region 214 has the same conductivity as the substrate 200, and its doping concentration is, for example, between 10 ¹² ~ 10 ¹⁴ atoms/cm2. As shown in FIG. 3 , the isolation structures 208a and 208b are shown as field oxide (FOX), which is formed by thermal oxidation, but the isolation structures 208a and 208b are not limited by the field oxide. Other isolation structures such as shallow trench isolation (STI) may also be used. The body region 214 can also be formed before the isolation structures 208a and 208b by using appropriate masks and using N-type or P-type ions. The material of the mask layer 210 is, for example, a photoresist material.

Referring to FIG. 4, after removing the isolation structure 208b by an etching step (not shown), the mask 210, the pad nitride layer 206, and the pad oxide layer 204 are etched to remove the film layers, thereby exposing the isolation structure. 208a and the surface 250 of the base region 214 . Here, the surface of the base region 214 is a concave surface 250 lower than the surface of the semiconductor substrate 200 , and the concave surface 250 is a rounded surface, so that the base region 214 has a substantially U-shaped cross section. Next, a gate dielectric layer 216 and a conductive layer 218 are sequentially formed on the semiconductor substrate 200, so as to conformably cover the surface of the semiconductor substrate 200, the concave surface 250 and the isolation structure 208a. As shown in FIG. 4 , the formation method of the gate dielectric layer 216 is, for example, a thermal oxidation method, so its material can be silicon oxide material, and the base region 214 previously formed in the first well 202 is formed when the gate dielectric layer 216 is formed. After further diffusion, a diffused base region 214 ′ is formed, and a gate dielectric layer 216 and a conductive layer 218 are sequentially formed on the semiconductor substrate 200 to have a partially concave and partially convex surface. The material of the conductive layer 218 can be doped polysilicon or metal material of tungsten silicide.

Referring to FIG. 5 , then, a patterned mask layer (not shown) is formed on the conductive layer 218 to expose part of the conductive layer 218 . An etching step (not shown) is then performed to remove portions of the conductive layer 218 and the gate dielectric layer 216 exposed by the patterned mask layer, thereby forming two separated gate stacks on a portion of the semiconductor substrate 200 respectively. Objects G1 and G2 respectively partially cover a portion of the body region 214 ′ and expose a portion of the body region 214 ′ between the gate stacks G1 and G2 . A patterned mask layer 220 is then formed to partially expose the gate stacks G1 and G2 and the base region 214 ′ therebetween. Next, an ion implantation step 222 is performed to dope dopants having the same conductivity as the well 202 to form a shallowly doped region 224 in a part of the body region 214'. The doping concentration used in the ion implantation step 222 is, for example, 10 ¹² -10 ¹³ atoms/cm2.

Referring to FIG. 6 , after removing the patterned mask layer 220 , a spacer 226 is then formed on the corresponding sidewalls of the gate stacks G1 and G2 . The body region 214' and the well 202 are then doped with dopants having the same conductivity as the well 202 by application of a suitable implant mask (not shown) to form a source region 228s and a drain, respectively. The doping concentration used in the region 228d is, for example, 10 ¹⁴ -10 ¹⁵ atoms/cm2. The body region 214' is then doped with a dopant having a conductivity different from that of the well 202 by application of another suitable implant mask (not shown) to form a body contact region 230 using the The doping concentration is, for example, 10 ¹⁴ -10 ¹⁵ atoms/cm 2 , and the body contact region 230 is roughly located between the two source regions 228s, and the source regions 228s are respectively adjacent to and in contact with the lightly doped regions 224 .

As shown in FIG. 6 , the LDMOS device is shown here as having two correspondingly disposed LDMOS devices, which are mirror-symmetrically disposed on the semiconductor substrate 200 with respect to the body contact 230 . Here, in the LDMOS device shown in FIG. 6 , the symbol L' shows the channel length of each LDMOS device, which is defined from the lightly doped region 224 to the P-type substrate located under the gate stacks G1 and G2 distance to one side of zone 214'. In addition, the symbol P′ shows the device pitch of each LDMOS device, which is defined as the distance from the junction of the body contact region 230 and each source region 228s to the midpoint of the drain region 228d. Therefore, referring to the result shown in FIG. 6, since the base region 214' has a concave surface lower than the surface of the adjacent semiconductor substrate 200, the subsequently formed gate stacks G1 and G2 can be partially disposed on the above concave surface instead of being entirely horizontal. The ground is located on the semiconductor substrate 200 , thereby reducing the horizontal lengths of the gate stacks G1 and G2 on the semiconductor substrate 200 . Therefore, compared with the LDMOS device shown in FIG. 1 , the device pitch P in the LDMOS device shown in FIG. 6 can be further reduced, thus reducing its on-resistance (Rds_on).

Moreover, since the body region 214' is formed before the formation of the gate stacks G1 and G2, the channel length L' of the LDMOS device in the LDMOS device shown in FIG. 6 can be defined by the gate stacks G1 and G2. Therefore, the channel length L' can be controlled more precisely, and devices with different channel lengths can be formed by adjusting the width of different field oxide layers in the base region 214'.

Please continue to refer to FIG. 7 , and then an interlayer dielectric layer 230 can be formed covering the structure shown in FIG. 6 . Then, a plurality of electrically independent conductive contacts 232d and 232s are formed in the interlayer dielectric layer 230 to respectively contact each drain electrode 228d, the body contact region 230 and each source region 228s. Then, several electrically independent wires 234 are formed on the interlayer dielectric layer 230, and these wires 234 respectively cover the conductive contacts 232d and 232s, and then form an electrical connection relationship with a part of the LDMOS device below them. The conductive contacts 232d and 232s and the wire 234 can be formed by known contact and wire processes, and the material can be conductive materials such as doped polysilicon, tungsten or aluminum. Here, the conductive contact 232s simultaneously contacts the base contact region 230 and the adjacent source 228s.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art may make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended claims.

Claims (16)

1, a kind of semiconductor device is applicable to high voltage operation, it is characterized in that, described device comprises:

One substrate has one first conductivity;

A plurality of isolation structures are arranged at the surface of described substrate;

One trap is arranged in the described substrate between described isolation structure, has one second conductivity and an exposing surface in contrast to described first conductivity;

One matrix area is arranged in the part of described trap, has described first conductivity and the recessed surface that are same as described substrate;

One grid stacking material is arranged on the part of described substrate, and part covers the described recessed surface of the described exposing surface and the described matrix area of described trap;

One drain region is arranged in another part of described trap and is not covered by described grid stacking material, has described second conductivity;

The one source pole district is arranged in the part of described matrix area, has described second conductivity; And

One matrix contact zone is arranged in another part of described matrix area, has described first conductivity and contiguous described source area.

2, device according to claim 1 is characterized in that described first conductivity is P-type conduction and described second conductivity is N type conductivity.

3, install according to claim 1, it is characterized in that described matrix area does not contact described isolation structure.

4, install according to claim 1, it is characterized in that, the dopant concentration in described source area and the described drain region is higher than the dopant concentration in the described trap, and the dopant concentration of described matrix contact zone is higher than the dopant concentration in the described matrix area.

5, install according to claim 1, it is characterized in that described grid stacking material has a non-smooth surface.

6, install according to claim 1, it is characterized in that the described recessed surface of described matrix area is a smoothing surface that is lower than the described exposing surface of described substrate.

7, install according to claim 1, it is characterized in that, matrix area has a section of U type substantially.

8, device according to claim 1 is characterized in that described device more comprises a shallow doped region, is arranged in the described matrix area and adjacent to described source area but non-conterminous in described matrix contact zone.

9, a kind of manufacture method of semiconductor device, described semiconductor device is applicable to high voltage operation, described method comprises:

Semi-conductive substrate is provided, is provided with a trap in it, wherein said Semiconductor substrate has one first conductivity, and described trap has one second conductivity and an exposing surface in contrast to described first conductivity;

Form a plurality of isolation structures on the surface of described Semiconductor substrate, one of wherein said isolation structure is on the described Semiconductor substrate that is formed in the described trap;

A screen that forms patterning is on described Semiconductor substrate, to expose the described isolation structure that is positioned at described trap;

Carry out an ion implantation step, as etch mask, form a matrix area with the below of the described isolation structure in described trap with described screen, described matrix area has one first conductivity;

Carry out an etching step, as etch mask, etching is removed the described isolation structure in the described trap with described screen, and to expose described matrix area, wherein said matrix area has a recessed surface that is lower than contiguous described Semiconductor substrate;

Remove described screen;

Form a grid stacking material of patterning, part covers the described recessed surface of described matrix area and the surface that is close to the described trap of described matrix area;

Form an one source pole district and a drain region in the part of described matrix area and in the part of described trap respectively, wherein said source area and described drain region are not covered by described grid stacking material and are had described second conductivity; And

Form a matrix contact zone in another part of described matrix area, described matrix contact zone is adjacent to described source area and do not covered by described grid stacking material and have described first conductivity.

As method as described in the claim 9, it is characterized in that 10, described first conductivity is P-type conduction and described second conductivity is N type conductivity.

11, as method as described in the claim 9, it is characterized in that described matrix area does not contact described isolation structure.

As method as described in the claim 9, it is characterized in that 12, the dopant concentration in described source area and the described drain region is higher than the dopant concentration in the described trap, and the dopant concentration of described matrix contact zone is higher than the dopant concentration in the described matrix area.

13, as method as described in the claim 9, it is characterized in that described grid stacking material has a non-smooth surface.

14, as method as described in the claim 9, it is characterized in that the described recessed surface of described matrix area is a smoothing surface.

As method as described in the claim 9, it is characterized in that 15, matrix area has a section of U type substantially.

16, as method as described in the claim 9, it is characterized in that, form respectively in the part of described matrix area and in the part of described trap before described source area and the described drain region, more be included in the step that forms a shallow doped region in the described matrix area, described shallow doped region has described second conductivity and is not covered by described grid stacking material.

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