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TW517358B - Layout structure and method of chipset with ball grid array package - Google Patents

Layout structure and method of chipset with ball grid array package Download PDF

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Publication number
TW517358B
TW517358B TW90128178A TW90128178A TW517358B TW 517358 B TW517358 B TW 517358B TW 90128178 A TW90128178 A TW 90128178A TW 90128178 A TW90128178 A TW 90128178A TW 517358 B TW517358 B TW 517358B
Authority
TW
Taiwan
Prior art keywords
pad
wiring layer
key signal
signal
die
Prior art date
Application number
TW90128178A
Other languages
English (en)
Inventor
Nai-Shuen Jang
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to US10/072,213 priority Critical patent/US6583365B2/en
Application granted granted Critical
Publication of TW517358B publication Critical patent/TW517358B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
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    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481Disposition
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    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48233Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
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    • H01L2924/30107Inductance
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    • H05K1/18Printed circuits structurally associated with non-printed electric components
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    • H05K2201/0792Means against parasitic impedance; Means against eddy currents
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    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/094Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
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    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
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    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10689Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Electromagnetism (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

517358 7750twf.doc/〇〇6 Λ7 B:
經濟部智慧財產局員工消費合作社印M 五、發明說明(f) 本發明是有關於一種積體電路之佈線架構,且特別 是有關於一種以球格陣列式封裝來包裝晶片組,其中之佈 線架構與佈線方法。 球格陣列(Ball Gnd Array ;以下簡稱BGA)積體電路 (1C),係爲一種新一代的高接腳數1(^封裝(packaging),其 適用於今日以次微米解析度所製造出來的,極大型積體電 路(Ultra_Large Scale Integration ; ULSI)之封裝使用。由於 積體電路的功能越來越形複雜,以電晶體爲單位的電路數 量之積集程度越來越高,故傳統的QFP (quad flat pack)或 PGA (pin-grid array)已逐漸不符合實際應用的要求。例如, 常見的QFP與PGA只提供一百至二百支1C接腳(PIN), 對於今日複雜的數位邏輯電子電路1C而言,顯然逐漸已 不敷使用。 就以今日廣泛使用的,以六十四位元微處理器爲基 礎的個人電腦而言,其核心邏輯(core logic)電路必須與微 處理器,以及諸如做爲系統主記憶體的動態隨機存取記憶 體(DRAM),與做爲快取記憶體的靜態隨機存取記憶體 (SRAM)等,各以六十四位元的全匯流排寬度連結。因此, 若此種核心邏輯被製作成爲單一晶片的1C,單只是各資料 匯流排與其對應的各個位址匯流排,便必須使用到接近兩 百支接腳,若再加上其他的控制信號,便輕易地會超過三 百支接腳。BGA 1C封裝即爲一種可以符合此種高接腳數 要求的封裝。 以印刷電路技術爲基礎的一小片印刷電路基板 (請先閱讀背面之注意事項再填寫本頁) · -·線· 本紙張尺度適用中國國家標準(CNS)A1規格(」1() x 么、釐) 517358 Λ; Π7 775Otwf. doc/006 五、發明說明(1) (Printed Circuit Board ;以下簡稱PCB),構成了球格陣列 封裝的基底板(substrate)。如同熟習於本技藝之士所習知 者,切割之後的半導體電路晶粒(dle)係先由自動化的取放 機(pick-and_place machines)黏固於此基板的表面上,並再 由焊線機(wire-bonding machines)將電路晶片上的接線墊 以金屬線連接至球格陣列封裝印刷電路基板上的對應焊墊 上。之後再由灌膠機將整個電路晶片,包含其焊線及焊墊 等’全邰予以密封。丨寸_膠硬化之後,基板背面之球格陣 列中的數百個焊球(ball) ’再由迴焊爐(solder refl〇w)處理 形成。 綜上所述,由於目前1C之內包之邏輯功能越來越多 樣化’工作頻率也已局達數百MHz的程度,使得對於Ic 封裝的要求必須要成提供數目夠多的輸入輸出焊墊 Pad) ’同時要能縮短晶粒(die)至接腳的引線長度數目。因 此’近年來BGA封裝已蔚爲高積集度ic包裝之主流,而 使用BGA封裝具有下列優點·· (1) 可提供數目夠多的輸入輸出焊墊。 (2) IC封裝尺寸小,適用於小型裝置例如筆記型電腦 (Notebook) 〇 (3) 引線電感小,適用於高速電路並可減少接地跳動 (Ground Bounce) 〇 (4) 將傳統之引線接腳(Lead PIN)連接方式,改善爲使 用錫球(Ball)之方式與PCB接觸,避免封裝搬運時,造成 接腳折彎或偏移情形。 5 ί --------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用中國國家標準(CN:S)/U規格do X 297公爱) 517358 Λ; Π; 7750twf.d〇c/006 五、發明說明(> ) 請參見第1圖,其爲習知之具有球格陣列式封裝之 晶片組之佈線架構,基底板一般包括有4層之佈線層,分 別爲正面佈線層、電源層、接地層以及背面佈線層,在放 置晶粒120側的正面佈線層中,焊墊金手指區110上之第 一焊墊m、第二焊墊112及第三焊墊113分別以第一長 弧金線131、第二長弧金線132及第三長弧金線133耦接 至晶粒120,而第一焊墊111耦接第一貫孔151,第—貫 孔151於背面佈線層連接上相對應的第一錫球141,同樣 地,第二焊墊112耦接第二貫孔U2,第二貫孔H2於背 面佈線層連接上相對應的第二錫球142,第三焊墊113鞠 接第三貫孔I53,第三貫孔M3於背面佈線層連接上相對 應的第三錫球143。 由第1圖上可知,習知此第一長弧金線131、第二長 弧金線I32及第三長弧金線133,由於長弧金線之長度車交 長,彼此之間容易產生雜訊干擾,影響晶粒120對外賴 訊號的品質。而且,上述第一焊墊111、第二焊墊112及 第三焊墊113分別連接第一貫孔U1、第二貫孔152及第 三貫孔153時,所用之訊號走線(trace)其間的間距很小, 會增加佈線的複雜度及困難度,又同樣容易產生雜訊干 擾。 有鑑於此,本發明提供一種具有球格陣列式封裝之^ 晶片組之佈線架構及佈線方法,可以降低雜訊干擾,並胃 化關鍵訊號走線之佈線設計的複雜度及困難度。 本發明之較佳實施例提供一種具有球格陣列式封裝 6 .扣 --------訂---------線 (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS);\1規格d() χ 297公釐) 517358 Λ7 Γ)7 7750twf.doc/006 五、發明說明(+) (請先閱讀背面之注意事項再填寫本頁) 之晶片組之佈線架構,此晶片組至少包括有晶粒以及基底 板,其中基底板至少包括有正面佈線層以及有背面佈線 層,而晶粒係配置於正面佈線層上,此佈線架構包括:長 弧金線、普通訊號焊墊、第一中弧金線、第一關鍵訊號焊 墊、第二中弧金線、第二關鍵訊號焊墊、第三中弧金線、 防干擾焊墊、第一貫孔、關鍵訊號走線、第一錫球、第二 貫孔、普通訊號走線、第二錫球、以及掛名錫球。 上述長弧金線耦接至晶粒,用以傳送普通訊號,而 普通訊號焊墊係屬於正面佈線層,用以承接長弧金線,並 接續傳送普通訊號。上述第一中弧金線耦接至晶粒,用以 傳送第一關鍵訊號,長弧金線的長度大於此第一中弧金線 的長度,而第一關鍵訊號焊墊係屬於正面佈線層,用以承 接第一中弧金線,並接續傳送第一關鍵訊號,普通訊號焊 墊與晶粒之距離係大於此第一關鍵訊號焊墊與晶粒之距 離。 經濟部智慧財產局員工消費合作社印^ 上述第二中弧金線耦接至晶粒,用以傳送第二關鍵 訊號,長弧金線的長度大於此第二中弧金線的長度,而第 二關鍵訊號焊墊係屬於正面佈線層,用以承接第二中弧金 線,並接續傳送第二關鍵訊號,普通訊號焊墊與晶粒之距 離係大於此第二關鍵訊號焊墊與晶粒之距離。上述第三中 弧金線同樣耦接至晶粒,而防干擾焊墊係屬於正面佈線 層,用以承接第三中弧金線,此防干擾焊墊緊鄰且位於上 述第一關鍵訊號焊墊與第二關鍵訊號焊墊之間,此防干擾 焊墊連接至穩定電源電壓或接地電壓,事實上,本發明只 7 本纸張尺度適用中國國家標f- (CNSM1規格(2】ϋχ297公釐) 517358 經濟部智慧財產局員工消費合作社印製 775〇twf.d〇c/0〇6 五、發明說明(f ) 要每個關鍵訊號焊墊旁配置有防干擾焊墊即可。 上述第一貫孔以及第二貫孔都是用來貫穿基底板, 以電性連接正面佈線層以及背面佈線層。關鍵訊號走線係 屬於正面佈線層,用以連接上述第一關鍵訊號焊墊以及笔 一貫孔。第一錫球係配置於背面佈線層上,此第一錫球牵禹 接至弟一貫孔’用以作爲晶片組之第一關鍵訊號的訊號_ 腳。普通訊號走線係屬於正面佈線層,用以連接上述普通 訊號焊墊以及第二貫孔。第二錫球係配置於背面佈線靨 上,此第二錫球耦接至第二貫孔,用以作爲晶片組之普_ 訊號的訊號接腳。掛名錫球係配置於背面佈線層上,此,揭 名錫球係緊鄰第一錫球,且不連接至任何貫孔,以使關_ 訊號走線與其他訊號走線之最小距離大於普通訊號走線_ 其他訊號走線之最小距離。 本發明所提供之一種具有球格陣列式封裝之晶片組 之佈線架構及佈線方法,係把在基底板上由高弧金線所及 的距離之複數個關鍵訊號焊墊,拉進到中弧金線所及的距 離,並在每個關鍵訊號焊墊之旁側配置接地焊墊或電壓焊 墊,由於晶粒以中弧金線來耦接焊墊,且在兩條中弧金線 所相對應之二個焊墊之間配置一個隔絕用的穩定電壓焊 墊,故能降低中弧金線間之雜訊干擾,又使這些中弧金線 所對應的焊墊所相對應的錫球附近放置相對應的掛名錫 球,由於掛名錫球旁邊不需要貫孔,故能增加走線的間距。 爲讓本發明之上述和其他目的、特徵和優點,能更 加明顯易懂,下文特舉較佳實施例,並配合所附圖示,做 -----------------^ (請先閱讀背面之注意事項再填寫本頁) :氏張尺度適用47國國家標準(CNS)A 1規格(二,川X 297公髮) — " " 517358 Λ; 7750twf.d〇c/〇06 五、發明說明(<) 詳細說明如下: 圖示簡單說明: 弟1 0繪不的疋習知之具有球格陣列式封裝之晶片 組之佈線架構示意圖;以及 第2圖繪示的是本發明之較佳實施例的一種具有球 格陣列式封裝之晶片組之佈線架構示意圖。 第3圖繪示的是本發明之另一較佳實施例的一種具 有球格陣列式封裝之晶片組之佈線架構示意圖° 重要元件標號: 110, 210焊墊金手指區 111第一焊墊 112第二焊墊 113第三焊墊 12〇,220 晶粒 131第一長弧金線 132第二長弧金線 133第三長弧金線 141第一錫球 142第二錫球 143第三錫球 151第一貫孔 152第二貫孔 / 1 53第三貫孔 ,211第一關鍵訊號焊墊 - ? 本紙張尺度適用中國國家標準(CNSM丨規格(」】〇 χ 297公釐) 衣--------訂------Γ---線"^1^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印努 517358 7 7 50twf. doc/00 6 '
~~ - -------- I ) I 五、發明說明(Q ) ' '一~ 212防干擾焊墊 213第二關鍵訊號焊墊 214普通訊號焊墊 231第一中弧金線 232第二中弧金線 233第三中弧金線 2 3 4長弧金線 241第一錫球 242第二錫球 243第一掛名錫球 251第一貫孔 252第二貫孔 260基底板 261關鍵訊號走線 262普通訊號走線 310掛名錫球 320防干擾焊墊 較佳實施例: 請參照第2 Η,其繪獅是細本卿之較佳實施 例的一種具有球格陣列式封裝之晶片組之佈線架構示意 圖,此佈線架構不意圖包括:基底板260、焊墊金手指2 1 0、 第一關鍵訊號焊墊211、防干擾焊墊212、第二關鍵訊號 焊墊213、普通訊號焊墊214、晶粒220、第一中弧金線23 1、 第二中弧金線232、第三中弧金線233、長弧金線234、第 (請先閱讀背面之注意事項再填寫本頁) 參衣 訂---------線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNSM丨規格) 517358 ^75〇twf.doc/006 ------- 發明說明 一錫球241、第二錫球242、第一掛名錫球243、第一貫孔 251、第二貫孔、關鍵訊號走線261、及普通訊號走線 262 等。 本實施例之晶片組至少包括有晶粒220以及基底板 260,其中基底板26〇至少包括有正面佈線層以及有背面 佈線層,例如:基底板包括有4層之佈線層,依序分別爲 正面佈線層 '接地層、電源層、以及背面佈線層,而晶粒 220係配置於正面佈線層上,例如:晶粒220係黏貼於基 底板260之正面佈線層上。由第2圖可輕易看出,焊墊金 手指210之普通訊號焊墊214、第一關鍵訊號焊墊211、 防干擾焊墊212、第二關鍵訊號焊墊213、關鍵訊號走線 261、及普通訊號走線262等皆配置屬於此基底板260之 正面佈線層。但是,有關第一錫球241、第二錫球242、 及第一掛名錫球243等錫球皆配置於此基底板260之背面 佈線層上。 本實施例將晶片組的訊號分成兩個群組:關鍵訊號 群組與普通訊號群組,關鍵訊號群組係包括高頻且重要的 關鍵訊號,例如:位址選通訊號、資料選通訊號以及時脈 訊號等,而普通訊號群組就包括非關鍵訊號群組的普通訊 號,例如:記憶體位址訊號、記憶體行或列控制訊號以及 記憶體寫致能控制訊號等。 球格陣列式封裝中有一種方式係將晶粒與基底板以 不同弧度的接合連接線打線接合。舉例而言,本實施例之 佈線架構中的接合連接線可分爲短弧金線(未繪出)、中弧
(I ^^衣--------tr---------^*- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A丨規格(2丨()X 297公釐) 517358 77 5〇twf. doc/006 八' ^---— Γ>7____ 五、發明說明(,) 金線及長弧金線三種。其中,接地焊墊(未繪出)以短弧金 線來親接至晶粒,各種電源電壓焊墊以中弧金線來稱接至 晶粒,而中弧金線的弧度還可分爲較高弧與較低弧二種, 但都介於短弧金線與長弧金線的弧度之間。 如第2圖所示,長弧金線234耦接至晶粒220,就是 用來傳送普通訊號,而屬於一般焊墊金手指210中之普通 ; 訊號焊墊214就用來承接並連接長弧金線234,以接續傳 j 送普通訊號。其他屬於普通訊號群組之訊號,也可依此類 推,了解其佈線方式。本發明將第一關鍵訊號焊墊211由 長弧金線可及的距離移至第一中弧金線231可及的距離, 亦即’此第一中弧金線2H耦接至晶粒220,用來傳送第 一關鍵訊號,而第一關鍵訊號焊墊211係用來承接第一中 弧金線231,並接續傳送第一關鍵訊號。當然地,長弧金 線234的長度大於第一中弧金線231的長度,而普通訊號 焊墊214與晶粒220之距離係大於此第一關鍵訊號焊墊211 與晶粒220之距離。因此,本發明中關鍵訊號所使用的接 合連接線(中弧金線)比習知技藝所使用之接合連接線(長弧 金線)爲短,自然可減少雜訊干擾。 | 本實施例中,第二中弧金線232耦接至晶粒220,用 # 來傳送第二關鍵訊號,同樣地,長弧金線234的長度大於 ^ 第一中弧金線232的長度,而第二關鍵訊號焊塾21 3承接 音 弟一中弧亞線2 3 2,並接f買傳送第二關鍵訊號,普涌訊^ S 與晶粒220之距離。 (請先閱讀背面之注意事項再填寫本頁) 裝·-------訂---------· 經濟部智慧財產局員工消費合作社印製 517358 7750tw£.doc/006_^_ 五、發明說明(丨D ) 本實施例之另一技術特徵,就是提供了阻隔功能的 電器回路。亦即,提供第三中弧金線233,其同樣耦接至 晶粒220,以及提供了防干擾焊墊212,其用以承接第三 中弧金線233,此防干擾焊墊212緊鄰且位於第一關鍵訊 號焊墊211與第二關鍵訊號焊墊213之間,事實上,本發 明只要每個關鍵訊號焊墊旁配置有防干擾焊墊即可,本發 明之防干擾焊墊212可連接至穩定電源電壓或接地電壓。 與防干擾焊墊212相連之穩定電源電壓係依據實際的連線 方式而定,而在本實施例中,關鍵訊號係主要與中央處理 單元有關,所以穩定電源電壓以CPU之工作電壓(簡稱VTT) 較佳,在實際連線上亦較方便。如熟悉此藝者可輕易知曉, 本發明所揭露之技術應用於其他地方時,所使用之穩定電 源電壓便會有所不同。由於在第一關鍵訊號焊墊211及第 二關鍵訊號焊墊213中間配置了防干擾焊墊212,第一中 弧金線231及第二中弧金線232中間配置了第三中弧金線 233,因此能減少第一中弧金線231及第三中弧金線233 之間互相的雜訊干擾,進一步提高傳輸訊號的品質。 本實施例之另一技術特徵,就是提供了掛名錫球 243。眾所皆知,第一貫孔251以及第二貫孔252都是用 來貫穿基底板,以電性連接正面佈線層以及背面佈線層。 但是明顯地,這些貫孔會佔掉面積,使走線相對必須互相 靠近。本實施例中,關鍵訊號走線261係用來連接第一 PJ 鍵訊號焊墊211以及第一貫孔251,而第一錫球241係配 置於背面佈線層上,此第一錫球241耦接至第一貫孔251, U--------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)Al規格(210x297公釐) 517358
經濟部智慧財產局員工消費合作社印W 5〇twf. doc/006
五、發明說明(丨I 用以作爲晶片組之第一關鍵訊號的訊號接腳。普通訊號走 線262係用以連接普通訊號焊墊214以及第二貫孔252, 而第二錫球242係配置於背面佈線層上,此第二錫球242 耦接至第二貫孔2U,用以作爲晶片組之普通訊號的訊號 接腳。本實施例提供之掛名錫球243同樣配置於背面佈線 層上,此掛名錫球243係緊鄰第一錫球241,且不連接至 任何貫孔,但可定義爲晶片組之接地電壓之接腳,由於掛 名錫球243不連接至任何貫孔,故可使第一貫孔25〗與第 一錫球241附近之走線空間加大,而使第一關鍵訊號走線 261與其他訊號走線之最小距離大於普通訊號262走線與 其他訊號走線之最小距離,當然就可降低訊號走線之間的 雜訊干擾。 * 弟3圖繪不的是本發明之另一^較佳實施例的一^種具 有球格陣列式封裝之晶片組之佈線架構示意圖,其中掛名 錫球310亦緊鄰於訊號用錫球之旁側。另外防干擾焊墊32〇 亦緊鄰於關鍵訊號焊墊旁側。事實上,防干擾焊墊只要在 第一關鍵訊號焊墊211或第二關鍵訊號焊墊213的旁側, 即可達到降低雜訊干擾的目的。 歸結而言,本發明也提供了一種具有球格陣列式封 裝之晶片組之佈線方法,此晶片組至少包括晶粒以及基底 板,而基底板至少包括正面佈線層以及背面佈線層,且晶 粒配置於正面佈線層上,本發明之佈線方法包括下列步 驟:首先提供出普通訊號焊墊,此普通訊號焊墊屬於該正 面佈線層;接著以長弧金線,來連接晶粒以及普通訊號焊 ^--------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國冢標準(CNSM1規格mo X 297公釐) 經濟部智慧財產局員工消費合作社印製 517358 ^^5〇twf. doc/0 05 -----~__
五、發明說明(广D 墊’用以傳送普通訊號;再提供出第一關鍵訊號焊墊,此 第一關鍵訊號焊墊屬於正面佈線層,而普通訊號焊墊與晶 粒之距離要大於第一^關鍵訊號焊墊與晶粒之距離;然後以 第一中弧金線,來連接晶粒以及第一關鍵訊號焊墊,用以 傳送第一關鍵訊號,上述長弧金線的長度要大於第一中弧 金線的長度。 本發明之實施例之佈線方法更包括下列步驟:又提 供出第二關鍵訊號焊墊,此第二關鍵訊號焊墊屬於正面佈 線層,上述普通訊號焊墊與晶粒之距離係大於第二關鍵訊 號焊墊與晶粒之距離;接著以第二中弧金線,連接晶粒以 及第二關鍵訊號焊墊,用以傳送第二關鍵訊號,上述長弧 金線的長度大於此第二中弧金線的長度;再提供防干擾焊 墊,此防干擾焊墊屬於正面佈線層,使防干擾焊墊緊鄰且 位於第一關鍵訊號焊墊與第二關鍵訊號焊墊之間;然後連 接此防干擾焊墊至一穩定電壓;以及再以第三中弧金線, 連接晶粒以及防干擾焊墊。如熟悉此藝者可知曉,本發明 只要每個關鍵訊·號焊墊旁配置有防干擾焊墊即可,所以不 一定需要提供有第二關鍵訊號焊墊以及第二中弧金線。 本發明之實施例之佈線方法更包括下列步驟··利用 第一貫孔貫穿基底板,以電性連接正面佈線層以及背面佈 線層;接著於正面佈線層上,以關鍵訊號走線,來連接第 一^關鍵訊號焊塾以及弟一^貫孔;再提供第一'錫球,配置於 背面佈線層上,用以作爲晶片組之第一關鍵訊號的訊號接 腳;然後連接第一錫球與第一貫孔;同樣地,以第二貫孔 --------^---------^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNSM 1規格(u〇 X Lxj7公楚) 517358 Λ7 7750twf.doc/006 五、發明說明(/>) 貫穿基底板,以電性連接正面佈線層以及背面佈線層;接 著於正面佈線層上,以普通訊號走線,來連接普通訊號焊 墊以及第二貫孔;並提供第二錫球,配置於背面佈線層上, 用以作爲晶片組之該普通訊號的訊號接腳;然後連接第二 錫球與第二貫孔;以及最後提供出掛名錫球,配置於背面 佈線層上,此掛名錫球係緊鄰第一錫球,且不連接至任何 貫孔,以使關鍵訊號走線與其他訊號走線之最小距離大於 普通訊號走線與其他訊號走線之最小距離。 雖然本發明已以較佳實施例揭露於上,然其並非用 以限定本發明,任何熟習此技藝者,再不脫離本發明之精 神和範圍內,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ---------------------訂---------線 . (請先閱讀背面之注意事項再填寫本頁)
經濟部智慧財產局員工消費合作社印K 本紙張尺度適用中國國家標準(CNS)A:丨規格(2K) X 297公楚)

Claims (1)

  1. 登齊平皆秦讨轰01?_11消費^阼^--?製 517358 A8 B8 C8 77 5Otwf. doc/0 0 6 D8 六、申請專利範圍 1. 一種具有球格陣列式封裝之晶片組之佈線架構,該 晶片組至少包括一晶粒以及一基底板,該基底板至少包括 一正面佈線層以及一背面佈線層,該晶粒配置於該正面佈 線層上,該佈線架構至少包括: 一長弧金線,耦接至該晶粒,用以傳送一普通訊號; 一普通訊號焊墊,屬於該正面佈線層,用以承接該 長弧金線,並接續傳送該普通訊號; 一第一中弧金線,耦接至該晶粒,用以傳送一第一 關鍵訊號,該長弧金線的長度大於該第一中弧金線的長 度;以及 一第一關鍵訊號焊墊,屬於該正面佈線層,用以承 接該第一中弧金線,並接續傳送該第一關鍵訊號,該普通 訊號焊墊與該晶粒之距離係大於該第一關鍵訊號焊墊與該 晶粒之距離。 2. 如申請專利範圍第1項所述之具有球格陣列式封裝 之晶片組之佈線架構,更包括: 一第二中弧金線,耦接至該晶粒,用以傳送一第二 關鍵訊號,該長弧金線的長度大於該第二中弧金線的長 度; 一第二關鍵訊號焊墊,屬於該正面佈線層,用以承 接該第二中弧金線,並接續傳送該第二關鍵訊號,該普通 訊號焊墊與該晶粒之距離係大於該第二關鍵訊號焊墊與該 晶粒之距離; 一第三中弧金線,耦接至該晶粒;以及 11 本紙張尺度適用中國國家標準(CNS)A4規格(,210 X 297公釐_) --------------------訂------- (請先閱讀背面之注意事項再填寫本頁) 517358 7750twf.doc/006 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 一防干擾焊墊,屬於該正面佈線層,用以承接該第 三中弧金線,該防干擾焊墊緊鄰且位於該第一關鍵訊號焊 墊與該第二關鍵訊號焊墊之間,該防干擾焊墊連接至一穩 定電壓。 3. 如申請專利範圍第2項所述之具有球格陣列式封裝 之晶片組之佈線架構,其中該第一關鍵訊號以及該第二關 鍵訊號屬於一關鍵訊號群組,該關鍵訊號群組包括:一位 址選通訊號、一資料選通訊號以及一時脈訊號。 4. 如申請專利範圍第2項所述之具有球格陣列式封裝 之晶片組之佈線架構,其中該穩定電壓係爲一接地電壓或 一電源電壓。 5. 如申請專利範圍第1項所述之具有球格陣列式封裝 之晶片組之佈線架構,更包括: 一第一貫孔,用以貫穿該基底板,以電性連接該正 面佈線層以及該背面佈線層; 一關鍵訊號走線,屬於該正面佈線層,用以連接該 第一關鍵訊號焊墊以及該第一貫孔; 一第一錫球,配置於該背面佈線層上,該第一錫球 耦接至該第一貫孔,用以作爲該晶片組之該第一關鍵訊號 的訊號接腳;以及 一掛名錫球,配置於該背面佈線層上,該掛名錫球 係緊鄰該第一錫球,且不連接至任何貫孔,以使該關鍵訊 號走線與其他訊號走線之最小距離大於其他訊號走線之最 小距離。 ίί (請先閱讀背面之注意事項再填寫本頁) - n I —Mr n I l n 一-口T · n n I n n n I I n n n n ϋ ϋ 1· 1« I n n n 1 I n n n I n I ϋ - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 澄齊卽智i材轰¾員工消費合作社印製 517358 A8 B8 C8 7 75 0twf. doc/006 D8 六、申請專利範圍 6. 如申請專利範圍第5項所述之具有球格陣列式封裝 之晶片組之佈線架構,更包括: '一第二貫孔,用以貫穿該基底板,以電性連接該正 面佈線層以及該背面佈線層; 一普通訊號走線,屬於該正面佈線層,用以連接該 普通訊號焊墊以及該第二貫孔;以及 一第二錫球,配置於該背面佈線層上,該第二錫球 耦接至該第二貫孔,用以作爲該晶片組之該普通訊號的訊 號接腳,其中該關鍵訊號走線與其他訊號走線之最小距 離,大於該普通訊號走線之最小距離。 7. 如申請專利範圍第5項所述之具有球格陣列式封裝 之晶片組之佈線架構,其中該掛名錫球係定義爲該晶片組 之接地電壓之接腳。 8. 如申請專利範圍第1項所述之具有球格陣列式封裝 之晶片組之佈線架構,更包括: 一第二中弧金線,耦接至該晶粒;以及 一防干擾焊墊,屬於該正面佈線層,用以承接該第 二中弧金線,該防干擾焊墊係緊鄰該第一關鍵訊號焊墊, 且該防干擾焊墊連接至一穩定電壓。 9. 一種具有球格陣列式封裝之晶片組之佈線架構,該 晶片組至少包括一晶粒以及一基底板,該基底板至少包括 一正面佈線層以及一背面佈線層,該晶粒配置於該正面佈 線層上,該佈線架構至少包括: 一長弧金線,耦接至該晶粒,用以傳送一普通訊號; (請先閱讀背面之注意事項再填寫本頁)
    本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 517358 7750twf.d〇c/006 A8 B8 C8 D8 六、申請專利範圍 一普通訊號焊墊,屬於該正面佈線層,用以承接該 長弧金線,並接續傳送該普通訊號; 一第一中弧金線,耦接至該晶粒,用以傳送一第一 關鍵訊號,該長弧金線的長度大於該第一中弧金線的長 度; 一第一關鍵訊號焊墊,屬於該正面佈線層,用以承 接該第一中弧金線,並接續傳送該第一關鍵訊號,該普通 訊號焊墊與該晶粒之距離係大於該第一關鍵訊號焊墊與該 晶粒之距離; 一第二中弧金線,耦接至該晶粒; 一防干擾焊墊,屬於該正面佈線層,用以承接該第 二中弧金線,該防干擾焊墊係緊鄰該第一關鍵訊號焊墊, 該防干擾焊墊連接至一穩定電壓; 一第一貫孔,用以貫穿該基底板,以電性連接該正 面佈線層以及該背面佈線層; 一關鍵訊號走線’屬於該正面佈線層,用以連接該 第一關鍵訊號焊墊以及該第一貫孔; 一第一錫球,配置於該背面佈線層上,該第一錫球 耦接至該第一貫孔,用以作爲該晶片組之該第一關鍵訊號 的訊號接腳; 一第二貫孔,用以貫穿該基底板,以電性連接該正 面佈線層以及該背面佈線層; 一普通訊號走線,屬於該正面佈線層,用以連接該 普通訊號焊墊以及該第二貫孔; I-------------------訂-I-------線· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 517358 ABCD 7 7 5 Otwf. doc/Ο Ο 6 六、申請專利範圍 一第二錫球,配置於該背面佈線層上,該第二錫球 耦接至該第二貫孔,用以作爲該晶片組之該普通訊號的訊 號接腳;以及 一掛名錫球,配置於該背面佈線層上,該掛名錫球 係緊鄰該第一錫球,且不連接至任何貫孔,以使該關鍵訊 號走線與其他訊號走線之最小距離大於該普通訊號走線與 其他訊號走線之最小距離。 10. 如申請專利範圍第9項所述之具有球格陣列式封 裝之晶片組之佈線架構,更包括: 一第三中弧金線,耦接至該晶粒,用以傳送一第二 關鍵訊號,該長弧金線的長度大於該第三中弧金線的長 度;以及 一第二關鍵訊號焊墊,屬於該正面佈線層,用以承 接該第三中弧金線,並接續傳送該第二關鍵訊號,該普通 訊號焊墊與該晶粒之距離係大於該第二關鍵訊號焊墊與該 晶粒之距離; 其中該防干擾焊墊緊鄰且位於該第一關鍵訊號焊墊 與該第二關鍵訊號焊墊之間。 11. 如申請專利範圍第9項所述之具有球格陣列式封 裝之晶片組之佈線架構,其中該第一關鍵訊號以及該第二 關鍵訊號屬於一關鍵訊號群組,該關鍵訊號群組包括:一 位址選通訊號、一資料選通訊號以及一時脈訊號。 12. 如申請專利範圍第9項所述之具有球格陣列式封 裝之晶片組之佈線架構,其中該穩定電壓係爲一接地電壓 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐〉 --------------------訂---------線 IAW. (請先閱讀背面之注意事項再填寫本頁) 775〇twf H 广^ / Π Π C Α8 Β8 C8
    經齊邹智慧財產局員Η消費合作社印製 517358 、申請專利範圍 或一電源電壓。 1 3 ·如申請專利範圍第9項所述之具有球格陣列式封 _之晶片組之佈線架構,其中該掛名錫球係定義爲該晶片 組之接地電壓之接腳。 14· 一種具有球格陣列式封裝之晶片組之佈線方法, 該晶片組至少包括一晶粒以及一基底板,該基底板至少包 括一正面佈線層以及一背面佈線層,該晶粒配置於該正面 佈線層上,該佈線方法包括下列步驟: 提供一普通訊號焊墊,該普通訊號焊墊屬於該正面 佈線層; 以一長弧金線,連接該晶粒以及該普通訊號焊墊, 用以傳送一普通訊號; 提供一第一關鍵訊號焊墊,該第一關鍵訊號焊墊屬 方令言亥正面佈線層,該普通訊號焊墊與該晶粒之距離係大於 該第一關鍵訊號焊墊與該晶粒之距離;以及 以一第一中弧金線,連接該晶粒以及該第一關鍵訊 號焊墊’用以傳送一第一關鍵訊號,該長弧金線的長度大 於該第一中弧金線的長度。 15.如申請專利範圍第14項所述之具有球格陣列式封 裝之晶片組之佈線方法,更包括下列步驟: 提供一第二關鍵訊號焊墊,該第二關鍵訊號焊墊屬 於該正面佈線層,該普通訊號焊墊與該晶粒之距離係大於 該第二關鍵訊號焊墊與該晶粒之距離; 以一第二中弧金線,連接該晶粒以及該第二關鍵訊 αζ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ill----訂11111! *^ - 查齊邛曾i讨i苟員11消費合阼f£-印親 517358 A8 B8 C8 7 75 0twf. doc/006 D8 六、申請專利範圍 號焊墊,用以傳送一第二關鍵訊號,該長弧金線的長度大 於該第二中弧金線的長度; 提供一防干擾焊墊,該防干擾焊墊屬於該正面佈線 層,該防干擾焊墊緊鄰且位於該第一關鍵訊號焊墊與該第 二關鍵訊號焊墊之間; 連接該防干擾焊墊至一穩定電壓;以及 以一第三中弧金線,連接該晶粒以及該防干擾焊墊。 16.如申請專圍第14項所述之具有球格陣列式封 裝之晶片組之佈線掘^方法,更包括下列步驟: 以一第一貫孔穿該基底板,以電性連接該正面 佈線層以及該背面佈_^; 於該正面佈線層上,以一關鍵訊號走線,連接該第 一關鍵訊號焊墊以及該第一貫孔; 提供一第一錫球,配置於該背面佈線層上,用以作 爲該晶片組之該第一關鍵訊號的訊號接腳; 連接該第一錫球與該第一貫孔; 以一第二貫孔,貫穿該基底板,以電性連接該正面 佈線層以及該背面佈線層; 於該正面佈線層上,以一普通訊號走線,連接該普 通訊號焊墊以及該第二貫孔; 提供一第二錫球,配置於該背面佈線層上,用以作 爲該晶片組之該普通訊號的訊號接腳; 連接該第二錫球與該第二貫孔;以及 提供一掛名錫球,配置於該背面佈線層上,該掛名 --------------------訂---------線 ^i^· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 517358 A8 B8 C8 D8 7750twf.doc/006 六、申請專利範圍 錫球係緊鄰該第一錫球,且不連接至任何貫孔,以使該關 鍵訊號走線與其他訊號走線之最小距離大於該普通訊號走 線與其他訊號走線之最小距離。 17. 如申請專利範圍第14項所述之具有球格陣列式封 裝之晶片組之佈線方法,更包括下列步驟: 提供一防干擾焊墊,該防干擾焊墊屬於該正面佈線 層,該防干擾焊墊係緊鄰該第一關鍵訊號焊墊; 連接該防干擾焊墊至一穩定電壓;以及 以一第二中弧金線,連接該晶粒以及該防干擾焊墊。 18. —種具有球格陣列式封裝之晶片組之佈線架構, 該晶片組至少包括一晶粒以及一基底板,該基底板至少包 括一正面佈線層以及一背面佈線層,該晶粒配置於該正面 佈線層上,該佈線架構至少包括: 一第一中弧金線,耦接至該晶粒,用以傳送一第一 關鍵訊號; 一第一關鍵訊號焊墊,屬於該正面佈線層,用以承 接該第一中弧金線,並接續傳送該第一關鍵訊號; 一第二中弧金線,耦接至該晶粒;以及 一防干擾焊墊,屬於該正面佈線層,用以承接該第 二中弧金線,該防干擾焊墊緊鄰且位於該第一關鍵訊號焊 墊之旁側,該防干擾焊墊連接至一穩定電壓。 19. 如申請專利範圍第18項所述之具有球格陣列式封 裝之晶片組之佈線架構,更包括: 一第三中弧金線,耦接至該晶粒,用以傳送一第二 (請先閱讀背面之注意事項再填寫本頁) ---------訂---------· 經齊郎智慧財產局員Η消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 517358 775Otwf. doc/006 A8 B8 C8 D8 經齊邹智慧財產局員工消費合作社印製 六、申請專利範圍 關鍵訊號;以及 一第二關鍵訊號焊墊,屬於該正面佈線層,用以承 接該第二中弧金線,並接續傳送該第二關鍵訊號; 20. 如申請專利範圍第19項所述之具有球格陣列式封 裝之晶片組之佈線架構,更包括: 一長弧金線,耦接至該晶粒,用以傳送一普通訊號; 以及 一普通訊號焊墊,屬於該正面佈線層,用以承接該 長弧金線,並接續傳送該普通訊號,其中該普通訊號焊墊 與該晶粒之距離,係大於該第一關鍵訊號焊墊與該晶粒之 距離、且大於該第二關鍵訊號焊墊與該晶粒之距離、亦大 於該防干擾焊墊與該晶粒之距離。 21. 如申請專利範圍第20項所述之具有球格陣列式封 裝之晶片組之佈線架構,更包括: 一第二貫孔,用以貫穿該基底板,以電性連接該正 面佈線層以及該背面佈線層; 一普通訊號走線,屬於該正面佈線層,用以連接該 普通訊號焊墊以及該第二貫孔;以及 一第二錫球,配置於該背面佈線層上,該第二錫球 耦接至該第二貫孔,用以作爲該晶片組之該普通訊號的訊 號接腳。 22. 如申請專利範圍第19項所述之具有球格陣列式封 裝之晶片組之佈線架構,其中該第一關鍵訊號以及該第二 關鍵訊號屬於一關鍵訊號群組,該關鍵訊號群組包括=一 (請先閱讀背面之注意事項再填寫本頁) -Lf 訂---------線· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 517358 A8 B8 C8 775Otwf. doc/0 0 6 D8 六、申請專利範圍 位址選通訊號、一資料選通訊號以及一時脈訊號。 (請先閱讀背面之注意事項再填寫本頁) 23. 如申請專利範圍第18項所述之具有球格陣列式封 裝之晶片組之佈線架構,其中該穩定電壓係爲一接地電壓 或一電源電壓。 24. 如申請專利範圍第18項所述之具有球格陣列式封 裝之晶片組之佈線架構,更包括: 一第一貫孔,用以貫穿該基底板,以電性連接該正 面佈線層以及該背面佈線層; 一關鍵訊號走線,屬於該正面佈線層,用以連接該 第一關鍵訊號焊墊以及該第一貫孔; 一第一錫球,配置於該背面佈線層上,該第一錫球 耦接至該第一貫孔,用以作爲該晶片組之該第一關鍵訊號 的訊號接腳;以及 一掛名錫球,配置於該背面佈線層上,該掛名錫球 係緊鄰該第一錫球,且不連接至任何貫孔,以使該關鍵訊 號走線與其他訊號走線之最小距離大於其他訊號走線之最 小距離。 經齊郎智慧財產局員工消費合作钍印製 25. 如申請專利範圍第24項所述之具有球格陣列式封 裝之晶片組之佈線架構,其中該掛名錫球係定義爲該晶片 組之接地電壓之接腳。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐〉
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US20020153166A1 (en) 2002-10-24
US6528872B2 (en) 2003-03-04
US20020156538A1 (en) 2002-10-24
US20020153605A1 (en) 2002-10-24
TW511414B (en) 2002-11-21
US6583365B2 (en) 2003-06-24

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