TW503531B - Multi-layered semiconductor apparatus - Google Patents

Abstract

The present invention relates to a multi-layered semiconductor apparatus where multiple layers of semiconductor integrated circuit chips and the semiconductor integrated circuit apparatus having specification are stacked. In the semiconductor integrated circuit apparatus, at least more than three predetermined semiconductor integrated circuit apparatus are undergone with a stacking layer process based on the order of the specification magnitude.

Description

503531 A7 B7 V. Description of the invention (1) Background of the invention The present invention relates to a stacked semiconductor device in which a plurality of semiconductor integrated circuit devices are stacked. With the reduction in size and weight of electronic devices such as portable devices and mobile devices, electronic components constituting electronic devices are also required to be miniaturized and highly integrated. Therefore, a multilayer semiconductor device (multi-chip device) having three-dimensionally stacked semiconductor integrated circuit wafers (LSI wafers) is required. However, an effective method for stacking semiconductor integrated circuit wafers has not been proposed. SUMMARY OF THE INVENTION A first aspect of the present invention is a stacked semiconductor device that includes a plurality of semiconductor integrated circuit wafers including semiconductor integrated circuit wafers and has specifications. At least three or more predetermined semiconductor integrated circuit devices among the aforementioned semiconductor integrated circuit devices are stacked in the order of the aforementioned specifications and sizes. A second aspect of the present invention is a stacked semiconductor device including at least three or more semiconductor integrated circuit wafers including semiconductor integrated circuit wafers and having specifications. In the aforementioned semiconductor integrated circuit device, the lowermost or uppermost semiconductor integrated circuit The size of the circuit device is either minimum or maximum. A third aspect of the present invention is a stacked semiconductor device including at least two or more semiconductor integrated circuit wafers and semiconductor semiconductor integrated circuit devices having specifications, and the adjacent bulk conductive volume circuit devices are connected to each other through the semiconductor integrated body. The electrical connection of the conductive material of the circuit device. In the aforementioned semiconductor integrated circuit device, the specifications other than the size of the lowermost or uppermost semiconductor integrated circuit device are minimum or maximum. -4- This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

Binding

503531 A7 B7 V. Description of the invention (2) The fourth aspect of the present invention is a stacked semiconductor device including a plurality of semiconductor integrated circuit devices including semiconductor integrated circuit wafers and having specifications. The stacked semiconductor device has A group of a predetermined number of specific semiconductor integrated circuit devices in the semiconductor integrated circuit device. The predetermined number exceeds two and is smaller than the total number of the semiconductor integrated circuit devices. The specifications of the specific semiconductor integrated circuit device. All of them are within a predetermined range and the aforementioned specific semiconductor integrated circuit device is continuously stacked. A fifth aspect of the present invention is a stacked semiconductor device in which a plurality of semiconductor integrated circuit devices including a semiconductor integrated circuit wafer are stacked. In the aforementioned semiconductor integrated circuit device, the specific semiconductor having the largest amount of signal transmission and reception between the semiconductors is continuously stacked. Integrated circuit devices are connected to each other. A sixth aspect of the present invention includes a first semiconductor integrated circuit device including a semiconductor integrated circuit wafer and a plurality of the first semiconductor integrated circuit devices included in the same plane, and a plurality of first semiconductor integrated circuit devices including the plurality of first semiconductor integrated circuit devices. A stacked semiconductor device of a second semiconductor integrated circuit device. Brief Description of the Drawings The country A is an example of a stacked semiconductor device according to an embodiment of the present invention, and a diagram showing a cross-sectional structure thereof in a pattern. Fig. 1B is another example of a multilayer semiconductor device according to an embodiment of the present invention, and schematically shows the cross-sectional structure of the country. FIG. 1C is a view schematically showing a cross-sectional structure of another example of the multilayer semiconductor device according to the embodiment of the present invention. The country 2A and FIG. 2B are countries showing a model of an example of the stacked semiconductor device type 1 according to the embodiment of the present invention. _ 3 A and 3 B are stacked semiconductors related to the embodiment of the present invention. -5- The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm).

Equipment ij 503531

Figure of device type 1 other mode display. Fig. 4A and Fig. 4B are diagrams showing another mode of the laminated bribe device type 1 according to the embodiment of the present invention. i FIG. 5A and FIG. 5B are diagrams showing another mode of the stacked half-bridging device type 1 according to the embodiment of the present invention. Fig. 6A and Fig. 6B are diagrams showing another mode of the stacked half device type 1 according to the embodiment of the present invention. _ 7 A and circle 7 B are diagrams showing the example of a multilayer semiconductor device type 2 of the embodiment of the present invention. — FIG. 8 is a diagram showing an example of a type 3 of a stacked semiconductor device according to an embodiment of the present invention. / FIG. 9 is a diagram showing an example of a stacked semiconductor device type # according to an embodiment of the present invention. FIG. 10 is a diagram showing an example of a multilayer semiconductor device according to an embodiment of the present invention. FIG. 11 is a diagram showing another example of a stacked semiconductor device type 4 according to an embodiment of the present invention. Fig. 12 is a diagram showing a cross-sectional structure of another example of a stacked semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1A shows a first configuration example of a multilayer semiconductor device according to an embodiment of the present invention. A plurality of semiconductor integrated circuit wafers (LSI wafers) are stacked on the base substrate BS

Winter paper size applies Chinese National Standard (CNS) X 297 & HJ 503531 A7 B7 V. Description of the invention (4) S1 ~ S5. The base substrate BS functions as a mother board with terminals TM and wiring patterns (not shown) or Power supply, etc. The semiconductor integrated circuit wafers S1 to S5 are provided with penetration plugs TP made of a conductive material penetrating the semiconductor integrated circuit wafers. Between the terminal TM of the base substrate BS and the lowermost penetration plug τρ and adjacent penetrations The plug τρ is connected by a conductive connection material CN. For the conductive connection material c N, for example, a BGA (ball grid array) is used. The base substrate and the semiconductor integrated circuit are passed through the plug τ p and the conductive connection material CN. Signals are transmitted and received between wafers and between semiconductor integrated circuit wafers. Fig. 1B shows a second configuration example of a multilayer semiconductor device according to an embodiment of the present invention. A plurality of semiconductor integrated circuit wafers si to S5 are stacked on a base substrate BS. The base substrate BS functions as a mother board and is provided with terminals tm and wiring patterns or power sources (not shown). Semiconductor integrated circuit wafers S1 to S5 are mounted on the substrates SB A1 to SB A5. The substrates SBA1 to SBA5 are provided with terminals for electrically connecting the semiconductor integrated circuit wafers S1 to S5 and wirings (not shown) through the plug τρ described later. The substrates SBB1 to SBB5 are interposed between the base substrate BS and the lowermost substrate SBA1 And the adjacent substrates SB / U to SBA5. A hole is formed in the center of the substrates SBB1 to SBB5, and the semiconductor integrated circuit wafers S1 to S5 are arranged corresponding to this hole. The substrates Sgl to SBA5 and the substrates SBB 1 to SBB5 are provided The through-plugs TP made of a conductive material penetrating these substrates. The terminal TM of the base substrate 68 and the lower-layer through-plug τρ and the adjacent through-plug τρ are connected by a conductive connection material CN. About the conductive connection Material cn, example -7-

503531 A7

If using solder. Birds are interspersed through f. ^ ^ I Sequentially pushes STP, conductive connection material CN, and wiring (not shown) with j = BA1 ~ SBA5 to signal between the base substrate and the semiconductor chip and between the semiconductor chip and the circuit chip Send and receive. — · 4 丨 As shown in FIG. 1A, the semiconductor integrated circuit wafers (S1 to S5) are directly connected to each other using through-plugs, and the semiconductor integrated circuit wafer itself corresponds to the semiconductor integrated circuit device. In addition, for example, as shown in FIG. 1B, the substrates (SBA1 to SBA5) on which the semiconductor integrated circuit wafers (S5 to S5) are mounted are connected through the plugs, and the semiconductor integrated circuit wafers (for example, s) and the substrates are used. The wafer-attached substrate (for example, sbai) corresponds to a semiconductor integrated circuit device. With regard to such a wafer substrate, the specifications of the semiconductor integrated circuit device may be the specifications of the semiconductor integrated circuit wafer itself or the specifications of the wafer substrate. In other words, the semiconductor integrated circuit device may be a semiconductor integrated circuit wafer or a device containing a semiconductor integrated circuit wafer and other components (substrates, etc.). In addition, the specifications of a semiconductor integrated circuit device may be the specifications of a semiconductor integrated circuit chip (Qing Shen), or the specifications of a device containing a semiconductor integrated circuit chip and other components (substrates, etc.) (Qing Shen 2 Bu is below) In order to simplify the description, the case 1 is described, but the same applies to the case 2. Hereinafter, the basic method of the lamination method of the multilayer semiconductor device according to this embodiment will be described. (Type 1 ) This type is a stack of at least three or more in accordance with the order of size and size. -8- This paper size applies to Chinese National Standard (CNS) A4 size (210 X 297 mm) A7 B7 V. Description of the invention (6) Semiconductor Circuit wafer σ Figures 2A and 2B show an example of this type. The horizontal axis is the stacking order of the semiconductor chip% circuit S1 to S: > and the vertical axis is the specifications of each semiconductor chip circuit chip S1 to S5.値 (power consumption, etc.). In the example of Figure 2A and 2B, the specifications 値 increase or decrease in the laminated range of wafers S2 to S4, but of course, in a stacked range of four or more layers, the size 値 can also increase. or Reduced. Figure 3A and Figure 3B show other examples of this type. In this way, two or more wafers with the same specifications (S 3 and s 4 in the illustration) can be adjacent to each other. That is, even if there are a large number of the same specifications, In the range of at least two stages or more, the specifications can also be increased or decreased. Figure 4A and Figure 4B show other examples of this type. This example includes the lowest wafer S1 and the uppermost wafer in three or more predetermined wafers. An example of at least one of the wafers S. The predetermined wafers above and above the legend '3 all include S 1 and s 5 and the specifications 値 increase or decrease in the full lamination range. Also, it can be as shown in the garden 3 A and FIG. 3 B Figure 5 shows the same type of wafers adjacent to each other. Figure 5 A and country 5 B mode show other examples of this type. This example is an example where three or more scheduled wafers do not include at least one of the lowermost wafer S1 and the uppermost wafer S5. In the legend The wafer S 3 whose specification 値 becomes the largest or smallest becomes other than the lowermost wafer S 1 and the uppermost wafer s 5. In addition, as shown in FIG. 3A and FIG. 3B, wafers of the same specification 邻接 may be adjacent. FIG. 6 Modes A and B show other examples of this type. This example is on a scheduled chip An example in which a specific wafer is sandwiched. In the illustration, the specifications of the specific wafer S 3 are larger or smaller than those of the wafers S 2 and S 4 adjacent to the two sides of the wafer S 3. About the wafers S 1, S 2 other than the specific wafer s 3 S 4 and S 5, the specifications 値 increase or decrease. Each paper size applies the Chinese National Standard (CNS) A4 specifications (210X297 mm) 503531 A7 _B7 _, V. Description of the invention (7) (Type 2) This type is Among the semiconductor integrated circuit wafers with a full lamination range, the specification of the lowest or uppermost semiconductor integrated circuit wafer 値 becomes the smallest or largest. The total number of stacked semiconductor semiconductor circuit wafers is two or more. The 7A and 7B modes show an example of this type. In the example shown in the figure, the specification 値 of the lowermost wafer S1 becomes the smallest or largest, but of course the specification 上 of the uppermost wafer S5 may also become the smallest or largest. When the specification 値 of the lowermost wafer S1 is the smallest (or the largest), the wafer having the smaller (or larger) specification may be used as the uppermost wafer S5. Conversely, when the specification 値 of the uppermost wafer S 5 is the smallest (or the largest), the wafer with the smaller (or larger) specification 値 may be used as the lowermost wafer S 1. In addition, when there are many types of wafers with the smallest or largest wafers, these wafers can also be arranged on the lowermost layer and the uppermost layer. Figures 5A and 5B are examples of this type, which is also equivalent to this type. ‘(Type 3) This type forms a group with each other within a predetermined range based on specifications, and successively stacks at least two or more semiconductor integrated circuit wafers included in the group. Figure 8 shows an example of this type. In the example shown in FIG. 8, the wafers S1 and S2, the wafers S3 and S4, and the wafers S5 and S6 constitute a group, respectively. In the example shown in Fig. 8, although the number of wafers included in one group is two, the number of wafers may be three or more. The number of wafers included in each group may be different. Furthermore, the wafers may not exist in any group. (Type 4) This type is one or two of most semiconductor integrated circuit wafers. -10 · This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 503531 A7 — one ____ B7 5. Description of the invention (8) The specific semiconductor integrated circuit wafer is arranged at a predetermined stacking position. Figure 9 mode shows an example of this type. In this example, a specific semiconductor integrated circuit wafer is successively laminated in most wafers (the examples shown in FIG. 9 are S2 and S3). Typically, specific wafers with the highest signal transmission and reception amount among each other among all the wafers are stacked consecutively. In addition, the specifications can be stacked consecutively, the nearest one to another (this is also included in the grouping concept of type 3). Figure 10 mode shows another example of this type. In the illustration, among all the wafers, the wafer Si having the largest amount of signal transmission and reception to and from the base substrate BS is arranged closest to the base substrate BS. The concept shown in FIG. 10 is also included in the concept of type 2. Country 1 1 mode shows this type of exception. In the example, among all the wafers, the wafer s 5 having the largest amount of signal transmission and reception with the outside is arranged at a position farthest from the base substrate B s. Also, the concept shown in FIG. 1 丨 is also included in the concept of type 2. In terms of the above-mentioned types, the semiconductor integrated circuit chip specifications include power consumption, operating voltage, number of operating voltages, operating current, guaranteed operating temperature, amount of generated electromagnetic waves, operating frequency, size, number of connection terminals, The connection terminal pitch, thickness, and the amount of signal transmission / reception with the base substrate on which the semiconductor integrated circuit wafer is mounted and the amount of signal transmission / reception with the outside. As described above, by optimizing the lamination method of a semiconductor integrated circuit wafer, a laminated semiconductor device having good performance can be obtained. In addition, the 'on-I stacking method is effective for a stacked semiconductor device such as that shown in FIG. 1A or FIG. 1B which uses a through-plug to electrically connect adjacent wafers. For example, when wire bonding is used for electrical connection between wafers, from the viewpoint of ease of wire bonding, for example, there are small wafers on large wafers. 11- This paper is in accordance with Chinese national standard (〇 recommended) 8 4 '袼 (21〇 \ 297mm) _ 503531 A7 ___ B7__ 5. The description of invention (9) is based on the chip size limitation. Therefore, it is considered that there is little degree of freedom in the wafer lamination method. When the electrical connection between the wafers is made by through-plugs, there are no restrictions as described above. For example, the configuration example shown in FIG. 1C can be used. Therefore, according to specifications other than the wafer size, various lamination methods described above can be applied. Hereinafter, a specific method of stacking semiconductor integrated circuit wafers for each specification will be described. In addition, the lamination method described in the following specific examples is _ Example 'Basically, various lamination methods described in the above types can be used. (Specific Example 1) In this example, the wafers are stacked according to the power consumption of the semiconductor integrated circuit wafers s 1 to S5 (for example, taking a large power consumption). When stacking many chips that integrate different functions, it is necessary to consider the power consumption of each chip, in other words, to consider the heat flow generated in each chip to dissipate (cool) the entire module. Then, the following specific example 1 A or specific example 1 B was prepared, and each wafer was laminated. (Specific Example 1 A) In this example, wafers are sequentially stacked in order from the direction of heat diffusion and propagation, from wafers that consume a large amount of power, that is, a large amount of heat. For example, each wafer is laminated as shown in FIG. 4β. In addition, by arranging a chip that consumes a lot of power on the base substrate BS side, that is, a heatsink side, the wafer that consumes a lot of power can be quickly discharged to the heat sink. In other words, the temperature of a chip that consumes a lot of power can be quickly reduced. Therefore, the heat of the chip that consumes less power can be efficiently released to the heat sink, and the entire module can be efficiently radiated (cooled). The heat sinks are arranged on both sides of the wafer (the side of the wafer 81 and the "side of the wafer -12 ·"

A7

Description of the invention (10: Second, for example, each wafer can be layered as shown in Fig. 5B. Others in this example, for example, each wafer is laminated as shown in Fig. 2B, Fig. 3B, Fig. 6B, Fig. 7B, etc. (Specific Example 1 B) For the direction of heat diffusion and propagation, the wafers are sequentially stacked from the wafer with less power consumption. For example, the wafer is formed as shown in FIG. 4A, and the stacking: crystal Xiao: ¾ Lixi wafer exists on the base substrate. Power-consuming customers 'Zhuanggu, and Xi's wafers sometimes function as a barrier to heat diffusion (-----). Therefore,' there is a risk that heat diffusion from a chip that consumes less power to a heat sink will be hindered. In this example, a wafer with a large power consumption and a low power consumption does not become an obstacle to heat diffusion because the wafer with a large power consumption is disposed on the base substrate B s side. A wafer with a large power consumption to a small wafer may even dissipate heat due to the gradient; Diffusion can effectively dissipate (cool) the entire module. In addition, when the heat sinks are arranged on both sides of the wafer (the wafer s 丨 side and the wafer s 5, for example, it can also be shown in Figure 5 八层 # various crystals. In this example, for example, layers such as FIG. 2A, FIG. 38, FIG. 6A, and FIG. 7 Each wafer. (Specific example 2) In this example, the wafers are stacked according to the operating voltage (power supply voltage) or the number of operating voltages (power supply voltage) of the semiconductor integrated circuit wafers S1 to S5. In some cases, the operating voltage or number of operating voltages of each chip may be different. In this case, it is necessary to stack the chips in consideration of a voltage drop or connection to a power source. Therefore, the following specific examples are prepared: A: Specific example 2 D stacking Each chip. -13-

503531 A7 B7 V. Description of the invention (correction (specific example 2 A)) This example is to stack wafers in order from a wafer with a high operating voltage (power supply voltage). For example, as shown in Figure 4B, each wafer is stacked. Most operating voltages exist in one wafer. For example, when the maximum operating voltage is used as a reference, the operating voltages of the wafers are compared. When supplying voltage to each wafer from the base substrate, that is, the power supply substrate, the voltage is supplied to the wafers farther away from the power supply through the midway wafer. Generally, the operating voltage is low. The chip's allowable operating voltage is also low. Therefore, if the operating voltage of the chip is low in the middle of the voltage supply path, it will lead to erroneous operation or damage such as damage. # In this example, a high operating voltage is placed on the base substrate BS side. Therefore, the power supply from the base substrate does not supply a voltage higher than the operating voltage of the halfway wafer to the halfway wafer serving as a voltage supply path. Therefore, it is possible to prevent a malfunction such as malfunction or damage from decreasing. Also, the power supply board is disposed on For both sides of the wafer (side of wafer si and side of wafer s 5), for example, each wafer may be stacked as shown in FIG. 5B. Embodiment, may be for example FIG. 2B, FIG. 3B, FIG. 6B, 7B and the like are stacked each wafer. (Specific Example 2 B) two movable

f W π In the chip ② If the maximum operating voltage is used as a reference ', the operating voltages are compared. When supplying voltage to each wafer from the base substrate, that is, the power supply substrate, the wafer on the far side is longer because the voltage supply path is longer than the wafer near the power source. This example is to stack the wafers sequentially from the wafer with the lower operating voltage (power supply voltage). For example, each wafer is laminated as shown in FIG. 4A. In addition, most of the operating voltages exist in Yuan Yi. 14- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male sauce) A7

The more wafers the more wafers. Affects that voltage can be generated. In this example, the lower the operating voltage, the lower the operating voltage is. In this example, the lower operating voltage is placed on the base substrate B S side. When viewed as a whole, the voltage drop can be reduced to improve reliability. Furthermore, the power supply substrates are arranged on both sides of the wafer (the wafer chip and the §5 side of the wafer). For example, each wafer can be stacked as in the country 5A. In this example, for example, each wafer may be stacked as shown in FIG. 3A, FIG. 6A, and FIG. 7A. (Specific example 2C) This example is when the number of operating voltages (power supply voltage) of each chip is different, for example, when a wafer with a private operation pressure and a wafer with two operating voltages have a higher operating voltage It is arranged on the base substrate BS side, that is, on the power substrate side. For example, the wafers are stacked as in the country 4β.

In this way, by arranging the wafers with a high voltage number on the base substrate BS T ', that is, on the power substrate side, it is possible to reduce the number of through-plugs that are packed to each wafer in order to supply power from the base substrate β s. Because of &, it is possible to reduce the processing cost or improve the reliability. — When the power supply substrate is arranged on both sides of the wafer (the wafer s 丨 side and the wafer s 5 side), for example, each wafer may be inked as shown in FIG. 5. In this example, the wafers may be stacked, for example, as shown in FIG. 2B, FIG. 3B, FIG. 6 and FIG. 7β. (Specific example 2D) The main example is to use a wafer with a single operating voltage to form a module or the like to form a plurality of wafers with operating voltages close to or the same as each other, and continuously stack the wafers in the cluster. Each wafer is stacked, for example, as shown in FIG. 8. For example, by forming a group of chips with the same operating voltage, the power supply terminals A7 and B7 can be made common, and the number of through-plugs for identifying each chip in order to supply the power supply voltage from the base substrate BS can be reduced. Because & ’can reduce processing costs: increase. / Non-specific (Specific Example 3) This example is based on the semiconductor power supply chips S1 to S5 of each chip. · 'When the operating current of each wafer is different, consider the operating current of each wafer and stack each wafer. Then, each wafer is laminated as follows. In this example, when the operating current of each wafer is different, each wafer is layered in the order of the larger operating current (for example, a large defect roll). For example, as shown in FIG. 4B, a 夂 wafer is stacked. When supplying current to each wafer from the base substrate, that is, the power substrate, if the wafer is far from the power substrate, the current supply path is longer than the wafer near the power substrate. Therefore, the resistance component of the wafer farther from the power substrate in the current supply path becomes larger. If a chip with a large operating current is placed on a chip far away from the power source, the voltage loss increases from the relationship of voltage = current × resistance. In this example, a wafer with a large operating current is placed on the base substrate BS side, that is, a power substrate side, that is, a wafer with a large operating current is placed at a position where the resistance component of the current path becomes small, so that the voltage loss can be suppressed to a minimum. . When the power supply substrates are arranged on both sides of the wafer (the wafer S 1 side and the wafer S 5 side), for example, the wafers are stacked in the same manner as the country 5B. In this example, the wafers may be stacked as shown in FIG. 2B, FIG. 3B, FIG. 6B, and country 7B. (Specific example 4) This example is based on the guaranteed operating temperature of the semiconductor integrated circuit wafers S1 to S5. -16- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) A7

Each wafer is stacked. When a large number of wafers are stacked and modularized, it is necessary to consider the guaranteed operating temperature of each wafer ^ (standard for reliability) to ensure the reliability of the entire module. Then, the following layers ® each wafer. In this example, when the guaranteed operating temperature between the day and day # is different, the wafers in the group are continuously stacked by clustering the guaranteed operating temperatures or the same wafers, to ensure the reliability standard. For example, it corresponds to the concept of FIG. 8. [It is also possible to arrange the wafer with the lowest guaranteed operating temperature at the lamination position where the temperature becomes the lowest (the lamination position where the temperature is designed to be the lowest). In addition, the guaranteed operating temperature of the entire module and the chip reference with the lowest guaranteed operating temperature can be set to 0. In this way, by stacking the wafers in consideration of the guaranteed operating temperature, the reliability of the entire module can be ensured (long life). Etc.), by bringing wafers with similar guaranteed operating temperatures close to each other, reliability management is easy. (Specific example 5) In this example, the respective chips are stacked according to the signals of the semiconductor integrated circuit wafers 81 to ^. When a large number of chips are stacked and modularized, if signal transmission and reception such as signal transmission / reception speed and signal transmission / reception speed are not taken into consideration, there is a possibility that the function of the module may be reduced or malfunction due to signal delay. Then, the following specific examples 5A to 5C multilayer disks were fabricated. ', (Specific Example 5A) In this example, specific wafers having the closest relationship are arranged next to each other. That is, as shown in Figure 9, the specific wafers with the closest relationship (example in Figure 9 -17- this paper size applies Chinese National Standard (CMS) A4 specification (210 X 297 mm) m binding

503531 A7 __Β7 V. Description of the invention (15 ~ " for S2 and S3) Zheng Zheng configuration. For example, the chips that transmit and receive the most signals between each other are placed next to each other. Specifically, a logic chip having a signal processing function and a memory chip (a cache chip such as a DraM or SRAM) that transmits and receives data to and from the logic chip are stacked next to each other. On the other hand, a chip that does not transmit and receive signals, such as a power control chip, is arranged at a remote location. If other chips are interposed between the chips transmitting and receiving data, the processing speed will be slowed due to signal delay, and the overall system function will be reduced. By arranging the chips as described above adjacently, the processing speed is increased, and the overall system function can be improved. In addition, when transmitting and receiving signals between each other, the chips with the closest operating frequency may be arranged adjacent to each other. In this way, the timing deviation during data transmission and reception can be minimized, and the overall system function can be improved. (Specific example 5B) In this example, a chip (for example, a signal processing chip that processes high-speed signals) that is most frequently transmitted and received to and from a mother board that becomes an interface substrate is disposed adjacent to the mother board. That is, as shown in FIG. 10, the chip 81, which has the most signal transmission and reception with the motherboard (base substrate BS), is arranged adjacent to the motherboard. Therefore, when transmitting and receiving signals with the motherboard, the signal delay can be minimized, and the overall system function can be improved. (Specific Example 5C) In this example, as shown in FIG. 11, for example, the chip S5 that transmits and receives a large amount of signals to and from the outside is arranged at a position farthest from the mother board (base substrate BS). For example, a chip that processes external signals such as video signals, sound signals, and antenna signals from a CCD or CMOS sensor is placed on the top layer. With this configuration I, the CCD or -1 8- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) A7 -------___ 57 V. Description of the invention (16) ~ ^ ^ Antenna When it is set above the wafer S5, it will not be shielded by other wafers S1 to S4. The signal can be transmitted and received between the wafer S5 and the outside. (Specific example 6) In this example, the wafers are stacked according to the amount of electromagnetic waves generated by the semiconductor integrated circuit wafers si to s5. When a large number of wafers are stacked and modularized, as the signal transmission / reception 1 between the wafers increases or the signal speeds up, the operating voltage also decreases. Therefore, each wafer is easily affected by noise. In other words, there is a possibility that an erroneous operation, sound, or image disturbance may occur due to electromagnetic interference (EMI) caused by electromagnetic waves generated from each chip, power line, ground line, and the like. Then, specific wafers 6A and 6B were prepared as described below. (Specific example 6A) In this example, a wafer with a large amount of electromagnetic wave generation is arranged near the mother board. For example, as shown in Fig. 7B, the wafer s 1 with the largest amount of electromagnetic waves is placed closest to the base substrate BS. Conversely, a wafer with a small amount of electromagnetic wave generation can be arranged at a position farthest from the base substrate. For example, the chip that generates the largest amount of electromagnetic waves (such as a chip with a large operating current flowing instantaneously with a large current, a sensor chip, audio, image processing chip, and a chip that processes antenna signals for transmission and reception) is placed closest to the base substrate. Position, the wafer which is easily affected by the electromagnetic wave is arranged away from the base substrate. With this configuration, it is possible to suppress the electric-acoustic-magnetic waves from the chip S1 from affecting the other chips S2 to S5, and to prevent erroneous operation due to the electromagnetic waves. 、 _ Type 2 __ -19- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X 297 mm) 503531 A7 B7 5. The various lamination methods described in the invention description (17) laminated each wafer. (Specific Example 6B) In this example, a wafer that is easily affected by electromagnetic waves is placed at a position farthest from the mother board (base substrate) according to Type 2, for example. In this way, a wafer (for example, a sensor wafer, a sound, an image processing wafer, and a wafer that processes antenna signals for transmission and reception) that is easily affected by electromagnetic waves is placed on a power substrate (base substrate) that is a source of EMI and the like. The remote stacking position prevents malfunction due to electromagnetic waves. (Specific example 7) In this example, the wafers are stacked according to the wafer size of the semiconductor integrated circuit wafers S1 to S5. The wafers of the stacked layers are not necessarily the same size, and wafers of various sizes are sometimes mixed and stacked. As described above, when various wafer sizes are mixed, if the stacking order of the respective wafers is not appropriate, problems such as stress cracking, connection failure, and increase in manufacturing cost may occur. One-body stacked modules are generally high-function and high-density, so the number of connection terminals between the module and the outside is very large. As for the package of such a module, a connection called a flip chip in which the connection terminals are arranged in a grid is used. In addition, for the motherboard or package, resins such as epoxy glass are often used from the viewpoint of weight or price. This resin has a coefficient of thermal expansion of five times that of semiconductors such as silicon or gallium arsenide, so stresses with different coefficients of thermal expansion will occur between the two. In the case of a three-dimensional laminated module, compared with a flat module in which each chip is arranged in a horizontal direction, the terminal pitch is sharpened and the connection between the motherboard and the chip becomes more difficult. »20- This paper size applies the Chinese National Standard (CMS) A4 specification (210X 297 mm) 503531 A7 B7 V. Description of the invention (18) ^ From this point of view, in this example, as shown in Figure 7B, for example, The wafer S1 having the largest wafer size is arranged at a stacking position closest to the base substrate BS (mother board). As a method for determining the wafer size, the following methods can be mentioned. (Specific example 7A) In this example, the wafer size is determined based on the length of each wafer long side (the rectangular long side when the wafer surface perpendicular to the stacking direction is a rectangle, but the wafer side is an arbitrary side when the wafer surface is a square). The longest-length wafer is placed closest to the base substrate (motherboard). (Specific Example 7B) In this example, according to the length and short side of each wafer long side (the rectangular long side when the wafer surface perpendicular to the lamination direction is a rectangle, but the wafer side is an arbitrary side when the wafer surface is a square) (The rectangular short side when the wafer surface perpendicular to the stacking direction is a rectangle, but if the wafer surface is a square, it is an arbitrary side.) The sum of the lengths is used to determine the wafer size, and the length and the largest wafer are placed closest to the substrate. Location of the substrate. (Specific Example 7C) In this example, the wafer size was determined based on each wafer area (the area of the wafer surface perpendicular to the lamination direction), and the wafer with the largest area was placed closest to the base substrate. As described above, in this example, by sequentially stacking the wafers from the one with the larger wafer size, it is possible to suppress connection failure due to stress and improve the reliability of the entire module. In addition, in this specific example 7, the wafers may be laminated according to various lamination methods as described in type 1 and type 2. (Specific example 8) -21- This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

Installation 5. Description of the Invention (19) In this example, the wafers are stacked according to the number of connection terminals or the distance between the connection terminals of the semiconductor integrated circuit wafers S1 to S5. Each of the stacked wafers is connected to each other by a connection terminal such as a through-plug, or between the wafer and a mother board (base substrate). However, the number of terminals or terminal pitches of the stacked wafers are not necessarily the same, and many wafers with various terminal numbers or terminal pitches are mixed and stacked. As described above, when various terminal numbers or terminal pitches are mixed, if the stacking order of the respective wafers is not appropriate, problems such as stress cracking, poor connection, and increased manufacturing cost may occur. That is, the same problem as described in Specific Example 7 occurs. In addition, the number of terminals for transmitting and receiving signals to and from the motherboard also varies according to each chip. Without proper selection of the stacking order ', the effective arrangement of each chip or the performance of the entire module cannot be improved. From this point of view, in this example, the following specific examples 8 A and 8 B are laminated on each wafer. (Specific Example 8 A) In this example, for example, as shown in FIG. 7B, the wafer S1 having the largest number of terminals is arranged closest to the base substrate BS (motherboard). More specifically, the chip having the largest number of terminals connected to the mother board is arranged at the stacking position closest to the mother board. With such a configuration, effective connection can be performed, and the performance of the entire module can be improved. (Specific example 8B) In this example, as shown in country 7B, the chip with the widest terminal pitch is arranged closest to the motherboard. From the viewpoint of the number of terminals, the chip with the least number of terminals is arranged closest to the motherboard. With this arrangement, the stress between the motherboard and the wafer can be reduced. Therefore, a highly reliable connection is possible, so -22- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7

This improves the reliability of the entire module. In this specific example 8, the wafers may be laminated according to a lamination method of type 1. (Specific example 9) Each of the examples described in Type 2 is based on the semiconductor integrated circuit wafer. Wafer thickness stacking from S1 to S5 The thicknesses of the stacked wafers are not the same. Most wafers of various thicknesses are stacked together. In this way, when the thicknesses of various wafers are mixed, if the order of the layers of the bribes is not appropriate, problems such as stress cracking and poor connection may occur. In other words, the three-dimensionally stacked modules are designed for high functionality and high density. Therefore, it is desirable to make the thickness of each wafer as thin as possible, but if the thickness of the wafer is too thin, the strength of the wafer becomes weak. Therefore, there is a problem that the reliability of the entire module is lowered. From this point of view, in this example, the following specific examples 9A and 9B are used. (Specific Example 9 A) In this example, for example, as shown in FIG. 7B, the wafer S 1 having the thickest wafer thickness is arranged closest to the base substrate BS (mother board). The absolute yield stress (strength) for a load such as bending or stress is proportional to the thickness', so a thick wafer is generally strong. The three-dimensionally stacked module has the highest thermal expansion coefficient due to the different thermal expansion coefficients described above. Therefore, by arranging the thickest chip on the motherboard side, the strength of the entire module is improved, and a three-dimensional module with high reliability can be obtained. (Specific Example 9 B) For this example, as shown in country 7 A, the wafer with the thinnest wafer thickness is arranged at the most. -23- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Binding% 503531 A7 B7 5. Description of the invention (21) The position close to the base substrate (motherboard). As mentioned earlier, the absolute value of the yield stress (strength) is proportional to the thickness, but it is better for the displacement of stress, that is, the degree of easy bending. In the case of a wafer which is easily bent, that is, a thin wafer ', the wafer itself is difficult to break due to the flexibility of the wafer itself, even if the stress acts between the wafer and the motherboard. Therefore, the strength of the entire module is improved, and a highly reliable three-dimensional module can be obtained. In addition, in this specific example 9, each wafer may be laminated according to various lamination methods described in Type 1 and Type 2. (Specific Example 10) In this example, the wafers are arranged in consideration of the positional relationship of the wafers of the semiconductor integrated circuit device. As described above, the sizes of the stacked wafers are not necessarily the same, and many wafers of various sizes are mixed and stacked. As described above, when various wafer sizes are mixed, if the lamination method of the respective wafers is not appropriate, effective arrangement cannot be performed. In this example, a large number of small wafers are sandwiched between large wafers. FIG. 12 is a diagram showing an example thereof. The symbols are the same as those in FIG. 1A. As shown in FIG. 12, a large-size wafer is arranged at the positions of the wafers S1 and S3, and a large number of the small-size wafers S2 are arranged at the positions between the wafers S1 and S3 in the horizontal direction (on the same plane). With this arrangement, each chip can be arranged at a high density, and a high-performance module can be obtained. 'Voice Additional advantages and variants will be easily conceived by those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific illustrations and representative specific examples shown and illustrated herein. Therefore, it is incomparable to make a departure from the additional application patents • 24-503531 A7 B7 5. The general invention concept, spirit or model, which is limited by the scope of the invention description (22) and its equivalent claims, can be modified in various ways. -25- Chinese paper standard (CNS) A4 (210 X 297 mm)

Claims (1)

503531 A8 B8 C8 D8 6. Application for Patent Scope 1. A laminated semiconductor device, characterized in that it is a laminated semiconductor device comprising a plurality of semiconductor integrated circuit devices including a single-conductor chip circuit chip and having specifications, as described above. At least three or more predetermined semiconductor integrated circuit devices among the semiconductor integrated circuit devices are stacked in the order of the aforementioned specifications and sizes. 2. The laminated semiconductor device according to item 1 of the patent application, wherein the semiconductor integrated circuit device further includes a substrate, and the semiconductor integrated circuit wafer is mounted on the substrate. 3. The laminated semiconductor device according to item 1 of the patent application, wherein the aforementioned specifications are the aforementioned specifications of the semiconductor integrated circuit wafer. 4. The #layer semiconductor device according to item 1 of the patent application scope, wherein the aforementioned predetermined semiconductor integrated circuit device is continuously stacked. 5. The laminated semiconductor device according to item 1 of the patent application park, wherein the predetermined semiconductor integrated circuit device is laminated with a semiconductor integrated circuit device other than the predetermined semiconductor integrated circuit device. 6. The stacked semiconductor device according to item 1 of the patent application park, wherein the predetermined semiconductor integrated circuit device includes at least one of the lowermost layer and the uppermost semiconductor integrated circuit device of the semiconductor integrated circuit device. 7. The laminated semiconductor device according to item 1 of the application, wherein adjacent semiconductor integrated circuit devices are electrically connected to each other by a conductive material penetrating the semiconductor integrated circuit device. 8. For the laminated semiconductor device according to item 1 of the scope of patent application, the aforementioned specifications are based on power consumption, operating voltage, number of operating voltages, operating current, guaranteed operating temperature, amount of electromagnetic waves generated, operating frequency, size, -26- This paper size applies to Laos National Standard (CNS) A4 (210 X 297 mm) 503531 A8 B8 C8 The amount of signals to be transmitted and received with the above-mentioned semiconductor quantity and external signals, the number of connection terminals, the distance between the connection terminals, the thickness, and the base substrate of the integrated pen circuit device are selected. 9. A stacked semiconductor device, characterized in that it is a stacked semiconductor device that includes at least two or more semiconductor integrated circuit devices that include semiconductor integrated circuit wafers and has specifications, ^ In the aforementioned semiconductor integrated circuit device, The specification of the lowermost or uppermost semiconductor integrated circuit device is the smallest or largest. 10. The laminated semiconductor device according to item 9 of the patent application park, wherein the semiconductor integrated circuit device further includes a substrate, and the semiconductor integrated circuit wafer is mounted on the substrate. 11. The laminated semiconductor device according to item 9 of the application, wherein the aforementioned specifications are those of the aforementioned semiconductor integrated circuit wafer. 12. The laminated semiconductor device according to item 9 of the application, wherein the adjacent semiconductor integrated circuit devices are electrically connected to each other by a conductive material penetrating the front semiconductor integrated circuit device. 13. For the laminated semiconductor device according to item 9 of the scope of patent application, the foregoing specifications are based on power consumption, operating voltage, number of operating voltages, operating current, guaranteed operating temperature, amount of electromagnetic waves generated, operating frequency, size, and number of connection terminals , The connection terminal pitch, thickness, and the amount of signal transmission and reception and the amount of external signal transmission and reception of the base substrate on which the semiconductor integrated circuit is mounted. 14 · A laminated semiconductor device 'characterized in that at least two or more semiconductor integrated circuits including semiconductor integrated circuit wafers are stacked, and this standard is applicable to Chinese National Standard (CNS) A4 (210X297) (Mm) 503531 A BC16. Patent-preferred stacked semiconductor devices with circuit devices. • Adjacent semiconductor integrated circuit devices are electrically connected to each other by conductive materials that penetrate the semiconductor integrated circuit devices. In the bulk circuit device, the specifications other than the size of the lowermost layer or the uppermost semiconductor integrated circuit device are the smallest or the largest. 15. The laminated semiconductor device according to item 14 of the application, wherein the semiconductor integrated circuit device further includes a substrate, and the semiconductor integrated circuit wafer is mounted on the substrate. 16. The laminated semiconductor device as claimed in claim 14 in which the aforementioned specifications are those of the aforementioned semiconductor integrated circuit wafer. 17. The laminated semiconductor device according to item 14 of the application, wherein the conductive material penetrates the semiconductor integrated circuit wafer or the substrate on which the semiconductor volume circuit wafer is mounted. 18. For the laminated semiconductor device of item 14 in the scope of patent application, the foregoing specifications are based on power consumption, operating voltage, number of operating voltages, operating current, guaranteed operating temperature, amount of electromagnetic waves generated, operating frequency, number of connection terminals, The connection terminal pitch, thickness, and signal transmission / reception amount of the base substrate on which the semiconductor integrated circuit device is mounted and external signal transmission / reception amount are selected. 19. A stacked semiconductor device, characterized in that it is a stacked semiconductor device comprising a plurality of semiconductor integrated circuit devices including semiconductor integrated circuit wafers and having specifications, wherein the stacked semiconductor device includes a semiconductor integrated circuit A group consisting of a predetermined number of specific semiconductor integrated circuit devices in the circuit assembly, -28- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) A8 B8 C8 D8 503531 6. The scope of the patent application is more than two and the number of booths of the semiconductor integrated circuit device is smaller than the number of booths of the aforementioned semiconductor integrated circuit device. &Quot; The specifications of the aforementioned specific semiconductor integrated circuit device are all within the predetermined range and the aforementioned specific semiconductor integrated circuit device is within the predetermined range. The circuit device is continuously stacked. 20. The laminated semiconductor device according to item 19 of the application, wherein the aforementioned semiconductor integrated circuit device further includes a substrate, and the aforementioned semiconductor integrated circuit wafer is mounted on the aforementioned substrate. 21. The laminated semiconductor device according to item 19 of the application, wherein the aforementioned specifications are the specifications of the semiconductor integrated circuit wafer. 22. For the laminated semiconductor device of the 19th in the scope of application for a patent, in which the aforementioned laminated half-cell device has? Counting the aforementioned groups, the aforementioned predetermined ranges are different from each other among the groups. 23. The laminated semiconductor device according to the item No. 9 of the patent application range, in which the specific semiconductor integrated circuit devices are closest to each other in the laminated semiconductor device. 24. The laminated semiconductor device according to claim 19, wherein the adjacent semiconductor integrated circuit devices are electrically connected to each other by a conductive material penetrating the semiconductor integrated circuit device. 25. The laminated semiconductor device according to item 19 of the application, wherein the aforementioned specifications are based on power consumption, operating voltage, number of operating voltages, operating current, guaranteed operating temperature, amount of generated electromagnetic waves, operating frequency, size, and connection terminals. The number, the connection terminal pitch, the thickness, and the amount of signal transmission / reception with the base substrate on which the semiconductor integrated circuit device is mounted and the amount of signal transmission / reception with the outside are selected. -29- This paper size applies to China National Standard (CNS) A4 (210 X 29? Mm) Binding 503531 A8 B8 C8 D8, patent application range 26.-A stacked semiconductor device, characterized in that it is a stacked semiconductor device in which a plurality of semiconductor integrated circuit devices including semiconductor wafers are stacked. Among the circuit devices, specific semiconductor integrated circuit devices having the largest amount of signal transmission / reception between each other are continuously stacked. 27. A multilayer semiconductor device, comprising: a first semiconductor integrated circuit device: including a semiconductor integrated circuit wafer and mostly provided on the same plane; and, a majority of the second semiconductor integrated circuit device: including a semiconductor An integrated circuit chip that sandwiches most of the aforementioned first semiconductor integrated circuit devices. -30- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)