CN216902914U - A silicon-based substrate and chip - Google Patents

Abstract

The embodiment of the utility model discloses a silicon base substrate and a chip, which relate to the technical field of semiconductor packaging, and are convenient for effectively taking into account short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon base substrate. The silicon-based substrate includes: a substrate body, wherein at least two via holes are provided in the substrate body, the at least two via holes include at least one first via hole and at least one second via hole, the first via hole is The cross-sectional area of the hole is larger than the cross-sectional area of the second via hole; wherein, the first via hole is used for electrically connecting the first metal wire arranged in the substrate body, and the second via hole is used for electrical connection A second metal wire arranged in the substrate body is electrically connected, and the cross-sectional area of the first metal wire is larger than the cross-sectional area of the second metal wire. The utility model is suitable for chip packaging.

Description

A silicon-based substrate and chip

technical field

The utility model relates to the technical field of semiconductor packaging, in particular to a silicon base substrate and a chip.

Background technique

With the miniaturization, integration, and intelligence of electronic products, the complexity and the number of chips used have increased significantly, and the complexity of chip packaging has also become higher and higher. In chip packaging, the interconnection between different pins of a single die or between multiple dies can usually be realized through a silicon wafer and an organic substrate.

For the above-mentioned interconnection through silicon wafers, dense metal thin lines (usually the line width is less than 1um (micrometer) and the line height is less than 1um) are usually used as interconnection lines, and the silicon wafers are connected by arranging fine vias in the silicon wafer. Thin metal wires in different layers. These vias are generally small in size and uniform in distribution, which not only facilitates the realization of high-density, large-bandwidth, short-distance signal transmission between chips, but also facilitates the control of the manufacturing process.

However, although this via and interconnect structure can effectively support short-distance signal transmission, it will lead to loss of signal integrity in long-distance, high-speed signal transmission, making the signal at the receiving end inconsistent with the original transmitting end, resulting in chip function errors .

Utility model content

In view of this, embodiments of the present invention provide a silicon-based substrate and a chip, which are convenient for effectively taking into account short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon-based substrate in chip packaging.

In a first aspect, an embodiment of the present invention provides a silicon-based substrate, comprising: a substrate body, wherein at least two via holes are provided in the substrate body, the at least two via holes include at least one first via hole and At least one second via hole, the cross-sectional area of the first via hole is larger than the cross-sectional area of the second via hole; wherein, the first via hole is used to electrically connect the first via hole arranged in the substrate body. a metal wire, the second via hole is used for electrically connecting a second metal wire arranged in the substrate body, and the cross-sectional area of the first metal wire is larger than that of the second metal wire; wherein , at least one of the at least two vias has any one of the following positions: one end is located on the first surface of the substrate body, the other end is located inside the substrate body; one end is located on the substrate body second surface, the other end is located inside the substrate body; one end is located on the first surface of the substrate body, the other end is located on the second surface of the substrate body; both ends are located inside the substrate body; wherein, the The first surface of the substrate body is used for arranging crystal grains, and the second surface faces away from the first surface.

Optionally, the cross-sectional area of the first via hole is greater than a first area threshold, and the cross-sectional area of the second via hole is smaller than a second area threshold, wherein the first area threshold is greater than or equal to the first area threshold. Two area thresholds.

Optionally, a ratio of the cross-sectional area of the first via hole to the cross-sectional area of the second via hole is greater than or equal to a first proportional threshold.

Optionally, the first ratio thresholds are 2:1, 4:1, 5:1, 9:1, and 16:1.

Optionally, in at least a partial space area in the substrate body, in a direction parallel to the first surface of the substrate body, and/or in a direction perpendicular to the first surface of the substrate body, the first The first via hole and the second via hole are alternately arranged.

Optionally, the first surface of the substrate body is used for arranging crystal grains; the second metal wire used for electrical connection of the second via hole and the first metal wire used for electrical connection of the first via hole are in the same position. The substrate body is arranged in layers, and the layer where the second metal wire is located is closer to the first surface of the substrate body than the layer where the first metal wire is located.

Optionally, the length of the first metal line is greater than a first length threshold, and the length of the second metal line is less than or equal to the first length threshold.

Optionally, the value range of the first length threshold is 4 mm to 6 mm.

In a second aspect, embodiments of the present invention further provide a chip, including a substrate and at least one die set on the substrate, wherein the substrate is any silicon-based substrate provided by the embodiments of the present invention a substrate, the first metal contact on the die is electrically connected to the first metal wire in the substrate, and the second metal contact on the die is electrically connected to the second metal wire in the substrate connection; wherein, the first metal wire is electrically connected to the first via hole, and the second metal wire is electrically connected to the second via hole.

In a third aspect, the embodiments of the present invention further provide a chip, including: a first substrate, a second substrate and a die, wherein the first substrate is any silicon-based substrate provided by the embodiments of the present invention a substrate; at least part of the pins of the die are electrically connected to metal contacts on the first surface of the first substrate; metal wires are arranged in the first substrate, and the metal wires include at least one of the first substrates. a metal wire and at least one of the second metal wires; a part of the metal contacts on the first surface of the first substrate are interconnected through the metal wires in the first substrate, and the other part of the metal contacts are connected through vias and all The metal wires in the first substrate are electrically connected to the metal contacts on the second surface of the first substrate; the metal contacts on the second surface of the first substrate are connected to the first The metal contacts on the surface are electrically connected, and the metal contacts on the first surface of the second substrate are connected to the metal contacts on the second surface of the second substrate through vias and metal lines in the second substrate. The contacts are electrically connected.

Optionally, the first metal contact and the second metal contact on the first surface of the first substrate are interconnected through the first metal wire; and/or, the first metal contact on the first surface of the first substrate The third metal contact and the fourth metal contact are interconnected by the second metal line.

Optionally, the minimum distance between the metal contacts on the first surface of the first substrate is less than a first distance threshold; the minimum distance between the metal contacts on the second surface of the second substrate is greater than the first distance. Two spacing thresholds, the first spacing threshold is smaller than the second spacing threshold.

Optionally, the minimum spacing between the metal contacts on the second surface of the first substrate is greater than the first spacing threshold and less than the second spacing threshold.

Optionally, the second substrate is a high density interconnection printed circuit board.

Optionally, the second metal wire and the first metal wire are arranged in layers in the first substrate, the first metal wire and the second metal wire are in different layers, and the first metal wire is in different layers. The thickness of the metal line is greater than the thickness of the second metal line.

Optionally, the width of the second metal line is less than 10 microns.

Optionally, the number of the crystal grains includes one or more.

Optionally, the number of the first substrates includes one or more, and each of the first substrates is provided with at least one die.

In the silicon-based substrate and the chip provided by the embodiments of the present invention, at least two via holes are provided in the substrate body, and at least one via hole in the at least two via holes has any one of the following positions: one end is located at the The first surface of the substrate body, and the other end is located inside the substrate body; one end is located on the second surface of the substrate body, and the other end is located inside the substrate body; one end is located on the first surface of the substrate body, and the other end is located in the substrate body It is located on the second surface of the substrate body; both ends are located inside the substrate body. In this way, it is convenient to electrically connect the first surface and the second surface of the substrate body and the metal wires or metal contacts inside the substrate body, thereby providing abundant available resources for the interconnection of die pins. The cross-sectional area of the first via is larger than the cross-sectional area of the second via, and the cross-sectional area of the first metal line is larger than the cross-sectional area of the second metal line. Therefore, the first via is convenient for electrical connection with the first metal line, and the second via It is convenient to be electrically connected with the second metal wire, so that it is convenient to interconnect the farther die pins through the first metal wire with a larger cross-sectional area, so as to reduce the attenuation of the signal by the impedance of the metal wire and ensure the transmission efficiency. Signal quality; at the same time, it is convenient to interconnect the die pins with a short distance through a second metal wire with a smaller cross-sectional area, so as to achieve high-density signal transmission, so that it is convenient to take into account the short-distance and high-density through the same silicon substrate. Signal transmission and long-distance low-loss signal transmission.

Description of drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are just some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a silicon-based substrate provided by an embodiment of the present invention;

2 is a schematic structural diagram of a via hole in an embodiment of the present invention;

3 is another schematic structural diagram of a via hole in an embodiment of the present invention;

4 is another structural schematic diagram of a via hole in an embodiment of the present invention;

5 is another structural schematic diagram of a via hole in an embodiment of the present invention;

FIG. 6 is another schematic structural diagram of a silicon-based substrate provided by an embodiment of the present invention;

FIG. 7 is another schematic structural diagram of a silicon-based substrate provided by an embodiment of the present invention;

FIG. 8 is another schematic structural diagram of a silicon-based substrate provided by an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a chip according to an embodiment of the present invention.

Detailed ways

The embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.

It should be clear that the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

In a first aspect, the embodiments of the present invention provide a silicon-based substrate, which facilitates effectively taking into account both short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon-based substrate.

FIG. 1 is a side view of a silicon-based substrate provided by an embodiment of the present invention. As shown in FIG. 1 , the silicon-based substrate provided by the embodiment of the present invention may include:

Substrate body 1, at least two via holes 2 are provided in the substrate body 1, the at least two via holes 2 include at least one first via hole 21 and at least one second via hole 22, the cross-section of the first via hole 21 is The area is larger than the cross-sectional area of the second via hole 22 ; wherein, the first via hole 21 is used to electrically connect the first metal wire 31 arranged in the substrate body 1 , and the second via hole 22 is used to electrically connect to the substrate body 1 . The cross-sectional area of the second metal wire 32 in the first metal wire 31 is larger than the cross-sectional area of the second metal wire 32; wherein, at least one of the at least two via holes 2 has any one of the following positions : one end is located on the first surface 11 of the substrate body 1, the other end is located inside the substrate body 1; one end is located on the second surface 12 of the substrate body 1, and the other end is located inside the substrate body 1; one end is located on the first surface 11 of the substrate body 1, The other end is located on the second surface 12 of the substrate body 1 ; both ends are located inside the substrate body 1 ; the first surface 11 of the substrate body 1 is used for arranging die, and the second surface 12 faces away from the first surface 11 .

In the silicon-based substrate provided by the embodiment of the present invention, at least two via holes 2 are provided in the substrate body 1 , and at least one via hole in the at least two via holes 2 has any one of the following positions: one end is located at The first surface 11 of the substrate body 1, the other end is located inside the substrate body 1; one end is located on the second surface 12 of the substrate body 1, and the other end is located inside the substrate body 1; The second surface 12 of the substrate body 1 ; both ends are located inside the substrate body 1 . In this way, it is convenient to electrically connect the first surface and the second surface of the substrate body and the metal wires or metal contacts inside the substrate body, thereby providing abundant available resources for the interconnection of die pins. The cross-sectional area of 21 is larger than the cross-sectional area of the second via hole 22, and the cross-sectional area of the first metal line 31 is larger than that of the second metal line 32. Therefore, the first via hole 21 is convenient for electrical connection with the first metal line 31. connection, the second via hole 22 is convenient for electrical connection with the second metal wire 32, so that it is convenient to interconnect the distant die pins through the first metal wire 31 with a larger cross-sectional area, so as to reduce the metal wire The attenuation of the signal by the impedance ensures the quality of the transmitted signal; at the same time, it is convenient to interconnect the die pins with a short distance through the second metal wire 32 with a smaller cross-sectional area, so as to achieve high-density signal transmission, so as to facilitate the passage of The same silicon-based substrate takes into account both short-distance high-density signal transmission and long-distance low-loss signal transmission.

In the embodiment of the present invention, the via hole 2 may refer to any hole in the silicon-based substrate for electrically connecting metal wires of different layers. According to whether the openings at both ends of the via hole 2 are located on the surface of the substrate body 1 , the via hole 2 can be further classified into the following situations. It should be noted that the via hole 2 here may include either a first via hole 21 with a larger cross-sectional area, or a second via hole 22 with a smaller cross-sectional area.

As shown in FIG. 2 , in an embodiment of the present invention, one end of at least one via hole 2 of the at least two via holes 2 may be located on the first surface 11 of the substrate body 1 , and the other end may be located inside the substrate body 1 . . Such vias 2 may be used to electrically connect metal contacts on the first surface 11 of the substrate body 1 with metal lines inside the substrate body 1 . Alternatively, as shown in FIG. 3 , in another embodiment of the present invention, one end of at least one via hole 2 of the at least two via holes 2 may be located on the second surface 12 of the substrate body 1 , and the other end may be located on the substrate Inside the body 1. Such vias 2 may be used to electrically connect metal lines inside the substrate body 1 with metal contacts on the second surface 12 of the substrate body 1 . Alternatively, as shown in FIG. 4 , in another embodiment of the present invention, one end of at least one via hole 2 of the at least two via holes 2 may be located on the first surface 11 of the substrate body 1 , and the other end may be located on the substrate The second surface 12 of the body 1 . Such vias 2 may be used to electrically connect metal contacts on the first surface 11 of the substrate body 1 with metal contacts on the second surface 12 of the substrate body 1 . Alternatively, as shown in FIG. 5 , in yet another embodiment of the present invention, both ends of at least one via hole 2 of the at least two via holes 2 may be located inside the substrate body 1 ; It is used to electrically connect two metal lines of different layers inside the substrate body 1 . Various interconnections of metal lines of different layers can be effectively realized through these types of vias 2 .

In a specific implementation, it can be determined whether the first via hole 21 , the first metal wire 31 or the second via hole 22 and the second metal wire 32 are used for the interconnection between the die pins according to the needs. Since the cross-sectional areas of the first via hole 21 and the first metal wire 31 are relatively large, they can support long-distance signal transmission. Based on this, in an embodiment of the present invention, the length of the first metal wire 31 can be greater than The first length threshold, so that when the signal transmission distance is greater than the first length threshold, the first metal line 31 and the first via hole 21 are used for interconnection. In contrast to this, the length of the second metal line 32 may be less than or equal to the first length threshold, so when the signal transmission distance is less than or equal to the first length threshold, the second metal line 32 and the second via hole 22 are used to perform the signal transmission. interconnected. Optionally, the first length threshold may be different according to the conductivity of the metal wire. The better the conductivity, the larger the first length threshold, and the worse the conductivity, the smaller the first length threshold. For example, in an embodiment of the present invention, for a metal wire made of metal copper, the value range of the first length threshold may be 4 mm to 6 mm, and typically, it may be 5 mm.

In the embodiment of the present invention, the size of the via hole 2 can be represented by the cross-sectional area of the via hole, the cross-sectional area of the larger via hole is larger, and the cross-sectional area of the smaller via hole is smaller. Since the first via hole 21 and the first metal line 31 are suitable for signal transmission with relatively long distance and low loss, the second via hole 22 and the second metal line 32 are suitable for signal transmission with a relatively short distance and high density, that is, The two have different task divisions. Therefore, in order to more effectively complete the long-distance low-loss signal transmission task and the short-distance high-density signal transmission task, in an embodiment of the present invention, the first pass The cross-sectional area of the hole 21 and the cross-sectional area of the second via hole 22 are made to have a large difference. For example, in one embodiment of the present invention, the cross-sectional area of the first via hole 21 may be greater than the first area threshold, and the cross-sectional area of the second via hole 22 may be smaller than the second area threshold, wherein the first area threshold greater than or equal to the second area threshold. The specific values of the first area threshold and the second area threshold can be set or adjusted according to specific process parameters. Optionally, in order to make the cross-sectional area of the first via hole 21 and the cross-sectional area of the second via hole 22 have a large difference, in another embodiment of the present invention, the cross-sectional area of the first via hole 21 may be The ratio of the cross-sectional area to the cross-sectional area of the second via hole 22 defines the difference between the cross-sectional area of the first via hole 21 and the cross-sectional area of the second via hole 22 . For example, the ratio of the cross-sectional area of the first via hole 21 to the cross-sectional area of the second via hole 22 may be greater than or equal to the first ratio threshold. Optionally, the first ratio threshold may be, for example, 2:1 or 4:1 , 5:1, 9:1, 16:1, etc.

In the embodiment of the present invention, the first via hole 21 and the second via hole 22 are used to electrically connect metal wires in different layers in the substrate body. Therefore, as long as the above-mentioned effective electrical connection can be achieved, and The specific shape of each via hole 2 is not limited, for example, each via hole 2 can be circular, oval, rectangular, polygonal, etc. The specific shape can be set and changed according to the layout layout, and the shape of each via hole 2 is not only Can be the same or different.

Further, since the interconnection of die pins is often complex and diverse, in order to realize such interconnection, the distribution of metal lines and vias used for interconnection may also exist in various situations. For example, multiple layers of metal wires can be arranged on the substrate, an insulating medium layer can be arranged between adjacent layers of metal wires, and any two metal wires of different layers can be electrically connected through vias 2. The large first metal wire 31 can be electrically connected through the first via hole 21 , and the second metal wire 32 with a smaller cross-sectional area can be electrically connected through the second via hole 22 .

Optionally, in order to facilitate the electrical connection of different layers of metal wires, the positions of the via holes 2 can be set at any position or arranged arbitrarily as required, which is not limited in the embodiment of the present invention. For example, in an embodiment of the present invention, a certain distribution area may be planned for the first via hole 21 and a certain distribution area may be planned for the second via hole 22, so that the distribution of the two types of via holes in the substrate is significantly different The first via hole 21 and the second via hole 22 can also be staggered or randomly distributed with each other, so that the distribution of the via holes in the substrate is more uniform and the stress and electrical performance are more optimized.

For example, as shown in FIGS. 6 to 8 , in one embodiment of the present invention, in at least a partial space area within the substrate body 1 , in a direction parallel to the first surface 11 of the substrate body 1 , and /or, in a direction perpendicular to the first surface 11 of the substrate body 1 , the first via holes 21 and the second via holes 22 may be staggered. Here, the first surface 11 of the substrate body 1 may be any surface of the substrate body 1 , for example, may be a surface for arranging crystal grains. The first via holes 21 and the second via holes 22 in FIG. 6 are staggered in the direction parallel to the first surface 11 of the substrate body 1 , and the first via holes 21 and the second via holes 22 in FIG. Arranged staggered in the direction of the first surface 11 of the substrate body 1 , the first vias 21 and the second vias 22 in FIG. 8 are parallel to the first surface 11 of the substrate body 1 and perpendicular to the first In the direction of the surface 11, they are all staggered.

As mentioned above, the first vias 21 and the first metal lines 31 are more suitable for long-distance and low-loss signal transmission due to their larger cross-sectional areas, while the second vias 22 and the second metal Since the wire 32 has a smaller cross-sectional area, it is more suitable for high-density signal transmission at a relatively short distance. In an embodiment of the present invention, since the first surface 11 of the substrate body 1 is used for arranging the die, in order to make the length of the second metal line 32 as short as possible to avoid more signal loss, the second via hole 22 The second metal wire 32 used for electrical connection and the first metal wire 31 used for electrical connection of the first via hole 21 can be arranged in layers in the substrate body 1, wherein the layer where the second metal wire 32 is located is opposite to the first metal wire 32. The layer where the metal wire 31 is located may be closer to the first surface 11 of the substrate body 1 , that is, closer to the die. Since the first metal lines 31 in different layers are electrically connected through the first via holes 21 , and the second metal lines 32 in different layers are electrically connected through the second via holes 22 , accordingly, the second via holes 22 In terms of distribution, it can also be relatively close to the first surface 11 of the substrate body 1 . For example, in one embodiment of the present invention, one end of the second via hole 22 may be located on the first surface 11 of the substrate body 1 , and the other end may be located inside the substrate body 1 .

Optionally, in an embodiment of the present invention, the layer where the first metal wire 31 is located may be either closer to the first surface 11 of the substrate body 1 or closer to the second surface 12 of the substrate body 1. Correspondingly, The distribution of the first vias 21 for electrically connecting the first metal lines 31 may not be particularly limited. For example, in one embodiment of the present invention, one end of the first via hole 21 may be located on the first surface 11 of the substrate body 1 , and the other end may be located inside the substrate body 1 , or one end of the first via hole 21 may be located in the substrate body 1 . The other end of the second surface 12 of the substrate body 1 is located inside the substrate body 1, or one end of the first via hole 21 may be located on the first surface 11 of the substrate body 1, and the other end may be located on the second surface 12 of the substrate body 1, Alternatively, both ends of the first via hole 21 may be located inside the substrate body 1 .

Correspondingly, the embodiments of the present invention also provide a chip, which is convenient for effectively taking into account short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon substrate.

The chip provided by the embodiments of the present invention may include a substrate and at least one die disposed on the substrate, wherein the substrate is any of the silicon-based substrates provided in the foregoing embodiments, and the first metal on the die The contact is electrically connected to the first metal wire in the substrate, and the second metal contact on the die is electrically connected to the second metal wire in the substrate; wherein the first metal wire is connected to The first via hole is electrically connected, and the second metal wire is electrically connected with the second via hole.

The chips provided by the embodiments of the present invention utilize any of the silicon-based substrates provided in the foregoing embodiments for die interconnection, so that corresponding beneficial technical effects can also be achieved, which have been described in detail above and will not be repeated here.

Correspondingly, the embodiments of the present invention also provide a chip, which is convenient for effectively taking into account short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon substrate.

As shown in FIG. 9 , the chip provided by the embodiment of the present invention may include: a first substrate 10 , a second substrate 20 and a die 30 ; wherein the first substrate 10 is any one of the silicon-based substrates provided in the foregoing embodiments At least part of the pins of the die 30 are electrically connected to the metal contacts 110 on the first surface 101 of the first substrate 10; the first substrate 10 is provided with metal wires 102, and the metal wires 102 may include at least one first metal wire 1021 and at least one second metal wire 1022, the cross-sectional area of the first metal wire 1021 is larger than the cross-sectional area of the second metal wire 1022;

A part of the metal contacts on the first surface 101 of the first substrate 10 can be interconnected through the metal wires 102 in the first substrate 10 , and another part of the metal contacts can be connected with the via holes 103 and the metal wires 102 in the first substrate 10 . the metal contacts 140 on the second surface 104 of the first substrate 10 are electrically connected;

The metal contacts 140 on the second surface 104 of the first substrate 10 are electrically connected to the metal contacts on the first surface 201 of the second substrate 20 , and the metal contacts on the first surface 201 of the second substrate 20 pass through via holes 203 and the metal wires 202 in the second substrate 20 are electrically connected to the metal contacts on the second surface 204 of the second substrate 20 .

In the chip provided by the embodiment of the present invention, at least part of the pins of the die 30 are electrically connected to the metal contacts 110 on the first surface 101 of the first substrate 10 , the first substrate 10 is provided with metal wires 102 , and the first A part of the metal contacts on the first surface 101 of the substrate 10 can be interconnected through the metal wires 102 in the first substrate 10, and another part of the metal contacts can be connected to the first substrate 10 through the vias 103 and the metal wires 102 in the first substrate 10 The metal contacts 140 on the second surface 104 of the substrate 10 are electrically connected, and further electrically connected to the second substrate 20. Since the metal wires 102 in the first substrate 10 include the first metal wires 1021 with larger cross-sectional areas, It also includes a second metal wire 1022 with a smaller cross-sectional area, so that the die pins that are far away can be interconnected through the first metal wire 1021 with a larger cross-sectional area, so as to reduce the resistance of the metal wire to the signal At the same time, through the second metal wire 1022 with a smaller cross-sectional area, the die pins with a short distance can be interconnected, so as to achieve high-density signal transmission, so as to facilitate the realization of short distances. High-density signal transmission and long-distance low-loss signal transmission.

It should be noted that the various metal contacts described in the embodiments of the present invention may generally refer to metal contacts with an electrical connection function, and do not limit the specific form and shape of the metal contacts. For example, metal contacts The dots can be flat metal dots, or metal bumps or metal balls protruding from the surface.

Optionally, in the embodiment of the present invention, the packaged chip may include one or more die 30, and these die 30 may be disposed on one or more first substrates 10, that is, the die The number of particles 30 may include one or more, the number of first substrates 10 may also include one or more, and each first substrate 10 may be disposed on the second substrate 20, wherein each first substrate 10 may be disposed on There are one or more dies 30 .

Optionally, the second substrate 20 may be various substrates suitable for chip packaging. For example, in an embodiment of the present invention, the second substrate 20 may be a high-density interconnection printed circuit board.

In the specific implementation, in order to more effectively achieve the effect of reducing the signal loss of the first metal wire 1021 and the effect of increasing the signal interconnection density of the second metal wire 1022 when the pin signals of the die are interconnected, in one of the present invention In the embodiment, the cross-sectional area of the first metal line 1021 and the second metal line 1022 may have a large difference. For example, the cross-sectional area of the first metal line 1021 may The cross-sectional area may be smaller than the second area threshold, wherein the first area threshold may be greater than or equal to the second area threshold, for example, the first area threshold may be one of the following area thresholds: 4 square microns, 10 square microns, 100 square microns. In addition, the width of the second metal line 1022 can also be limited, for example, the width of the second metal line 1022 can be limited to be less than 10 microns, so that more second metal lines 1022 can be arranged on the first substrate 10 per unit area, The signal interconnection density of the second metal line 1022 is effectively improved.

The chip provided by the embodiment of the present invention may refer to a chip product obtained by encapsulating the die 30 . In order to realize the signal interconnection between different pins of the same die 30, or the interconnection between the pins of different die 30, in the embodiment of the present invention, the die 30 can be arranged on the first substrate 10, The above-mentioned signal interconnection is realized through the metal wires 102 arranged in the first substrate 10 . Optionally, in the case where multiple layers of metal wires 102 are arranged in the first substrate 10 , the metal wires 102 of different layers may be further electrically connected through the via holes 103 in the first substrate 10 .

Further, in order to facilitate the application of the chip, for example, in order to facilitate the arrangement of the packaged chip on the main board of the device or to connect it with other external circuits, in the embodiment of the present invention, the first substrate 10 can connect the die to the chip through the metal wire 102. In addition to the signal interconnection of the pins of the die 30, the pin signals of the die 30 can also be led out to the second substrate 20 through the metal wires 102 and the vias 13, so as to be electrically connected to the main board of the device or other external circuits through the second substrate 20. connect.

Optionally, whether it is the metal wire 102 used for interconnecting the die pin signals or the metal wire 102 used to lead the die pin signal to the second substrate 20, it can be transmitted according to the path between the signal transmission endpoints. The length can be realized by using the first metal wire 1021 with a larger cross-sectional area, or by using the second metal wire 1022 with a smaller cross-sectional area. For example, in one embodiment of the present invention, the first metal contact and the second metal contact on the first surface 101 of the first substrate 10 may be interconnected through the first metal wire 1021; and/or, the first metal contact The third metal contact and the fourth metal contact on the first surface 101 of a substrate 10 may be interconnected by the second metal line 1022 . That is to say, in this embodiment, the metal wire 102 for realizing the signal interconnection of the die pins may include either the first metal wire 1021, the second metal wire 1022, or both. Similarly, in another embodiment of the present invention, the metal wire 102 used to lead the die pin signal to the second substrate 20 can also include either the first metal wire 1021 or the second metal wire 1022, or both.

In order to select the first metal line 1021 or the second metal line 1022 for signal interconnection according to the length of the path between the signal transmission endpoints, in an embodiment of the present invention, the first metal line 1021 and the second metal line 1021 can be The length of the line 1022 is set within a certain range. For example, the length of the first metal wire 1021 may be greater than the preset length threshold, and the length of the second metal wire 1022 may be less than or equal to the preset length threshold. Optionally, the value range of the preset length threshold may be 4 mm to 6 mm, for example 5 mm. In this way, if the path between the signal transmission endpoints is greater than the preset length threshold, the signal interconnection can be performed through the first metal wire 1021; if the path between the signal transmission endpoints is less than or equal to the preset length threshold, the first metal wire 1021 The two metal wires 1022 perform signal interconnection.

In order to be able to transmit more signals in the first substrate 1 , a larger number of metal wires 102 may be arranged in the first substrate 10 . When the metal lines 102 cannot be arranged on a plane, the metal lines 102 can be arranged in layers, and the metal lines 102 of different layers can be isolated by an insulating medium layer. For example, in an embodiment of the present invention, the metal wires 102 may be arranged in one or more layers in the first substrate 10, and an insulating medium layer is arranged between the metal wires 102 of different layers. The metal lines 102 of different layers may be electrically connected through via holes on the insulating medium layer. Optionally, in the embodiment of the present invention, the via hole 103 in the first substrate 10 may include at least one first via hole and at least one second via hole, wherein the first via hole may be connected with the first metal wire 1021 For electrical connection, the second via hole may be electrically connected to the second metal wire 1022, and the cross-sectional area of the first via hole is larger than that of the second via hole.

Optionally, the first metal wire 1021 and the second metal wire 1022 may be in the same layer, or may be in different layers respectively. For example, in an embodiment of the present invention, the second metal lines 1022 and the first metal lines 1021 are arranged in layers in the first substrate 10 , and the layer where the second metal lines 1022 are located is opposite to the layer where the first metal lines 1021 are located. , which is closer to the first surface 101 of the first substrate 10 . In this way, since the die 30 is disposed on the first surface 101 of the first substrate 10, the second metal wire 1022 will be closer to the die 30 than the first metal wire 1021, so that the length of the second metal wire 1022 can be effectively reduced, The signal transmission loss of the second metal wire 1022 is reduced.

Further, when the first metal line 1021 and the second metal line 1022 are in the same layer, the difference in cross-sectional area of the first metal line 1021 and the second metal line 1022 can be realized by different widths of the metal lines. When the first metal line 1021 and the second metal line 1022 are in different layers, the difference in cross-sectional area of the first metal line 1021 and the second metal line 1022 may be realized by different widths and/or different thicknesses of the metal lines. For example, in an embodiment of the present invention, the second metal line 1022 and the first metal line 1021 are arranged in layers in the first substrate 10, the first metal line 1021 and the second metal line 1022 are in different layers, and the first metal line 1021 and the second metal line 1022 are in different layers. The thickness of one metal line 1021 may be greater than that of the second metal line 1022 .

Generally, compared with packaged chip products, the area and volume of the die 30 are smaller, so the pin spacing of the same die 30 is also smaller. For example, in an embodiment of the present invention, the same The minimum distance between the pins of the die 30 may be 40 microns to 150 microns. The minimum spacing between pads in external circuits such as a motherboard is generally larger, for example, may be 800 microns to 1000 microns. In view of this, in order to be suitable for connecting the die 30 to an external circuit such as a motherboard, in the embodiment of the present invention, the transition between the first substrate 1 and the second substrate 2 can be performed, and the pins of 40 microns to 150 microns can be gradually connected. pitch, transitioning to a pad pitch of 800 microns to 1000 microns.

Specifically, in an embodiment of the present invention, in the chip package, the die 30 may be disposed on the first surface 101 of the first substrate 10 by a process such as flip-chip bonding, and the first substrate 10 may also be A process such as flip-chip bonding is provided on the first surface 201 of the second substrate 20 , and the second surface 204 of the second substrate 20 can be used for electrical connection with external circuits such as a motherboard. The minimum spacing between the metal contacts 110 on the first surface 101 of the first substrate 10 may be less than the first spacing threshold, and the minimum spacing between the metal contacts on the second surface 204 of the second substrate 20 may be greater than the second spacing threshold A spacing threshold, wherein the first spacing threshold may be smaller than the second spacing threshold. For example, in one example, the first pitch threshold may be 100 microns and the second pitch threshold may be 800 microns.

In order to smoothly transition from the minimum distance between the metal contacts 110 on the first surface 101 of the first substrate 10 to the minimum distance between the metal contacts on the second surface 204 of the second substrate 20, the present invention In one embodiment, the minimum spacing between the metal contacts 140 on the second surface 104 of the first substrate 10 may be further defined, for example, the distance between the metal contacts 140 on the second surface 104 of the first substrate 10 The minimum distance between them may be greater than the above-mentioned first distance threshold and less than the above-mentioned second distance threshold. For example, in one example, the minimum pitch between metal contacts 140 may be 350 microns to 600 microns.

It can be understood that since the first substrate 10 is disposed on the first surface 201 of the second substrate 20 through a flip-chip process, the metal contacts 140 on the second surface 104 of the first substrate 10 can be connected to the second The metal contacts on the first surface 201 of the substrate 20 correspond to each other, that is, the minimum distance between the metal contacts is equal to the minimum distance between the metal contacts 140 .

It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Each embodiment in this specification is described in a related manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments.

In particular, for the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and reference may be made to some descriptions of the method embodiments for related parts.

For the convenience of description, the above apparatus is described by dividing the functions into various units/modules. Of course, when implementing the present invention, the functions of each unit/module may be implemented in one or more software and/or hardware.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field of the present invention can easily think of changes within the technical scope disclosed by the present invention. Or replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (18)

1. A silicon-based substrate, comprising:

the circuit board comprises a substrate body, wherein at least two via holes are arranged in the substrate body, the at least two via holes comprise at least one first via hole and at least one second via hole, and the cross sectional area of the first via hole is larger than that of the second via hole; the first via hole is used for electrically connecting a first metal wire arranged in the substrate body, the second via hole is used for electrically connecting a second metal wire arranged in the substrate body, and the cross-sectional area of the first metal wire is larger than that of the second metal wire;

wherein at least one of the at least two vias has any of the following:

one end of the substrate body is positioned on the first surface of the substrate body, and the other end of the substrate body is positioned in the substrate body;

one end of the substrate body is positioned on the second surface of the substrate body, and the other end of the substrate body is positioned in the substrate body;

one end of the substrate body is positioned on the first surface of the substrate body, and the other end of the substrate body is positioned on the second surface of the substrate body;

both ends are positioned in the substrate body;

the first surface of the substrate body is used for arranging crystal grains, and the second surface and the first surface are opposite.

2. The silicon-based substrate of claim 1, wherein a cross-sectional area of the first via is greater than a first area threshold and a cross-sectional area of the second via is less than a second area threshold, wherein the first area threshold is greater than or equal to the second area threshold.

3. The silicon-based substrate of claim 1, wherein a ratio of a cross-sectional area of the first via to a cross-sectional area of the second via is greater than or equal to a first ratio threshold.

4. The silicon-based substrate according to claim 3, wherein the first scale threshold is 2:1, 4:1, 5:1, 9:1, 16: 1.

5. The silicon-based substrate according to claim 1, characterized in that the first and second vias are staggered in a direction parallel to the first surface of the substrate body and/or in a direction perpendicular to the first surface of the substrate body within at least a partial spatial region within the substrate body.

6. The silicon-based substrate according to claim 1,

the first surface of the substrate body is used for arranging crystal grains;

the second metal wire used for electric connection of the second via hole and the first metal wire used for electric connection of the first via hole are distributed in the substrate body in a layered mode, and the layer where the second metal wire is located is closer to the first surface of the substrate body relative to the layer where the first metal wire is located.

7. The silicon-based substrate of claim 1, wherein the length of the first metal line is greater than a first length threshold, and the length of the second metal line is less than or equal to the first length threshold.

8. The silicon-based substrate according to claim 7, wherein the first length threshold has a value in a range from 4 mm to 6 mm.

9. A chip comprising a substrate and at least one die disposed on the substrate, wherein the substrate is a silicon-based substrate according to any one of claims 1 to 8, a first metal contact on the die is electrically connected to the first metal line in the substrate, and a second metal contact on the die is electrically connected to a second metal line in the substrate; the first metal line is electrically connected with the first via hole, and the second metal line is electrically connected with the second via hole.

10. A chip, comprising: a first substrate, a second substrate and a die, wherein the first substrate is the silicon-based substrate of any one of claims 1 to 8; at least part of pins of the crystal grain are electrically connected with the metal contact on the first surface of the first substrate; metal wires are distributed in the first substrate and comprise at least one first metal wire and at least one second metal wire;

a part of the metal contacts on the first surface of the first substrate are interconnected through the metal wires in the first substrate, and the other part of the metal contacts are electrically connected with the metal contacts on the second surface of the first substrate through the via holes and the metal wires in the first substrate;

the metal contact on the second surface of the first substrate is electrically connected with the metal contact on the first surface of the second substrate, and the metal contact on the first surface of the second substrate is electrically connected with the metal contact on the second surface of the second substrate through a via hole and a metal wire in the second substrate.

11. The chip of claim 10,

the first metal contact and the second metal contact on the first surface of the first substrate are interconnected through the first metal wire; and/or the presence of a gas in the gas,

the third metal contact and the fourth metal contact on the first surface of the first substrate are interconnected through the second metal line.

12. The chip of claim 10, wherein a minimum pitch between metal contacts on the first surface of the first substrate is less than a first pitch threshold; a minimum pitch between metal contacts on the second surface of the second substrate is greater than a second pitch threshold, the first pitch threshold being less than the second pitch threshold.

13. The chip of claim 12, wherein a minimum pitch between metal contacts on the second surface of the first substrate is greater than the first pitch threshold and less than the second pitch threshold.

14. The chip of claim 10, wherein the second substrate is a high-density interconnect printed circuit board.

15. The chip of claim 10, wherein the second metal line and the first metal line are layered in the first substrate, the first metal line and the second metal line are in different layers, and a thickness of the first metal line is greater than a thickness of the second metal line.

16. The chip of claim 10, wherein the width of the second metal line is less than 10 microns.

17. The chip of claim 10, wherein the number of dies comprises one or more.

18. The chip of claim 10, wherein the number of the first substrates comprises one or more, and each of the first substrates has at least one die disposed thereon.

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