[go: up one dir, main page]

TW490793B - Semiconductor device and method of formation - Google Patents

Semiconductor device and method of formation Download PDF

Info

Publication number
TW490793B
TW490793B TW089106143A TW89106143A TW490793B TW 490793 B TW490793 B TW 490793B TW 089106143 A TW089106143 A TW 089106143A TW 89106143 A TW89106143 A TW 89106143A TW 490793 B TW490793 B TW 490793B
Authority
TW
Taiwan
Prior art keywords
barrier layer
layer
opening
copper
interconnect
Prior art date
Application number
TW089106143A
Other languages
English (en)
Inventor
Alexander L Barr
Suresh Venkatesan
David B Clegg
Rebecca G Cole
Olubunmi Adetutu
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW490793B publication Critical patent/TW490793B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05172—Vanadium [V] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01016—Sulfur [S]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

490793 五、發明說明（ 先前申請s耒考 (請先閱讀背面之注意事項再填寫本頁) 本申請案已於1"9年4月5曰以專利申請案號〇9/285,666 申請美國專利。 發明領域 本發明係有關於形成半導體裝置的製程，特別是形成包 士有互連障礙層（interconnect barrier layer)的半導體裝置 的製程。 相關拮藝夕啟沭 經濟部智慧財產局員工消費合作社印製
Ik著半導體裝置的尺寸與封裝持續縮小，在半導體裝置 的打線墊（bond pads )上形成導電緩衝墊（conductive bumps ) 的技術也逐漸普遍化。這些^爰衝墊（bumpS )係用來取代金 屬導線’而電連接打線塾（戈011(1 pads )至個別的封裝腳位 (packaging leads)。緩衝墊的類型包括了控制倒塌晶片連 結型（controlled-collapse chip-connection，C4)緩衝塾。大 體而言，緩衝墊要求在打線墊與緩衝墊之間形成一層由打 線墊所限制大小的金屬層。該打線墊所限制大小的金屬層 包含有鉻化物與鉻合金。然而，含鉻的薄膜通常具有缺陷 (defect )，—例如裂缝（crack )、以及非規則狀的鼓粒邊界 (grain boundary )，其可能會限制含鉻金屬層準確地分離打 線塾與緩衝塾材料之能力。 典型之緩衝墊包括如錫（Sn)與鉛（Pb)等元素。因此， 通常會導致障礙物無法有效分離打線墊與緩衝墊，使得打 線墊的材料與緩衝墊中的錫（S、η )或鉛（P b )起反應，而形 -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 490793 A7 __B7_ 五、發明說明（2 ) 成這些材料的金屬間合金（intermetallic alloy)。如果打線 墊包括有含銅的材料，便會形成易碎的金屬間合金。易碎 的金屬間合金可能因而碎裂並造成緩衝墊的失效。另外， 打線墊與缓衝墊之間合金的過程以及黏著性的退化可能會 導致空洞（void)的形成。較嚴重者，會產生高電阻而對於 半導體裝置的性能有負面的影響並甚至造成半導體裝置的 故障。 . 圖式之簡要説明 , 本發明將籍由下列參照附圖所作之較佳具體實施例的詳 細描述，將會更爲明白但並不爲其所限制，其中相同的參 考數字代表相同的元件，其中： 圖1至圖7係爲本發明第一組具體實施例中，形成具有 銅互連與緩衝墊之半導體裝置的橫截面圖；以及 圖8至圖1 2係爲本發明第二组具體實施例中，形成具有 銅互連與緩衝墊之半導體裝置的橫截面圖。 熟習此項技藝者當可明白以上圖式係以簡化與清楚爲 要，且不必然依實際比例而繪示者。舉例而言，圖式中部 分元件的尺寸較於實際尺寸係被誇大，以助益對於本發明 具體實施例之了解。 本發明之詳細描述 根據本發明之具體實施例，所揭露者係爲一種半導體裝 置及其形成方法。在一具體實施例中，一導通障礙層 (conductive barrier layer)覆蓋於互連（interconnect)之上 方，一保護層（passivation layer)覆蓋於導通障礙層之上 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) T裝 1T---------0», 490793 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（3 ) 方，而该保濩層具有一曝露該導通障礙層之部分的開口 (opening)。在另一具體實施例中，_保護層覆蓋於互連 心上方’孩保護層具有一曝露該互連的開口，而導通障礙 層於開口的範圍内覆蓋於互連之上方。 圖1包括一半導體裝置之部分橫截面圖。該半導體裝置 包括一半導體裝置基板100、以及形成於該半導體裝置基 板1 0 0中之場隔離區i 0 2與摻雜區i 〇 4。一閘極介電層 106覆盍於半導體裝置的部分之上方，而一閘極電極工⑽ 覆蓋於該閘無介電層1 〇 6之上方。 - 一第一層間介電層（ILd)i ίο形成於閘極電極108以及 整個半導體裝置基板100之上方。第一層間介電層11〇被 足義圖案以形成雙重嵌入之開口，其係由黏著/障礙層 112與銅填充材料114所填滿。該黏著/障礙層112通常爲 一種堅硬的金屬、堅硬的金屬氮化物或是堅硬的金屬及其 金屬氮化物的組合。而銅填充材料114則通常爲銅金屬或 銅合金，其中的銅含量必須至少爲九十原子百分比。銅可 以與鎂、硫、碳或類似的元素組成奋金，以增進其黏著 性、電移動性、以及其他金屬互連的特性。在沉積黏著/ 障礙層112與銅填充材料H4之後，該基板被研磨處理， 以除去開口之外的黏著/障礙層1 i 2與銅填充材料丨丨4部 分。 " 在形成第一互連（interconnect)之後，一絕緣障礙層Μ〕 形成於由銅所填滿的互連與第一層間介電層11〇之上方。 此一絕緣障礙層丨22包含有氮化矽（silic0I1 nitride)、氮氧 ^ ^--------t--------- (請先閲讀背面之注意事項再填寫本頁) 冬
本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐） 490793 A7
化矽（silicon oxynitride )或類似的材料。使用絕緣材料以 形成絕緣障礙層122可以減少形成額外的圖案以及蝕刻製 程的需要，否則如果使用導通障礙層，便需要上述的額外 製程以將互連施以彼此之間的電隔離。一第二層間介電層 (ILD)124形成於絕緣障礙層122之上方。一包括有導; 黏著/障礙層126與銅填充材料128之雙重嵌入的互連形 成於第二層間介電層124中。該雙重嵌入的互連之形成係 藉由使用類似於第一層間介電層1 1 〇中雙重嵌入互連的結 構所使用的翁程與材料。 - 如圖2所示，一保護層22接著形成於第二層間介電層 124與雙重嵌入的互連之上方。該保護層22可包括一或多 層的氮化碎、氮氧化矽、二氧化矽（silic〇n di〇xide)或類似 的材料。靠近銅填充材料丨2 8之保護層2 2的部分通常包括 有氮化碎、或含有相對於原子氧之較高濃度的原子氮之氮 氧化石夕。保護層2 2被定義圖案以形成打線墊的開口 2 *， 其透過保護層22而延伸至銅填充材料128。 如圖3所示，一導通障礙層3 2沉積於保護層2 2與銅填充 材料1 2 8之上，方。導通障礙層3 2之沉積製程係可用化學氣 相沉積、物理氣相沉積、蒸鍍沉積、電鍍、無電極電鍍或 類似的方式而完成。該導通障礙層32之厚度通常介於大 約50至300奈米（nm)的範圍。通常，導通障礙層32包含 有一種堅硬的金屬、堅硬的金屬氮化物或是堅硬的金屬及 其金屬氮化物的組合。在一具體實施例中，導通障礙層 32包含了鈦（Ti)與氮化鈦（TiN )的組成。鈦/氮化欽的堆 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） (請先閱讀背面之注意事項再填寫本頁} 裝-------訂i! Φ 經濟部智慧財產局員工消費合作社印製 490793
經濟部智慧財產局員工消費合作社印製 ®增進了其對於下方之保護層22與銅填充材料128的黏著 程度。此外，氮化鈦（TiN)形成了一道阻止銅填充材料與 陸續沉積的導電緩衝墊反應的障礙。就另一種方式而言， 導通障礙層32亦可包含其他材料，如妲（Ta)、氮化鈕 (TaN )、鎢（W)、氮化鈥鎢（Ti WN)、鈥鐫（Ti W)合金、氮 化鶴（WN)、氮化翻（MoN)、氮化姑（c〇N)、以及上述材 料的組成。在其他具體實施例中，亦可使用耐氧材料。這 些材料包括鉑（Pt)、鈀（Pd)、鎳（Ni)、導電的金屬氧化 物、其對應之金屬、或類似之材料。這些導電的金屬氧化 物以及其對應之金屬更可包括銥（Ir)與氧化依（Ir〇2);铷 (Ru)與氧化铷（Ru〇2);鍊（Re)與氧化鍊（Re〇^Re〇3广 或是鐵（Os)與氧化鐵（〇s〇2)。 隨後再鋪上一層光阻34於導通障凝層32之上方。光阻 34曝露出導通障礙層32下方覆蓋有保護層22之部分。光 阻3 4的形成使得打線墊開口 3 4被覆蓋住。此外，其亦可 被定義圖案，以略為延伸至保護層22上方導通障礙層32 之表面部分，如圖3所示。 接著以習用之蝕刻製程對導通障礙層3 2進行蝕刻作用， 以除去保護層2 2上方導通障礙層3 2之曝露部分。在蝕刻 之後，有圖案之光阻層34再藉由電漿蝕刻製程或使用有機 化學藥品的濕化學製程而除去，而這些化學藥品包括ν· 甲基氮五圜-2-酉同（N-methyl-2-pyrrolidone)、丙酉同、4 丁基甲酿1 ( ΜΙΒΚ)、或其他類似的化學藥品。 就另一種方法而言，如果使用鍍金的方'式，例如電鍍或 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明說明（6 無電極電鍍’㈣成導通障礙化，上述 程便不需要了。取而代之者，道、^ #，導通障礙層32可以透過直 (請先閱讀背面之注意事項再填寫本頁) 接在銅填充材料128上方的曝露部份於形成開口24之後， 電鍍而得。如果有必要的話，電鍍可以繼續進行到所鍍上 的金屬覆蓋保護層的—部分，以形成導通障礙層32，t 係如圖4所示者。 接著’ 一晶粒塗佈層（die c〇at layer) ”形成於半導體裝 置I上万，並且被定義圖案以在打線墊開口以上方形成 -晶粒塗伟層開口 54，如圖5所示。在本具體實施例中； 導通障礙層32之周圍部分具有曝露於晶粒塗佈層開口 54 的邊緣。晶粒塗佈層52之形成係可用可感光之聚醯亞胺 (polyumde)層或是使用習知的光阻與蝕刻製程所定義圖案 之聚酸亞胺（polyimide )層。 經濟部智慧財產局員工消費合作社印製 在形成打線墊所限制大小的金屬層62之前，如圖6所 示，導通障礙層32之曝露部分係由射頻濺鍍的清潔方式 所處理。射頻濺鍍的清潔方式可除去導通障礙層32之最 上層邵分，其可能包含有例如氧、碳、氟與氯等雜質，以 改善障礙層與打線墊所限制大小的金屬層6 2之間的接觸 電阻。在一具體實施例中，射頻濺鍍的清潔製程係可在沉 積打線蟄所限制大小的金屬層（於緩衝墊下方）之前，作爲 現場（in-Situ)製程的一部分。在一具體實施例中，執行射 頻賤艘α潔的製程參數如下：射頻功率大約介於丨2〇〇瓦 (W)至1500瓦（W)之間的範圍内、直流偏壓大約介於_3〇〇 伏特（V)至_600伏特（V)之間的範圍内、產力大約介於 9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 490793 A7 五、發明說明（） 帕（Pascal)之間的範圍内、而時間則大約介於15〇秒至25〇 秒之間的範圍内。射頻濺鍍的清潔製程大約從導通障礙層 32的表面移除了 20至40奈米（nm)範圍的障礙材料。 接著，打線塾所限制大小的金屬層62形成於晶粒塗佈層 開口 54中’如圖6所示。電極所限制大小的金屬層通常包 括有黏著層、中等耦合/焊接層、與反氧化障礙層之組 成。在-具體實施例中，電極所限制大小的金屬層62包括 四種不同層膜之組成：-路層622、—路銅合金層似、一 銅層626、與--金層628。鉻層⑵與鉻銅合金層_各有介 於50至500奈米（nm)範圍之厚度，銅層626具有介於7⑻ 至1300奈米（nm)範圍之厚度，而金層㈣則具有介於至 140奈米(nm)範圍之厚度。就另—種方法而言，電極所限 制大小的金屬層也可包括有其他層膜，例如欽、銅與金的 的：二鈦•、銅與金心組合。通常，電極所限制大小 =屬層62之形成可藉由使用罩幕(_k)的蒸鐘製程而 而’其他的方法，例如賤鍍亦可用於形成電極所 限制大小的金屬層。 根據-具體實施例，在形成電極所限制大小 大料72之緩衝塾材料，被沉積於電㈣限 制大小的金屬層6 2之上方，茹同7 k 一 ^ ^ ^ . ^ ^ , 圖所777。鉛錫焊接材料72 =係可：由使用罩幕的蒸鍍製程而完成，或就另一種 ΓΓ出係可藉由使用習知方法，如電鐘或焊接 賣出㈣—etung)的方式而完成。接著，再施以 -10- 裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適^ΓΓ_ &鮮（GNS)A4規格⑽· 297公釐） 五、發明說明（8 ) 回流（reflow)的製程步驟以圓化鉛錫焊接材料”之角落， 並形成如圖7所示之緩衝塾。 在此一製程階段，基本的半導體裝置便已完成。此一裝 置隨後可被接著至如覆晶（flip chip )或球型格狀陣列封裝 (ball gnd array package)等封裝基板。儘管未被繪示出 來，其他層間的互連亦可依需要而形成。同理，其他互連 亦可被形成以連接至摻雜區j〇4與閘極電極〗〇8。如果額 外的互連需要形成時，其可使用與用來形成絕緣障礙層 122、第二層間介電層124、黏著/障礙層126與銅填充材料 128相同的製程。 圖8至圖1 2係爲本發明另一具體實施例之半導體裝置的 檢截面圖。煩請參閱圖8，其中有一導通障礙層82形成於 第二層間介電層124與銅填充材料128之上方。導通障礙 層8 2之形成係使用相同於先前對照圖3所述之導通障礙層 32的任一種形成材料方法。導通障礙層82具有介於50至 300奈米（nm)範圍之厚度。在此一具體實施例中，一選用 之抗氧化層（oxidation-resist) 84隨後被形成於導通障礙層 8 2之上方。該抗氧化層可採用能夠避免下方層膜被氧化 或者較下方層膜更易被氧化之任何材料。可以採用的材料 包括氮化矽、多晶矽、非晶矽、或導電之金屬氧化物或其 對應之導電金屬。抗氧化層84具有介於10至50奈米（nm) 範圍之厚度。一光阻層86隨後被形成於導通障礙層82與 抗氧化層84之上方。光阻層86被定義圖案，以覆蓋下方 覆蓋有黏著/障礙層126與銅填充材料128'之導通障礙層8 2 -11 - 本紙張尺度適用中國國家^票準（CNS)A4規格（210 X 297公釐） 9 490793 五、發明說明（ 與抗氧化層8 4。 導通障礙層82與抗氧化層84之未被定義圖案的部分隨 後便以g用之蝕刻製程而除去。之後，光阻便被除去，而 一保濩層92形成於包括有導通障礙層82與抗氧化層^之 堆疊結構以及第二層間介電層124部分區域之上方，如圖 9所示。保濩層9 2係類似於先前對照圖2所述之保護層2 2 者。在此一具體實施例中，保護層9 2被定義圖案，以形 成打線墊之開口 94。如圖9所示，並非所有打線·墊之開= 内的保護着均被移除。因此，打線墊之開口只有部分形成 於走義圖案的製程中。保護層之剩餘部分9 6在定義圖案 的製程之後依然保留在抗氧化層8 4之上方。 接著，一晶粒塗佈層1〇〇1形成於半導體裝置之上方，並 且被定義圖案以形成一晶粒塗佈層開口 1〇〇3，如圖i 〇所 示。晶粒塗佈層1001係類似於先前對照圖5所述之晶粒塗 佈層1001者。晶粒塗佈層開口 1〇〇3曝露出保護層92之部 分區域，其包括剩餘部分9 6。在形成晶粒塗佈層開口 1003 <後，以蝕刻方式除去剩餘部分9 6以及其下方之抗 氧化層8 4。藉此形成如圖} i所示之晶粒塗佈層開口 1〇〇3。在此一蝕刻過程中，晶粒塗佈層1〇〇1所曝露出的 保護層9 2部分也被蝕刻。在一具體實施例中，保護層$ 2 包括含碎與氮之成分，例如氮化矽或氮氧化矽，而抗氧化 層8 4則包括有氮化矽。於是，相同或類似的蝕刻化學藥 品可被使用來移去保護層9 2以及抗氧化層8 4的剩餘部分 9 6° ， -12- 本紙張尺度適Tfg國家X 297公釐）
ψ Μ--------t---------φ___ (請先閱讀背面之注意事項再填寫本頁)
經濟部智慧財產局員工消費合作社印製 製程持續被進行以完成如圖12所示之裝置。一電椏所 制大小的金屬層1220以與之前所述者採用相同之方式形 其包括一路層1222、一鉻銅合金層1224、一銅層 、26、與一金層1228。如果需要的話，類似於之前所述 =射頻賤鏡清潔製程可被用來製備形成電極所限制大小的 金屬層1220之前所需要之障礙層表面。在此一具體實施例 :’施以回流步驟，以圓化鉛錫焊接材料1230之角落，並 王現如圖1 2所示之圓頂形貌。 在圖9至郾：1 2所示之具體實施例中，絕緣障礙層1 2 2係 用於除了最上層之互連之外的所有互連。最上層之互連係 爲其上形成有打線墊之互連者。因此，其爲使用導通障礙 層82之唯一互連。 本發明有許多其他可行之具體實施例。煩請參閱圖3， 導通障礙層32亦可包括一類似圖8至圖12中所示之第二組 具體實施例中的抗氧化層8 4之覆蓋（overlying)抗氧化層。 同樣地’第二組具體實施例不一定需要使用抗氧化層 8 4，因爲保護層9 2之剩餘部分9 6允許含氧之電漿的使 用’而不會對導通障礙層8 2造成損害。此項特點在導通-障礙層32或82包括氮化妲（TaN)、氮化鈦（TiN)、或類似 材料時，顯得格外重要，因爲以上這些材料可以與含氧電 漿或其他用來移除或顯影光阻或聚醯亞胺（polyilnide)層的 化學藥品產生不利的化學反應。這些化學藥品可能包括四 甲基氫氧化錢（tetramethyl ammonium hydroxide)、N -甲基-1-氮五圜-2_ 嗣（N-methyl-2-pyrrolidone)、丙嗣、異丁基 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —^wi ^--------^--------- (請先閱讀背面之注意事項再填寫本頁) 490793 經濟部智慧財產局員工消費合作社印製 發明說明（ 甲酮（MIBK)，、以及其他類似的化學藥品。 除了在打線塾之上形成如圖9至圖12所示之導通障礙層 之外’導電障礙材料亦可用來形成半導體裝置導電區域之 間可藉由能量或雷射而調整的連接（energy- 〇r laser_ alterable connection )。這些連接之導電性可藉由雷射來修 正，以程式化或調整裝置之電路。 、 使用導通障礙層來形成藉由雷射而調整的連接具有優於 先如技藝的優點。導通障礙層通常比一般用來形成藉由雷 射而調整的連接之互連具有比較薄、較低熱導度、與較低 反射率之特性。相較於互連，導通障礙層也較具自我保護 (self_passivating)的優點。藉此，使用藉由雷射而調整的 連接可改善穩定度，因爲在雷射調變之後用來短路的電壓 被降低了。此外，藉由雷射而調整的連接可形成於靠近半 導體裝置之上表面處。如此可使雷射使用較低的功率即可 改變藉由雷射而碉整的連接之導電性，其可降低會產生短 路、損壞鄰近互連、以及損壞環繞保護層之電壓。此外， 導通障礙層與藉由雷射而調整的連接可以使用相同材料而 同時形成。藉此，製程整合不需要額外的製程步驟。 儘管特定之材料已依照電極所限制大小的金屬層6 2而 被列舉’其他的材料與變動亦可被使用。舉例而言，導通 障礙層可被作爲部分之電極所限制大小的金屬層。在這種 情形中，可在形成其他的電極所限制大小的金屬層之前， 以蒸嫂或濺鍍至晶圓的方式形成。而在另一具體實施例 中，電極所限制大小的金屬層與焊接材蚪可一起藉由物理 -14- I ^ I------^--------- (請先閱讀背面之注意事項再填寫本頁)
490793 A7 __________B7 ___ 12 ---------- 五、發明說明（） 氣相沉積或喷射印刷的方式而形成，其中饺㈤ 六r塔化夂焊接滴點 可被沉積於孔洞旁邊的地方。 本發明所述之具體實施例可被整合成一製程流程，而、 需使用有毒材料、開發新的製程或是添購新的製^設備^ 導通障礙層3 2及8 2係足以阻隔互連中的銅與緩衝塾中的 錯錫焊接劑彼此產生反應。因此，可在互連與缓衝塾之間 的介面維持製程的整合性。如此可提昇緩衝塾之機械整人 度，並且降低互連與緩衝墊之間的接面電阻。 口 本發明之·圖式與描述以較佳實施例說明如上，僅用於藉_ 以幫助了解本發明之實施，非用以限定本發明之精神，而 熟悉此領域技藝者於領悟本發明之精神後，在不脫離本發 明之精神範圍内，當可作些許更動潤飾及同等之變化替 換，其專利保護範圍當視後附之申請專利範圍及其等同領 域而定。 ·裝--------訂--------- Φ (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 適 度 i尺 張 5 格 規 A4 S)A N (C 準 標 家 釐 公 97

Claims (1)

  1. 490793 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 1· 一種半導體裝置，包括： 一第一互連（114)，其覆蓋於半導體裝置基板（100)之 上方； 一絕緣障礙層（122)，其覆蓋於該第一互連（114)之上 方； 一大部分含銅之互連（128)，其覆蓋於該第一互連 (114)與絕緣障礙層（122)之部分的上方； 一導通障礙層（82)，其覆蓋於該大部分含銅之互連 (128)之部'分的上方，而該導通障礙層（82)延伸於該大-部分含銅之互連（128)之部分的邊緣區域的下方；以及 一保護層（92)，其覆蓋於該導通障礙層（82)之上 方，而該保護層（92)具有一曝露該導通障礙層（82)之 部分的開口。 2·如申請專利範圍第1項之半導體裝置，其中該導通障礙 層（8 2 )之一部份為至少兩導電區域之間的可藉由雷射而 調整的連接。 3. —種半導體裝置，其包括： 一大部分含銅之互連（128)，其覆蓋於半導體裝置基 板（100)之上方； i 一保護層（22)，其覆蓋於該大部分含鋼之互連（128) 之上方，而該保護層（22)具有一曝露該大部分含銅之互 連（128)之部分的開口（24);以及 一導通障礙層（3 2)，其位於開口（24)之内且覆蓋於 該大部分含銅之互連（128)之部分的上方。 |、 (請先閱讀背面之注意事項再填寫本頁) T. n I— tame l . I ϋ ΒΒϋ n I— n 11 ·1 I ， -16-
    490793 A8 B8 C8 D8 六、申請專利範圍 4. 一種形成半導體裝置的方法，其包括以下之步驟： 形成一第一互連（114)，其覆蓋於半導體裝置基板 (100)之上方； 形成一絕緣障礙層（122)，其覆蓋於該第一互連（114) 之上方； 形成一大部分含銅之互連（128)，其覆蓋於該第一互 連（114)與絕緣障礙層（122)之部分的上方； 开>成一導通障礙層（82)，其覆蓋於該大部分含銅之 互連（12_8>·之部分的上方，而該導通障礙層（82)延伸於 該大部分含銅之互連（丨28 )之部分的邊緣區域的下方； 形成一保護層（92)，其覆蓋於該導通障礙層（82)之 上方；以及 开> 成一開口於該保護層（9 2 )内，其中該開口曝露該 導通障礙層（82)之部分。 5·如申請專利範圍第4項之方法，其中形成一開口於該保 護層（92)内更包括以下的步驟： 形成一部分的開口（ 9 4 )於該保護層（9 2 )内，其中該 部分的開口之深度小於該保護層在部分開口形成之處的 厚度； 形成一晶粒塗佈層（1001 )於該保護層（9 2 )之上方； 形成一開口（1003)於該晶粒塗佈層（1〇〇1)内，其中該 晶粒塗佈層開口（ 1〇〇3)曝露出保護層（92)内之部分的開 口（ 9 4 );以及 蝕刻保護層（9 2 )内之部分的開口，’以在形成晶粒塗 -17 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 490793 A8 B8 C8 D8 ' — —— 六、申請專利範圍 佈層（1001)中之開口（ 1003 )之後，曝露其下方之層膜。 6.如申請專利範圍第5項之方法，其更包括以下的步驟： 在形成保護層（9 2 )内的開口之後，移去導通障礙層 (82)之一部分，其中該導通障礙層（82)之部分具有一 深度；以及 在移去導通障礙層（82)之一部分之後，形成一導電 缓衝墊（123〇)於該導通障礙層（82)之上方。 7· —種形成半導體裝置的方法，其包括以下之步驟： 形成一大部分含銅之互連（128)，其覆蓋於半導體裝 置基板（100)之上方； 形成一保護層（22)，其覆蓋於該大部分含銅之互連 (128)之上方； 形成一開口（ 2 4 )於該保護層（2 2 )内，而該開口（ 2 4 ) 曝露該大部分含銅之互連（128 )之部分；以及 形成一導通障礙層（32)，於開口（24)之内，該導通 障礙層（32)覆蓋於該夫部分含銅之互連（ία)之部分的 上方。 (請先閱讀背面之注意事項再填寫本頁) ▼裝--------訂---------' 經濟部智慧財產局員工消費合作社印製 -18- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）
TW089106143A 1999-04-05 2000-04-01 Semiconductor device and method of formation TW490793B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/285,666 US20020000665A1 (en) 1999-04-05 1999-04-05 Semiconductor device conductive bump and interconnect barrier

Publications (1)

Publication Number Publication Date
TW490793B true TW490793B (en) 2002-06-11

Family

ID=23095213

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089106143A TW490793B (en) 1999-04-05 2000-04-01 Semiconductor device and method of formation

Country Status (5)

Country Link
US (2) US20020000665A1 (zh)
JP (1) JP4566325B2 (zh)
CN (1) CN1192430C (zh)
SG (1) SG84587A1 (zh)
TW (1) TW490793B (zh)

Families Citing this family (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6577011B1 (en) * 1997-07-10 2003-06-10 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
JPH11340265A (ja) * 1998-05-22 1999-12-10 Sony Corp 半導体装置及びその製造方法
DE19843624C1 (de) * 1998-09-23 2000-06-15 Siemens Ag Integrierte Schaltungsanordnung und Verfahren zu deren Herstellung
US8178435B2 (en) * 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US7531417B2 (en) * 1998-12-21 2009-05-12 Megica Corporation High performance system-on-chip passive device using post passivation process
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US7381642B2 (en) * 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US7405149B1 (en) * 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US6544880B1 (en) * 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
US6077766A (en) * 1999-06-25 2000-06-20 International Business Machines Corporation Variable thickness pads on a substrate surface
JP4554011B2 (ja) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US6570251B1 (en) * 1999-09-02 2003-05-27 Micron Technology, Inc. Under bump metalization pad and solder bump connections
JP3859403B2 (ja) * 1999-09-22 2006-12-20 株式会社東芝 半導体装置及びその製造方法
US7494927B2 (en) * 2000-05-15 2009-02-24 Asm International N.V. Method of growing electrical conductors
JP3824845B2 (ja) * 2000-06-21 2006-09-20 セイコーエプソン株式会社 Ｌｃｄドライバｉｃチップ
AU2002228926A1 (en) * 2000-11-10 2002-05-21 Unitive Electronics, Inc. Methods of positioning components using liquid prime movers and related structures
US6753605B2 (en) * 2000-12-04 2004-06-22 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US6863209B2 (en) 2000-12-15 2005-03-08 Unitivie International Limited Low temperature methods of bonding components
WO2002052646A1 (en) * 2000-12-22 2002-07-04 Koninklijke Philips Electronics N.V. Integrated circuit device
US6794705B2 (en) * 2000-12-28 2004-09-21 Infineon Technologies Ag Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials
JP2003045877A (ja) * 2001-08-01 2003-02-14 Sharp Corp 半導体装置およびその製造方法
US6759275B1 (en) 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
US7049226B2 (en) * 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
US6762122B2 (en) * 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
US6916398B2 (en) * 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
JP3820975B2 (ja) * 2001-12-12 2006-09-13 ソニー株式会社 半導体装置及びその製造方法
US6661098B2 (en) * 2002-01-18 2003-12-09 International Business Machines Corporation High density area array solder microjoining interconnect structure and fabrication method
JP4340416B2 (ja) * 2002-02-26 2009-10-07 Ｓｐａｎｓｉｏｎ Ｊａｐａｎ株式会社 半導体記憶装置の製造方法
US7531898B2 (en) * 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
AU2003256360A1 (en) * 2002-06-25 2004-01-06 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
JP3779243B2 (ja) 2002-07-31 2006-05-24 富士通株式会社 半導体装置及びその製造方法
JP2004214594A (ja) * 2002-11-15 2004-07-29 Sharp Corp 半導体装置およびその製造方法
DE10301243B4 (de) * 2003-01-15 2009-04-16 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltungsanordnung, insbesondere mit Kondensatoranordnung
JP4170103B2 (ja) * 2003-01-30 2008-10-22 Ｎｅｃエレクトロニクス株式会社 半導体装置、および半導体装置の製造方法
US6869878B1 (en) * 2003-02-14 2005-03-22 Advanced Micro Devices, Inc. Method of forming a selective barrier layer using a sacrificial layer
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
US7026714B2 (en) * 2003-03-18 2006-04-11 Cunningham James A Copper interconnect systems which use conductive, metal-based cap layers
JP4571781B2 (ja) * 2003-03-26 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7238610B2 (en) * 2003-03-31 2007-07-03 Intel Corporation Method and apparatus for selective deposition
US7566964B2 (en) * 2003-04-10 2009-07-28 Agere Systems Inc. Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures
US6893959B2 (en) * 2003-05-05 2005-05-17 Infineon Technologies Ag Method to form selective cap layers on metal features with narrow spaces
DE10335182B4 (de) * 2003-07-30 2007-03-01 Infineon Technologies Ag Anordnung zur Verbesserung der Modulzuverlässigkeit
DE10337569B4 (de) * 2003-08-14 2008-12-11 Infineon Technologies Ag Integrierte Anschlussanordnung und Herstellungsverfahren
US6977435B2 (en) * 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
WO2005024912A2 (en) * 2003-09-09 2005-03-17 Intel Corporation Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow
IL157838A (en) * 2003-09-10 2013-05-30 Yaakov Amitai High-brightness optical device
US7294565B2 (en) * 2003-10-01 2007-11-13 International Business Machines Corporation Method of fabricating a wire bond pad with Ni/Au metallization
US6933171B2 (en) * 2003-10-21 2005-08-23 Intel Corporation Large bumps for optical flip chips
US7451975B2 (en) * 2004-03-18 2008-11-18 Lexmark International, Inc. Input tray and drive mechanism using a single motor for an image forming device
JP2005347622A (ja) * 2004-06-04 2005-12-15 Seiko Epson Corp 半導体装置、回路基板及び電子機器
US8552559B2 (en) * 2004-07-29 2013-10-08 Megica Corporation Very thick metal interconnection scheme in IC chips
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US7355282B2 (en) 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
DE102004048202B4 (de) * 2004-09-30 2008-05-21 Infineon Technologies Ag Verfahren zur Vereinzelung von oberflächenmontierbaren Halbleiterbauteilen und zur Bestückung derselben mit Außenkontakten
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US20060205204A1 (en) * 2005-03-14 2006-09-14 Michael Beck Method of making a semiconductor interconnect with a metal cap
US8025922B2 (en) 2005-03-15 2011-09-27 Asm International N.V. Enhanced deposition of noble metals
US7666773B2 (en) 2005-03-15 2010-02-23 Asm International N.V. Selective deposition of noble metal thin films
US8384189B2 (en) * 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
JP2007005539A (ja) * 2005-06-23 2007-01-11 Seiko Epson Corp 半導体装置
JP4605378B2 (ja) 2005-07-13 2011-01-05 セイコーエプソン株式会社 半導体装置
US20070014919A1 (en) * 2005-07-15 2007-01-18 Jani Hamalainen Atomic layer deposition of noble metal oxides
CN1901162B (zh) * 2005-07-22 2011-04-20 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
US7960838B2 (en) 2005-11-18 2011-06-14 United Microelectronics Corp. Interconnect structure
KR100735526B1 (ko) * 2006-02-08 2007-07-04 삼성전자주식회사 와이어 본딩 신뢰성이 향상된 반도체 소자, 이의 제조에사용되는 레티클, 및 그 제조 방법
US7932615B2 (en) * 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
TWI460820B (zh) * 2006-06-28 2014-11-11 Qualcomm Inc 積體電路（ｉｃ）晶片及其製程
US8421227B2 (en) * 2006-06-28 2013-04-16 Megica Corporation Semiconductor chip structure
US8592977B2 (en) * 2006-06-28 2013-11-26 Megit Acquisition Corp. Integrated circuit (IC) chip and method for fabricating the same
US20080038913A1 (en) * 2006-08-10 2008-02-14 International Business Machines Corporation Methods of forming aluminum-free wire bond pad and pad so formed
US7435484B2 (en) * 2006-09-01 2008-10-14 Asm Japan K.K. Ruthenium thin film-formed structure
DE102006051491A1 (de) * 2006-10-31 2008-05-15 Advanced Micro Devices, Inc., Sunnyvale Metallisierungsschichtstapel mit einer Aluminiumabschlussmetallschicht
KR20090075883A (ko) * 2006-10-31 2009-07-09 어드밴스드 마이크로 디바이시즈, 인코포레이티드 알루미늄 단자 금속층이 없는 금속화층 스택
DE102006051490B4 (de) * 2006-10-31 2010-07-08 Advanced Micro Devices, Inc., Sunnyvale Technik zur Herstellung einer Passivierungsschicht ohne ein Abschlussmetall
US8193636B2 (en) * 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump
US7682959B2 (en) * 2007-03-21 2010-03-23 Stats Chippac, Ltd. Method of forming solder bump on high topography plated Cu
US8030733B1 (en) 2007-05-22 2011-10-04 National Semiconductor Corporation Copper-compatible fuse target
US7964934B1 (en) 2007-05-22 2011-06-21 National Semiconductor Corporation Fuse target and method of forming the fuse target in a copper process flow
DE102007046519A1 (de) * 2007-09-28 2009-04-02 Osram Opto Semiconductors Gmbh Dünnfilm-LED mit einer Spiegelschicht und Verfahren zu deren Herstellung
US20090087339A1 (en) * 2007-09-28 2009-04-02 Asm Japan K.K. METHOD FOR FORMING RUTHENIUM COMPLEX FILM USING Beta-DIKETONE-COORDINATED RUTHENIUM PRECURSOR
KR101544198B1 (ko) * 2007-10-17 2015-08-12 한국에이에스엠지니텍 주식회사 루테늄 막 형성 방법
US7829450B2 (en) * 2007-11-07 2010-11-09 Infineon Technologies Ag Method of processing a contact pad, method of manufacturing a contact pad, and integrated circuit element
DE102007057689A1 (de) * 2007-11-30 2009-06-04 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem Chipgebiet, das für eine aluminiumfreie Lothöckerverbindung gestaltet ist, und eine Teststruktur, die für eine aluminiumfreie Drahtverbindung gestaltet ist
KR20090067505A (ko) * 2007-12-21 2009-06-25 에이에스엠지니텍코리아 주식회사 루테늄막 증착 방법
CN101630667A (zh) * 2008-07-15 2010-01-20 中芯国际集成电路制造(上海)有限公司 形成具有铜互连的导电凸块的方法和系统
US8084104B2 (en) * 2008-08-29 2011-12-27 Asm Japan K.K. Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition
US7709956B2 (en) * 2008-09-15 2010-05-04 National Semiconductor Corporation Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure
US8133555B2 (en) 2008-10-14 2012-03-13 Asm Japan K.K. Method for forming metal film by ALD using beta-diketone metal complex
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US20100155949A1 (en) * 2008-12-24 2010-06-24 Texas Instruments Incorporated Low cost process flow for fabrication of metal capping layer over copper interconnects
US20110020546A1 (en) * 2009-05-15 2011-01-27 Asm International N.V. Low Temperature ALD of Noble Metals
US8329569B2 (en) * 2009-07-31 2012-12-11 Asm America, Inc. Deposition of ruthenium or ruthenium dioxide
US8003515B2 (en) * 2009-09-18 2011-08-23 Infineon Technologies Ag Device and manufacturing method
KR101652386B1 (ko) * 2009-10-01 2016-09-12 삼성전자주식회사 집적회로 칩 및 이의 제조방법과 집적회로 칩을 구비하는 플립 칩 패키지 및 이의 제조방법
KR20110106751A (ko) * 2010-03-23 2011-09-29 삼성전자주식회사 반도체 소자 및 전자 시스템
JP5342532B2 (ja) 2010-10-05 2013-11-13 三菱重工業株式会社 車体フレームの製造方法
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
DE102011005642B4 (de) * 2011-03-16 2012-09-27 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zum Schutz von reaktiven Metalloberflächen von Halbleiterbauelementen während des Transports durch Bereitstellen einer zusätzlichen Schutzschicht
US8871617B2 (en) 2011-04-22 2014-10-28 Asm Ip Holding B.V. Deposition and reduction of mixed metal oxide thin films
US8716858B2 (en) * 2011-06-24 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure with barrier layer on post-passivation interconnect
US8946000B2 (en) 2013-02-22 2015-02-03 Freescale Semiconductor, Inc. Method for forming an integrated circuit having a programmable fuse
KR102387275B1 (ko) * 2015-02-25 2022-04-15 인텔 코포레이션 마이크로전자 구조체 내의 상호연결 패드를 위한 표면 마감부
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
US9704804B1 (en) * 2015-12-18 2017-07-11 Texas Instruments Incorporated Oxidation resistant barrier metal process for semiconductor devices
DE102016114867B4 (de) 2015-12-31 2025-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung, Filmstapel und Verfahren zu deren Herstellung
CN107871669B (zh) * 2016-09-28 2021-02-05 欣兴电子股份有限公司 组装方法
US10204859B2 (en) * 2017-01-25 2019-02-12 Macronix International Co., Ltd. Interconnect structure and fabricating method thereof
US10629334B2 (en) * 2017-09-20 2020-04-21 Texas Instruments Incorporated Nanostructure barrier for copper wire bonding
US10658315B2 (en) * 2018-03-27 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Redistribution layer metallic structure and method
US11367683B2 (en) 2018-07-03 2022-06-21 Infineon Technologies Ag Silicon carbide device and method for forming a silicon carbide device
US11869840B2 (en) 2018-07-03 2024-01-09 Infineon Technologies Ag Silicon carbide device and method for forming a silicon carbide device
US11189538B2 (en) * 2018-09-28 2021-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with polyimide packaging and manufacturing method
US11948848B2 (en) * 2019-02-12 2024-04-02 Intel Corporation Subtractive etch resolution implementing a functional thin metal resist
US11244914B2 (en) 2020-05-05 2022-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad with enhanced reliability
CN114566588A (zh) * 2022-03-09 2022-05-31 中国科学院上海微系统与信息技术研究所 一种基于MoN的SNS约瑟夫森结及其制备方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63293951A (ja) * 1987-05-27 1988-11-30 Hitachi Ltd 半導体素子電極構造
US5220199A (en) * 1988-09-13 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
JP3290459B2 (ja) * 1991-06-27 2002-06-10 株式会社日立製作所 半導体集積回路装置およびその製造方法
US5470787A (en) * 1994-05-02 1995-11-28 Motorola, Inc. Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US5656858A (en) 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
JP2985692B2 (ja) * 1994-11-16 1999-12-06 日本電気株式会社 半導体装置の配線構造及びその製造方法
JPH08191104A (ja) * 1995-01-11 1996-07-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
EP0815593B1 (en) * 1995-03-20 2001-12-12 Unitive International Limited Solder bump fabrication methods and structure including a titanium barrier layer
US5731624A (en) 1996-06-28 1998-03-24 International Business Machines Corporation Integrated pad and fuse structure for planar copper metallurgy
JP3660799B2 (ja) * 1997-09-08 2005-06-15 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP3697044B2 (ja) * 1997-12-19 2005-09-21 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JPH11340265A (ja) * 1998-05-22 1999-12-10 Sony Corp 半導体装置及びその製造方法
US6187680B1 (en) 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL

Also Published As

Publication number Publication date
JP4566325B2 (ja) 2010-10-20
US20020000665A1 (en) 2002-01-03
US20020093098A1 (en) 2002-07-18
SG84587A1 (en) 2001-11-20
US6713381B2 (en) 2004-03-30
CN1269607A (zh) 2000-10-11
JP2000306914A (ja) 2000-11-02
CN1192430C (zh) 2005-03-09

Similar Documents

Publication Publication Date Title
TW490793B (en) Semiconductor device and method of formation
TW522538B (en) Semiconductor device and method of manufacturing the semiconductor device
JP4373866B2 (ja) 半導体装置の製造方法
TWI303855B (en) Semiconductor device and its method for manufacturing
US6927493B2 (en) Sealing and protecting integrated circuit bonding pads
US6392300B1 (en) Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire
US7151312B2 (en) Semiconductor device and method of manufacturing the same
KR101339517B1 (ko) 알루미늄 구리 본드 패드를 위한 캡 층
TW201133736A (en) Semiconductor device including a stress buffer material formed above a low-k metallization system
US7095045B2 (en) Semiconductor device and manufacturing method thereof
US6448171B1 (en) Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability
US9875978B2 (en) Semiconductor chip device
JP2001257226A (ja) 半導体集積回路装置
US7163884B2 (en) Semiconductor device and fabrication method thereof
US20220052000A1 (en) Bonding structures of semiconductor devices
JP4793006B2 (ja) 半導体装置及びその製造方法
JP7606908B2 (ja) 半導体装置、半導体装置の製造方法
JPH118249A (ja) 配線の製法
KR100236713B1 (ko) 반도체장치의 범프(Bump) 형성방법
JP4702827B2 (ja) 半導体装置およびその製造方法
JP2000232156A (ja) 半導体装置の製造方法
JP3308105B2 (ja) 半導体集積回路装置およびその製造方法
WO2005062367A1 (en) I/o sites for probe test and wire bond
WO1997022995A1 (en) Semiconductor device containing two or more metallic wiring layers and method for manufacturing the same
KR101671973B1 (ko) 다층 금속 범프 구조체 및 그 제조방법

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees