JP4702827B2 - 半導体装置およびその製造方法 - Google Patents
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- JP4702827B2 JP4702827B2 JP2004372562A JP2004372562A JP4702827B2 JP 4702827 B2 JP4702827 B2 JP 4702827B2 JP 2004372562 A JP2004372562 A JP 2004372562A JP 2004372562 A JP2004372562 A JP 2004372562A JP 4702827 B2 JP4702827 B2 JP 4702827B2
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
2 電極パッド
3 窒化シリコン膜
4 中間層
5 シード層
6 バンプ
7 ポリイミド樹脂膜
Claims (7)
- 所望の素子領域の形成された半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように電極パッドを形成する工程と、
前記電極パッド表面に酸化性材料を含む中間層を形成する工程と、
フォトリソグラフィにより、バンプ形成領域に窓を有するレジストパターンを形成する工程と、
前記レジストパターンの窓から露呈する前記中間層の上側にバンプを形成する工程と、
前記バンプをマスクとして、前記中間層をパターニングする工程と、
前記バンプの側面で、前記バンプと前記中間層との界面を覆うように、少なくとも前記バンプの周辺部に樹脂絶縁膜を形成する工程と、
を含んでなり、
前記樹脂絶縁膜を形成する工程は、感光性の樹脂絶縁膜を前記バンプ上と、前記バンプの側面であって前記界面よりも高く前記バンプの上面より低いレベルまでと、に塗布後、露光し、アッシングし、前記バンプ表面を露呈させる工程を有することを特徴とする半導体装置の製造方法。 - 前記中間層表面にシード層を形成する工程をさらに含み、
前記バンプを形成する工程では、前記レジストパターンの窓から露呈するシード層表面にめっき法によりバンプを形成し、
前記中間層をパターニングする工程では、前記バンプをマスクとしてシード層もパターニングすることを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記樹脂絶縁膜を形成する工程は、感光性ポリイミド樹脂膜を塗布する工程を含むことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記中間層の形成工程は、スパッタリング法によりチタンタングステン(TiW)層を形成する工程を含むことを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。
- 前記シード層を形成する工程は金層をスパッタリングにより形成する工程を含み、
前記バンプの形成工程は、前記シード層上に電気めっきにより金層からなるバンプを形成する工程を含むことを特徴とする請求項2乃至4のいずれかに記載の半導体装置の製造方法。 - 前記中間層の形成工程はクロム薄膜の形成工程を含み、
前記シード層の形成工程はニッケル層をスパッタリングする工程を含み、
前記バンプの形成工程は、前記ニッケル層上に半田ボールを載置し、前記ニッケル層と前記半田ボールとの界面を融着する工程と、
前記レジストパターンを除去し、前記半田ボールをマスクとして前記中間層およびシード層をパターニングする工程と、
前記半田ボールと前記中間層との界面を覆うようにポリイミド樹脂膜を形成する工程と、
を含むことを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記ポリイミド樹脂膜を形成する工程は、感光性ポリイミド樹脂を塗布し、露光後、前記半田ボール上のポリイミド樹脂を除去する工程を含む請求項6に記載の半導体装置の製造方法。
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JP2004372562A JP4702827B2 (ja) | 2004-12-24 | 2004-12-24 | 半導体装置およびその製造方法 |
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JP2004372562A JP4702827B2 (ja) | 2004-12-24 | 2004-12-24 | 半導体装置およびその製造方法 |
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JP2001224726A Division JP2003037129A (ja) | 2001-07-25 | 2001-07-25 | 半導体装置およびその製造方法 |
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JP2005123649A JP2005123649A (ja) | 2005-05-12 |
JP4702827B2 true JP4702827B2 (ja) | 2011-06-15 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2011054805A (ja) * | 2009-09-02 | 2011-03-17 | Toshiba Corp | 半導体装置、及び半導体装置の製造方法 |
JP6332668B2 (ja) * | 2014-03-19 | 2018-05-30 | 新光電気工業株式会社 | 配線基板及びその製造方法と半導体装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0677231A (ja) * | 1992-08-27 | 1994-03-18 | Toshiba Corp | 半導体装置およびその製造方法 |
JPH06151587A (ja) * | 1992-11-11 | 1994-05-31 | Mitsubishi Electric Corp | 半導体集積回路パッケージ、その製造方法、及びその実装方法 |
JPH10112462A (ja) * | 1996-10-04 | 1998-04-28 | Matsushita Electron Corp | 半導体装置の製造方法 |
JP2000021914A (ja) * | 1998-06-30 | 2000-01-21 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2001035869A (ja) * | 1999-07-21 | 2001-02-09 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
-
2004
- 2004-12-24 JP JP2004372562A patent/JP4702827B2/ja not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0677231A (ja) * | 1992-08-27 | 1994-03-18 | Toshiba Corp | 半導体装置およびその製造方法 |
JPH06151587A (ja) * | 1992-11-11 | 1994-05-31 | Mitsubishi Electric Corp | 半導体集積回路パッケージ、その製造方法、及びその実装方法 |
JPH10112462A (ja) * | 1996-10-04 | 1998-04-28 | Matsushita Electron Corp | 半導体装置の製造方法 |
JP2000021914A (ja) * | 1998-06-30 | 2000-01-21 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2001035869A (ja) * | 1999-07-21 | 2001-02-09 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
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