WO1997022995A1

WO1997022995A1 - Semiconductor device containing two or more metallic wiring layers and method for manufacturing the same

Info

Publication number: WO1997022995A1
Application number: PCT/JP1996/003685
Authority: WO
Inventors: Juri Kato; Yukiharu Kobayashi; Masanori Yasuhara; Yutaka Maruo; Hiroo Sato; Kazuharu Kawamura; Takeshi Watanabe
Original assignee: Seiko Epson Corporation
Priority date: 1995-12-18
Filing date: 1996-12-18
Publication date: 1997-06-26
Also published as: TW367605B; KR19980702211A

Abstract

A method for manufacturing a semiconductor device containing two or more metallic wiring layers comprises: the step (a) of forming a first metallic wiring layer (10) having a first conductive layer (12) made mainly of at least aluminum and a second conductive layer (14) containing a metal having a melting point higher than that of the layer (12); the step (b) of forming an interlayer insulating layer (20) having a through hole by forming an insulating layer exhibiting electrical insulation on the first metallic wiring layer (10) and a resist layer of a prescribed pattern on the insulating layer, and patterning the insulating layer in such a way that at least part of the second conductive layer (14) is left by etching the insulating layer, using the resist layer as a mask; the step (c) of removing the resist layer; and the step (d) of forming a second metallic wiring layer (50) including a first conductive layer (52) made mainly of at least aluminum on the interlayer insulating layer (20) and electrically connecting the first and second wiring layers (12 and 50) to each other by forming a conductive section in the through hole. In this method, the reaction of the aluminum contained in the first conductive layer (12) with the etching gas and the resist components is prevented and no reaction product that hinders the patterning of the second metallic wiring layer (50) is formed, because the resist layer is removed while the second conductive layer (14) is left. Therefore, defects such as short-circuit and disconnection in the second metallic wiring layer (50) is prevented reliably.

Description

Specification

2 Semiconductor device including 11% or more gold / 5 wiring layers and method of manufacturing the same

The present invention relates to a semiconductor device having a multilayer wiring layer made of a material containing aluminum as a main component and a method for manufacturing the same.

[Landscape technology]

A semiconductor device with a metal wiring layer of two or more scraps! As shown in FIG. 11, a first metal wiring layer is formed on a substrate, an element formation region formed on a certain plate, and a region 200 including at least an insulating layer. 10 is formed. The first additional wiring layer 10 includes a first conductive layer 12 made of aluminum or an aluminum alloy, and a second layer 14 formed on the first conductive dust 12. Consists of The second conductive dust 14 is made of, for example, a β-melting metal such as titanium or molybdenum or an alloy thereof. Functions as an anti-reflection film. Then, on the gold / S wire scrap 1 0 I¾ 1 is waste question insulating layer 2 0 made of S i 0 ₂ or PSG is formed. Next, a resist layer 30 for passing through holes is formed on the insulating layer 20 between chips. Thereafter, etching, for example, dry etching is performed using a gas containing fluorine such as CF ₄ to remove the interlayer insulating layer 20 and the second conductive layer 14, thereby forming a through hole 40 having a predetermined pattern. You. After that, the resist layer 30 is removed, and a second metal wiring (not shown) is formed.

In the above-described process, when the resist ^ 30 is removed by, for example, dry etching using oxygen plasma, the patterning of the second metal wiring traces is obstructed by some deposits. Have been found to be

[Disclosure of the Invention] An object of the present invention is to prevent the generation of a substance that hinders the patterning of a metal wiring layer, and to perform patterning with a high degree of bonding. An object of the present invention is to provide a semiconductor device including a metal wiring and a method of manufacturing the same.

The manufacturing method of the present invention is a method of manufacturing a semiconductor device including two or more gold wiring layers, and includes the following steps (a) to (d).

(a) Forming a first metal wiring layer having at least a conductive layer of aluminum at least as a main component and a second ^; layer containing gold having a higher melting point than the conductive layer of the layer Process,

(b) forming an insulating material having an electrical insulating property on the first metal wiring layer, forming a resist layer having a predetermined pattern on the insulating layer, and using the resist layer as a mask, A step of patterning the insulating layer while leaving at least a part of the second layer by etching the debris, thereby forming a debris insulating layer having a through hole;

(c) removing the resist layer; and

(d) forming, on the IS ^ insulating layer, at least a second metal wiring scrap including a first conductive layer containing aluminum as a main component, and forming a conductive portion in the through hole; Electrically connecting the first metal wiring layer and the second gold wiring layer.

According to the inventors of the present application, it has been confirmed that the above-mentioned undesired deposits (foreign matter) that cause the patterning failure β of the second metal wiring layer include aluminum and a resist component. Although the generation mechanism of this foreign matter is not necessarily clear, when a through-hole is formed by etching the insulating layer between layers and the second conductive layer constituting the first metal wiring layer below the insulating layer between layers. Then, the first conductive layer exposed in the through-hole, the aluminum constituting the layer, the resist component, and the etching gas component react with each other, so that they can be subjected to the asshing treatment with oxygen plasma and the wet cleaning with a commonly used organic solvent. It is considered that a reaction product that cannot be removed is generated, and this reaction product inhibits the patterning of the second metal wiring dust. Further, according to the present inventors, the reaction product is: It has been confirmed that it grows in the form of a screen (screen shape) during the asking process or cleaning process using oxygen plasma.

According to the method of manufacturing a semiconductor device according to the present invention, at the time of forming the through-hole in the step (b), at least a part of the second layer containing the gold melting point is left. Thereby, the interlayer insulating layer can be etched while completely covering the first layer mainly composed of aluminum. Therefore, it is possible to prevent the reaction between aluminum, which is a substance causing the foreign matter, and the etching gas and the resist component. As a result, there is no occurrence of a reaction product which causes short-circuiting or disconnection of the second metal wiring layer, and a highly reliable and high-yield integrated device can be manufactured. Note that the semiconductor device according to the present invention has 2 ′ or more gold wiring layers, and the first gold wiring layer means a metal wiring layer below the upper gold wiring layer, Fl, the second metal wiring layer means a gold wiring layer which is above and closest to the gold wiring layer of the above (1).

In the present invention, the first conductive layer containing aluminum as a main component is made of aluminum or an aluminum alloy such as aluminum-silicon, aluminum-copper, and aluminum-silicon-copper. The second conductive layer containing the high melting point metal may be made of a high melting point metal such as titanium, molybdenum and tungsten, or an alloy of these metals, for example, titanium-nitrogen, molybdenum-silicon, tungsten-silicon, It is composed of titanium-tungsten or the like. The second conductive dust preferably has a thickness of 20 to 200 nm, more preferably 40 to 100 nm. By setting the thickness of the second conductive dust in this range, not only does it function as an antireflection film for light during exposure and as a barrier waste, but also the second conductive layer is formed when forming a through hole. It is possible to secure a margin for preventing the first conductive layer from being exposed by being removed by etching. This margin is set in consideration of the difference in the depth of each through hole, etching conditions, and the like.

In the method for manufacturing a semiconductor device according to the present invention, subsequent to the step (c), etching is performed using the interlayer insulating layer as a mask to remove the second conductive layer in a region corresponding to the through hole. It is preferable that the step (e) is right and then the step (d) is performed. According to this manufacturing method, the first conductive dust constituting the first metal wiring layer comes into contact with the contact conductor formed in the through-hole, so wherein _c can be a metal wiring layer to reduce the contact resistance between the contactor preparative conductive portion and the second conductive layer is to contain the refractory metal, electrical resistance than the first conductive layer mainly composed of Aruminiumu Since it is large, the contact resistance in the contact conductive portion can be reduced by not interposing the second conductive layer in the contact conductive portion. However, if the contact resistance in the contact conductive portion is acceptable, the semiconductor device of the present invention described later can be manufactured by a simple process by not performing the step (e).

Further, in the manufacturing method according to the present invention, in the step (c), it is preferable that the resist layer is removed in a gas phase containing oxygen plasma.

In the present invention, as described above, in the step (b), by leaving the second conductive bending constituting the first metal wiring layer, an undesired deposition in the step of removing the resist layer in the step (c) is performed. The generation of objects can be prevented. As a result, the resist layer can be sufficiently removed by the asshing treatment in a gas phase containing oxygen plasma. For this reason, a cleaning process using a liquid which is normally required in removing the resist layer is not required or can be extremely simplified, so that the process can be simplified.

A semiconductor device according to the present invention is a semiconductor device including two or more gold wiring layers.

A first conductive layer containing aluminum as a main component, and a first metal wiring layer connecting a second conductive layer containing a metal having a higher melting point than the first conductive layer;

A second metal wiring layer which is located higher than the first metal wiring layer and has at least a first conductive layer mainly containing aluminum;

A dust insulating layer which is present between the first metal wiring ^ and the second metal wiring ^, electrically insulates both, and has a through hole at a predetermined position; and

A contact conductive portion formed in the through hole of the interlayer insulating dust and electrically connecting the first metal wiring layer and the second metal wiring layer,

The contact conductive portion is connected to the first gold bent wiring, and And electrically connected to the first conductive layer via the conductive layer.

According to this semiconductor device, in the step of forming a through hole in the insulating layer by leaving the second conductive layer, aluminum, a resist component, and an etching gas component constituting the first metal wiring layer Since no reaction product is generated, no deposit that hinders the patterning of the second metal wiring layer is generated. Therefore, it is possible to provide a semiconductor device which can be manufactured by a simple process and has high reliability and good yield.

[Brief description of the figure]

1 to 7 are cross-sectional views schematically showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 1 is a cross-sectional view showing a step of forming a first metal wiring ^ on an element formation region.

FIG. 2 is a cross-sectional view illustrating a step of forming a dust insulating layer.

FIG. 3 is a cross-sectional view showing a step of removing the resist layer.

FIG. 4 is a cross-sectional view showing a step of etching the second conductive layer.

FIG. 5 is a cross-sectional view showing a step of forming a barrier layer forming the second metal wiring layer.

FIG. 6 is a cross-sectional view showing a step of forming a first conductive layer forming a second metal wiring layer.

FIG. 7 is a sectional view showing a step of forming a passivation layer.

8 to 10 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 18 is a cross-sectional view showing a step of forming a barrier layer constituting the second metal wiring layer.

FIG. 9 is a cross-sectional view showing a step of forming a first conductive layer constituting a second metal wiring layer.

FIG. 10 is a cross-sectional view showing a step of forming a passivation layer.

FIG. 11 is a cross-sectional view schematically showing one example of a conventional method for manufacturing a semiconductor device. [Best Mode for Carrying Out the Invention]

Hereinafter, preferred embodiments of the present invention will be described in order to further explain the present invention in β form.

(First embodiment)

A method for manufacturing the semiconductor device ^{1 according} to the first embodiment of the present invention will be described with reference to FIGS.

(Α) First, an element isolation region 2 and an element formation region 100000 are formed on a semiconductor substrate 100 by a normal method, and further, these element isolation region 2 and an element formation region 100層 Form the first layer 8 Then, a through hole is formed at a predetermined position of the insulating layer 8 of the first layer by an ordinary method. Then, a first conductive layer 12 having a thickness of 200 to 100 nm is formed on the first interlayer insulating layer 8, and then a second conductive layer 12 having a thickness of 40 to 100 nm is formed. The conductive layer 14 is formed, for example, by a sputtering method. The first conductive layer 12 is made of aluminum or an alloy containing aluminum as a main component, for example, aluminum-silicon, aluminum-copper, aluminum-silicon-copper. The second conductive layer 14 may be made of a melting point of gold, such as titanium, molybdenum and tungsten, or gold of these metals, for example, titanium-nitrogen, molybdenum-carbon, tungsten-silicon, titanium-tungsten. It is composed of The film thickness of the second conductive layer 14 is not only a function as an antireflection layer and a barrier layer for light during exposure, but also the second conductive layer is removed by etching when a through hole is formed. The setting is made in consideration of a margin for preventing the first conductive dust from being exposed.

These layers are patterned using commonly used lithography technology and etching technology such as reactive ion etching (RIE) to form a first conductive dust 12 and a second conductive dust having a predetermined pattern. A first metal wiring layer 10 consisting of 14 is formed (FIG. 1).

The element forming region 1 0 0 0 In this example, element consists formed on the semiconductor substrate 1 0 0 on eg S i 0 ₂ chips (LOCOS) - formed in the regions partitioned by the f- isolation region 2 Formed in the substrate 100, for example, in a source / drain region. It is configured to include impurity diffusion debris 4 constituting a region and a gate electrode 6 formed on a substrate 100 via an insulating film. In FIG. 1, a MOS element is shown as an example of an element in a conventional manner, but the element formation region 100 includes all types of semiconductor elements and element isolation structures capable of forming an electronic circuit. There are many things you can do. The element formation region 100 can be formed by a method generally used depending on various devices.

(B) Next, a second inter-layer insulating layer 20 made of, for example, Si 02, PSG, etc., is formed on the first metal wiring brows 10 with a film thickness of 200 to 400 Formed in nm. Next, a resist layer 30 having a predetermined pattern is formed on the second inter-insulation layer 20 by using a commonly used method. Through holes 40a are formed in the second interlayer insulating layer 20 by dry etching using the resist waste 30 as a mask and using, for example, a fluorocarbon-based gas as a reaction gas. As the full Uz carbon-based gas used for dry _{_{etching, CF "CHF 3, C 2}} F f , or the like can be used. Further, the etching gas, helium, argon, an inert gas such as nitrogen is added By adding an inert gas to the etching gas, the etching rate of the second conductive layer 14 can be reduced, and as a result, the second conductive j ′ is removed and the second conductive layer 14 is removed. Exposure of the conductive debris is prevented.The preferred composition of the etching gas depends on the selection ratio between the second insulating layer between debris 20 and the second lightning layer 14 and the like. For example, it is desirable to set the ratio between the fluorocarbon-based gas and the inert gas to be 10:90 to 9 °: 10 by volume ratio. Second conductive debris 14 that constitutes metal wiring layer 10 remains In this state, a through hole 40a is formed in the second interlayer insulating dust 20 (FIG. 2).

In this step, since the first conductive layer 12 mainly composed of aluminum is covered by the second conductive layer 14 made of high melting point metal, the second conductive layer 12 is etched during the second inter-layer insulating layer 20. Does not produce deposits containing aluminum and resist components.

(C) Next, the resist layer 30 is removed by asshing with, for example, oxygen plasma (FIG. 3). In this step, since the deposit is not formed in the step (B), no substance that inhibits the subsequent patterning of the second metal wiring layer remains. In this state, the resist layer 30 can be almost completely removed by asking with the oxygen plasma. However, in this step, if necessary, jet cleaning using a liquid such as an organic solvent can also be used.

(D) Next, the second interlayer insulating layer 2 0 as a mask, for example, SF _t:, by removing the second ¾ layer 1 4 an etching gas Te Kawai such CF _4, the first conductive (4) A through hole 40b is formed with the layer 12 exposed (FIG. 4).

(E) Next, a barrier layer 54 having a film thickness of 20 to 200 nm is formed by, for example, a sputtering method. The metal constituting the barrier layer 54 is not particularly limited, and a commonly used melting point metal such as titanium, titanium-nitrogen, titanium-tungsten or a combination thereof can be used (FIG. 5).

(F) Next, a first conductive layer 52 made of aluminum or an alloy containing aluminum as a main component is formed by, for example, a sputtering method. This first conductive waste 5

For 2, a material similar to the material constituting the first conductive i 12 can be used. Further, the barrier layer 54 and the first conductive dust 52 are patterned by a commonly used lithography technique and etching technique to form a second metal wiring layer 50. By the above-mentioned step (E) and this step (F), a contact conducting portion 56 composed of a barrier layer 54 and a first conductive layer 52 is formed in the through hole 40b (see FIG. 6).

(G) Next, a passivation layer 60 composed of SiO ₂ or the like is formed by a commonly used method (FIG. 7).

In the manufacturing method of the present embodiment including the above-described steps, the first resistive layer 30 is removed while the second conductive layer 14 constituting the first metal wiring ^ 10 is removed. Of the conductive layer 12 and the components of the etching gas and the resist debris 30 can be prevented, and as a result, a reaction product that inhibits the patterning of the second metal wiring ^ 50 Is not formed. Therefore, it is possible to avoid the occurrence of troubles such as short-circuit disconnection in the second metal wiring layer 50 as follows:

Further, the thickness of the second conductive dust 14 of the first metal wiring layer 10 is set to the above-mentioned range larger than usual, and an inert gas is added to the etching gas of the second interlayer insulating layer 20. By adopting at least one means of adding a hole, preferably both means, the difference in the depth of the through hole 40a can be cleared, that is, the deepest through hole can be formed at the shallowest through hole. It can be set so that the second conductive layer 14 remains.

Further, by performing the etching of the second interlayer insulating layer 20 and the second conductive layer 14 of the first metal wiring layer 10 in different steps, it is possible to optimize the respective etching conditions. . .

Further, in the semiconductor device shown in FIG. 7, the contact conductive portion 56 for electrically connecting the first gold wiring 10 and the second gold wiring layer 50 is formed of the first gold wiring. It is formed by removing the portion of the second conductive layer 14 having relatively high electric resistance, which constitutes the layer 10, so that the contact conductive portion 56 and the first gold bent wiring dust 10 are not formed. Contact resistance can be reduced.

(Second embodiment)

In the present embodiment, in the contact region for connecting the first metal wiring layer 10 and the second metal wiring layer 50, the second conductive layer 14 of the first metal wiring layer 10 is formed. This is different from the first embodiment in that the first embodiment is not removed. Hereinafter, the manufacturing process of the present embodiment will be described physically.

Forming a first metal wiring layer 10 on the element formation region 100 0 (A),

A step (B) of forming a two-layer insulating layer 20 and a resist layer 30 and forming a through hole 40 a in a predetermined pattern in the inter-layer insulating layer 20 (B); Since the step (C) of removing the resist layer 30 used as the mask of the layer 20 is the same as in the first embodiment, its illustration and detailed description are omitted ₍ and the first In the embodiment, in the step (D), the second conductive layer 14 constituting the first metal wiring layer 10 is etched using the second insulating layer 20 as a mask, and the first conductive layer 1 Although the through hole 40b was formed in a state where 2 was exposed, in this embodiment, the step (D) shown in Fig. 4 was not performed, that is, following the steps (A) to (C), Steps (H), (I) and (J) are performed.

(H) This step corresponds to the step (E) of the first embodiment, and a barrier layer 54 is formed on the second interlayer insulating layer 20 (FIG. 8). Manufacturing conditions and materials of barrier layer 54 Is the same as that of the first barrier layer 54.

(I) This step corresponds to the step (F) of the first embodiment, and a first conductive layer 52 mainly composed of aluminum is formed on the barrier layer 54. The method and material for forming the second conductive layer are the same as those of the first conductive layer 52 of the first embodiment.

Then, the barrier waste 54 and the first conductive waste 52 are patterned to form a second metal wiring layer 50 (FIG. 9). Then, by the step (H) and the step (I), a contact conductive portion 56 composed of the barrier layer 54 and the first conductive t 52 is formed in the through hole 42.

(J) This step corresponds to the step (G) of the first embodiment, in which a passivation layer 60 is formed on the surface of the second metal wiring layer 50 (FIG. 10). ).

The semiconductor rest having two layers of bending wiring layers 10 and 50 manufactured by the above-described process is the contact conductive part 56 of the second metal wiring 50 and the metallization of 51. The wiring M 10 is connected to the first conductive layer 12 via the second conductive dust 14. In this embodiment, although the contact resistance between the first metal wiring layer 10 and the second metal wiring layer 50 is larger than that of the semiconductor device of the first embodiment, Since there is no step (D), the number of manufacturing steps can be reduced, and the manufacturing process can be simplified. As in the first embodiment, since a reaction product that adversely affects the patterning of the second metal wiring layer 50 is not generated, a semiconductor device with high reliability and high yield is manufactured. be able to.

In the first embodiment and the second embodiment described above, the semiconductor device having two metal wiring circumferences and the manufacturing method thereof have been described. However, the present invention relates to a semiconductor device having three or more metal wiring wastes. Can be similarly applied.

In addition, the present invention is not limited to the above-described embodiments, and can take various forms within the scope of the gist of the present invention. For example, the present invention provides a method in which a barrier layer is provided in the lowermost chip of the first metal wiring layer, and a reflection preventing anti-reflection layer is formed on a conductive layer of the uppermost gold wiring layer. It is possible to adopt a configuration such as having conductive waste.

Claims

till

1. A method of manufacturing a semiconductor device including two or more gold wiring layers, the method including the following steps (a) to (d).

(a) forming at least a first conductive dust mainly composed of aluminum and a first metal wiring dust having a second conductive layer including a gold melting point having a melting point higher than that of the first conductive dust;

Request

(b) An insulating layer having electrical insulation is formed on the first metal wiring layer, a resist layer having a predetermined pattern is formed on the insulating layer, and the resist dust is masked. Forming the insulating layer while having at least a part of the second conductive layer left by patterning the insulating waste by etching the insulating waste. ,

(c) removing the resist!

(d) forming a second metal wiring layer including at least a first conductive layer containing aluminum as a main component on the H¾3 insulating layer, and forming a conductive portion in the through hole; E to electrically connect the second metal屈配line scrap the first metal wiring layer稃_t

2. In claim 1,

A step of removing the second conductive layer in a region corresponding to the through hole by performing etching using the inter-dust insulating layer as a mask following the step (c); (d) a method of manufacturing a semiconductor device.

3. In Claim 1 or 2,

In the step (c), a method for manufacturing a semiconductor device, wherein the resist is removed in a gas phase containing oxygen plasma.

4. In any of items 1 to 3,

In the method (b), the etching is performed in a phase containing a reactive gas and an inert gas.

5. In any of the S-claims 1 to 4,

A method for manufacturing a semiconductor device, wherein the second conductive layer has a thickness of 20 to 200 nm.

6. A semiconductor device including two or more metal wiring layers,

A first conductive layer mainly containing aluminum, a first metal wiring layer having a second conductive layer containing a metal having a higher melting point than the first conductive layer,

A second metal wiring debris that is located at a higher position than the first metal wiring layer and that forms at least a first conductive layer containing aluminum as a main component;

A dust insulating layer which is present between the first extra wiring layer and the second gold wiring layer, electrically insulates both, and has a through hole at a predetermined position; and

A contact conductive portion formed in a through hole of the inter-layer insulating layer, and electrically connecting the first metal wiring dust and the second metal wiring layer;

—The semiconductor device wherein the contact conductive portion is typically connected to the first conductive layer via the second conductive layer in connection with the first metal wiring layer.

7. In Claim 6,

The semiconductor device, wherein the second conductive layer has a thickness of 20 to 200 nm.