TW483112B - Method to reduce junction leakage current of borderless contact silicon nitride - Google Patents

Abstract

This invention provides a method to reduce junction leakage current of borderless contact silicon nitride. A semiconductor substrate is provides and a gate oxide layer and at least two polysilicon gate structures are formed in order on the substrate. Then, at least a spacer is formed on the at least two polysilicon gate structures and the gate oxide layer between the at least two polysilicon gate structures is removed to expose the semiconductor substrate. A silicon dioxide layer is formed on the surface of the semiconductor substrate between the two polysilicon gate structures through thermal oxidation process. A conformal silicon nitride layer is deposited on the silicon dioxide layer, the two polysilicon gate structures and the spacer to function as a borderless etching stop layer. Finally, an inner dielectric layer is formed on the conformal silicon nitride layer.

Description

483112 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for reducing the leakage current at the junction of a silicon nitride layer without a borderline contact window; in particular, it relates to a method for removing two adjacent polysilicon gate structures. The method of completely exposing the gate oxide layer to the semiconductor substrate to form a silicon dioxide layer on the exposed semiconductor substrate. 5-2 Background of the Invention: Various devices and conductive layers disposed on a semiconductor substrate in a horizontal direction are separated from each other by an insulating layer, and are electrically connected to each other by vertical interconnects. The vertical holes in contact with various devices in the substrate are called contact windows (c ο n t a c t), and the vertical holes in contact with the upper metal layer are called via windows (v i a). Whether it is a contact window or a via window, its purpose is to align this vertical interconnect with the feature area to be connected and conducted below. If the misalignment between the vertical interconnects and the characteristic regions to be connected is not present, there will be defects in the semi-conductive device and reliability problems. Therefore, in order to ensure that a vertical interconnect is within the range of the characteristic area to be connected, this characteristic area must have a large area. _ This larger area is referred to as the defined area around the vertical contact hole or via hole (b 0 r d e r). However, increasing the area of this feature area will affect the packing density of the feature area, and also affect the degree of integration of the integrated circuits on the substrate. Therefore, in order to reduce

483112 V. Description of the invention (2)-^ bQrder), technologies such as borderless contact windows (borderless…, borderless vias, etc.) have been developed ^ in response to the demand for integrated circuit integration. Oxide pad (pad is deposited by low pressure chemical vapor deposition directly on the nitride film layer on the film with internal X 1 de) as the endless boundary stop layer, due to Shen Rupo 1 Di% force (Internal Stress) Relationship, which will produce, and produce the solid deposition we need. Because of gas defects such as junction lea〇Ca 11 i〇n), and then cause the junction leakage current (a phenomenon, our a ^ age) phenomenon. In order to reduce the leakage current at the interface, the Shixi layer is used as a borderless display. The plasma-excited chemical vapor deposition method is used to deposit a nitrided gas, and the layer is terminated by the remaining time. Because the plasma is a kind of partially ionized Is dissociated, the high-energy electrons present in the paddle, the chemical reaction of the process gas, and then on the surface of the wafer with other gas molecules to undergo the dissociation / synthesis of the ideal ratio of the special film (S t 〇 〇 ichi metry) The vapor deposition process, which is more pure for films that are fed by thermal energy, often contains ^ reaction, and the deposition process is not good. In addition to the thermal energy used for deposition, lice 1 is used. In order to control the stress of the ion pair compared with its striking force, the internal stress of the film is adjusted by appropriately adjusting the electric power of the distribution slurry, so that the phenomenon of the film is deposited, but other deposition methods are also low, which reduces the COverag of the interface leakage current. , ^ Has the following disadvantages (U is caused by the step coverage (step into the inner layer of the misguided $), the window of the etching process is reduced after filling, and it is not easy to perform when filling a non-guaranteed ^ (as shown in Figure A)) Its shape covers (non-conformal) film, likely to have holes or crack

Page 5 483112 V. Description of the invention (3) The seam occurs (as shown in Figure 1B), so it is easy to cause a short circuit between the contact and the contact. Then someone used a low pressure chemical vapor deposition method to deposit a tetraethyl group. The silicate layer still has the disadvantage of shrinking the window during the etching process. 5-3 Objects and Summary of the Invention: In view of the above-mentioned background of the invention, many disadvantages of conventional methods are adopted, and the main object of the present invention is to provide a method for reducing the leakage current at the junction of the silicon nitride layer of the borderless contact window. , Remove the gate oxide layer between two adjacent polysilicon gate structures until the semiconductor substrate is completely exposed. After that, a silicon dioxide layer is formed on the exposed semiconductor substrate, and a conformal silicon nitride layer is deposited on the silicon dioxide layer, the two polycrystalline silicon gate structures, and the gap 璧 as a The borderless engraved termination layer, and finally, an inner dielectric layer is deposited on the entire semiconductor substrate. By this method, the borderless contact window silicon nitride layer is separated from the semiconductor substrate, and the thickness of the long silicon dioxide layer is thicker than the thickness of the original gate oxide layer. The structure of the silicon layer is better than the structure of the original gate oxide layer. Therefore, the stress of the semiconductor substrate can be completely relieved by the silicon nitride layer of the borderless contact window, thereby achieving an excellent effect of reducing the leakage current at the junction. _ Another object of the present invention is to provide a method for reducing the leakage current at the junction of the nitrided layer of the borderless contact window. This method does not require the formation of a tetraethyl oxalate layer on the semiconductor substrate. Therefore, the present invention reduces the borderless contact

483112 V. Description of the invention (4) The method of leakage current at the interface of the window nitride layer can increase the gapfill capability in the inner dielectric layer. Recall and save. The mechanical method is based on the flow of low current and low current. The surface is connected to the nitrogen window of the supply layer to raise silicon. Only for this mention. The surface of the electric current leak of the Ming Fafang was described above. The silicon on the upper layer was connected to reduce the contact gate of the nitrogen root window. The two gates were less broken to crystals. The oxygen is connected to the gate 闸 ο the upper shape material is connected to the bottom of the body and guided, the half of the material is thermally bonded to the structure of the structure, and the broken crystal after the gate ο more exposed to the bottom of the material After the half-shift of the body position is removed, the layers of the oxygen structure are connected to the surface of the layer, and the layers of the silicon substrate of the silicon substrate are semi-conducted. The lower pole is connected to the silicon, and the Ba layer is broken into two pieces of oxygen, which form the oxygen surface in one method. The thickness of the thick-walled layer is interstitial and the internal oxygen is composed of one or two. The knot is long and pole-shaped, and it is the most crystalline after breaking the gate. At this moment, # layer-layer boundary broken silicon marginalization is nitrogen-free and one-two is shaped. The contact layer for the co-structural nitrogen junction window is connected to hard-boundary edge-oxygen-free substrate. Houliang has to build a thick layer of layered oxygen and oxygen barriers. The original one is better than the low-oxygen lowered base of the second best one, which must be achieved. It must be clear. This material should be outside. The semi-current of the bottom fruit body is conductive to the electrical layer leakage and the silicon surface is connected to the boundary. There is no layer of low-electricity drop dielectric layer within the edge. This method can be used to increase the current bottom leakage of the top material. Half-layered dream-layered salt nitric acid window with silicon contact fill gap

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483112 V. Description of the invention (5) The purpose and many advantages of the present invention will be fully disclosed by the detailed description of the following specific embodiments and with reference to the accompanying drawings. 5-4 Detailed Description of the Invention: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited. It is subject to the scope of subsequent patent applications. Φ Referring to the second A diagram, a semiconductor is first provided. The substrate 200 is a preferred material in the present invention. Next, a thermal oxidation method, such as the Rapid Thermal Oxidation method, is reacted at about 95 0 ° C to 1100 ° C and 1 atmosphere to form a silicon dioxide oxide layer 2 1 0, which has a thickness of about 5 0 to 100 Angstroms. Referring to FIG. 2B, at least two polycrystalline silicon gate structures 2 2 0 are formed on the semiconductor substrate using a conventional process, for example, using a low-pressure chemical vapor deposition method at about 600 ° C. to 65 At 0 ° C, 0 · 3 ~ 0.6Torr, a polycrystalline silicon layer 2 2 2 is deposited, and then doped with the group 3 or 5 elements (such as filling or stone application) by thermal diffusion or ion implantation. Xi layer, and then a low pressure chemical vapor deposition method, at about 3 0 0 ° C ~ 4 0 0 ° C, 0. 1 ~ 1. OTorr atmospheric pressure deposition of a silicidation

483112 V. Description of the invention (6) Metal layer 2 2 5 (Si 1 pesticide), such as tungsten silicide (WSi), followed by low pressure chemical vapor deposition method at about 7 0 0 ° C ~ 8 0 0QC '0. 1 ~ 1. A silicon nitride layer 2 2 7 is deposited under the atmospheric pressure of OTorr, and then a photoresist layer 2 2 9 is formed on the silicon nitride layer by spin coating, and through appropriate lithography and development Step to obtain the desired gate structure pattern. Referring to FIG. 2C, by any conventional deposition method, such as a low pressure chemical vapor deposition method, a conformal dielectric layer 230 is formed on the entire semiconductor substrate including the polycrystalline silicon gate structure. The material of this dielectric layer 230 is different from that of the internal dielectric layer, so that it can not be engraved when the dielectric layer is engraved | Dielectric layer 2 3 0. In this embodiment, the material of the dielectric layer 230 is preferably nitride nitride. Referring to the second D diagram, the conformal dielectric layer 2 30 is isotropically etched by a dry etching method. In the present invention, a reactive ion etching method and a plasma mainly composed of NF are preferably used to form a gap.璧 2 3 5 is located on each side wall of the at least two polysilicon gate structures, and the gap 璧 can be used as a mask when performing heavy doping on the source and the drain. Referring to the second diagram E, the gate oxide layer located between two-phase φ adjacent gate structures is anisotropically etched by a dry etching method. In the present invention, a reactive ion etching method and a CF-based electrode are preferred. Paste to completely expose the semiconductor substrate

483112 V. Description of the invention (7) Referring to the second F diagram, the exposed semiconductor substrate is thermally oxidized. In the present invention, rapid thermal chemical vapor deposition (R apid thermal-CVD) is preferred, and SiH is used. And N20 form a silicon dioxide layer 250 at a temperature of about 80 ° C, and a thickness of about 150 to 190 angstroms. The silicon dioxide layer 2 50 is used as a conformal medium in the next step. A buffer layer between the electrical layer 260 (preferably made of silicon nitride) and the semiconductor substrate 200, in order to relieve the stress between the silicon nitride layer on the semiconductor substrate and reduce the interface leakage current. effect. With reference to the second G diagram, any conventional chemical vapor deposition method is preferred in the present invention, and the low pressure chemical vapor deposition method is preferred, with Si H 2C 1 and NΗ 3 at φ about 70 0 ° C ~ 8 0 0 ° C, 0.1 ~ 1. OTorr reacts to form a conformal dielectric layer at atmospheric pressure 2 6 0 (preferably made of silicon nitride) on the entire semiconductor substrate for a borderless etching stop And finally, any conventional chemical vapor deposition method is preferred. In the present invention, a low pressure chemical vapor deposition method is preferred, and the preferred material is tetraethyl silicate at about 6 5 0 ° C to 8 5 At 0 ° C and a pressure of about 0.1 to 5 Torr, a silicon dioxide inner dielectric layer 270 is formed on the entire semiconductor substrate. The inner dielectric layer of the silica is used as an insulating layer. In order to isolate other wiring patterns and circuit structures. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application.

Page 10, 483112 The diagrams A, B, and B are schematic diagrams of longitudinal cross-sections of a silicon nitride layer with a borderless contact window deposited by plasma-excited chemical vapor deposition. Figure G is a schematic longitudinal sectional view of each step of the method for reducing the leakage current at the junction of the silicon nitride layer of the borderless contact window of the present invention. Representative symbols of the main parts: 10 semiconductor substrate 20 gate oxide layer 30 gate electrode 40 gap wall 50 silicon nitride boundaryless 4k etch stop layer 60 inner dielectric layer 200 semiconductor substrate 210 gate oxide layer 220 polycrystalline silicon gate structure 222 polycrystalline silicon Layer 22 5 silicided metal layer 227 silicon nitride layer 229 photoresist layer 230 conformal dielectric layer 235 spacer 250 silicon dioxide layer 260 conformal dielectric layer (silicon nitride layer)

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Claims (1)

483112 VI. Scope of patent application 1. A method for reducing the leakage of a silicon nitride layer of a borderless contact window, comprising at least: providing a semiconductor substrate having a gate oxide layer and at least two polycrystalline silicon gate structures on the semiconductor substrate On the gate oxide layer; removing the gate oxide layer between the two polycrystalline silicon gate structures to expose the semiconductor substrate, and forming a silicon dioxide layer between the two polycrystalline silicon gates by an oxidation method; On the surface of the semiconductor substrate, a conformal dielectric layer is deposited on the silicon dioxide layer and the two polycrystalline silicon gate structures; and an inner dielectric layer is formed on the conformal silicon nitride layer. 2. The method according to item 1 of the patent application, wherein the thickness of the gate oxide layer is 50 to 100 angstroms. 3. The method according to item 1 of the patent application, wherein the two polycrystalline silicon gate structures each have a silicon nitride spacer. 4. The method according to item 1 of the patent application, wherein the step of removing the gate oxide layer between two adjacent gate structures is a dry etching method. 5. The method according to item 4 of the scope of patent application, wherein the dry money engraving method includes a reactive ion etching method Page 13 483112 6. Application for patent scope 6. The method according to item 5 of the patent scope, wherein the reactive ion etching method uses at least one of the following gases as the reaction gas: cf4, chf3, c2f ^ c3f8. 7. The method of claim 1 in the scope of patent application, wherein the oxidation method may be a thermal oxidation method. 8. The method of claim 7 in the scope of patent application, wherein the thermal oxidation method may be a Rapid Thermal Oxidation method. Please 0-5 11 if it is 9 degrees. 9 special r—Η The encapsulation of the thick layer of oxygen 10. The method according to item 1 of the patent application, wherein the conformal dielectric layer is a silicon nitride layer. 1 1. The method according to item 10 of the application, wherein the silicon nitride layer is formed by a chemical vapor deposition method. 1 2. The method according to item 1 of the patent application, wherein the internal dielectric layer is formed by chemical vapor deposition. 1.3. The method of claim 1, wherein the inner dielectric layer includes a silicon dioxide layer. Page 14 483112 VI. Scope of patent application 1 4. A method for reducing leakage of a silicon nitride layer in a borderless contact window, which at least includes: providing a semiconductor substrate having a gate oxide layer and at least two semiconductor substrates; A polysilicon gate structure is formed on the gate oxide layer; a silicon nitride spacer is formed on the two polysilicon gate structure sidewalls at the same time; the gate oxide layer located between the two polysilicon gate electrodes is removed to expose the semiconductor bottom Material surface; an oxide method is used to form a silicon dioxide layer on the surface of the semiconductor substrate φ between the two polycrystalline silicon gates; a conformal silicon nitride layer is deposited on the silicon dioxide layer, the two polycrystalline silicon gates And on the silicon nitride spacer; and an inner dielectric layer is deposited on the conformal nitride nitride layer by chemical vapor deposition. 15. The method according to item 14 of the scope of patent application, wherein the thickness of the gate oxide layer is 50 to 100 angstroms. 16. The method according to item 14 of the scope of patent application, wherein the step of removing the gate oxide layer located between two adjacent gate structures is a dry etching method. 17. The method according to item 16 of the patent application scope, wherein the dry etching method includes a reactive ion etching method. Page 15 6. Scope of patent application 18. If the method of the scope of patent application No. 17 & the reactive ion etching n? "Use at least one of the following gases as the reaction gas: CF4, CHF3, C2F6 And (^ 8. The method of item 14 in the scope of patent application, wherein the thickness is 150 to 190 angstroms. "20. The method of item 14 in the scope of patent application, wherein Sr iV AU lii λγ i T Nitrogenation, and openness Nitrogenation is formed every 7 layers by chemical defect i-phase deposition method. The internal dielectric layer includes the method according to item 14 of the scope of patent application, 苴, a Silicon dioxide layer. /, Τ 忒 22 · A method for reducing the non-boundary contact window nitride zeolite, ρ + includes: a method for removing electricity leakage from a silicon layer, which provides at least half a conductive substrate; forming a gate oxide layer On the semiconductor substrate; = At least two polycrystalline silicon gate structures are simultaneously formed on the two polycrystalline silicon My «on 'walls by the gate oxygen; a silicon nitride gap is formed on the sidewall of the gate ... Remove the gate between the / n αlization layer to expose the semiconductor substrate poles Forming an oxide layer to rapidly evening stone heating process in the process more than two spar Xi Page 16 483112 Page 17