JP3425849B2 - Interconnection of high density integrated circuit and method of forming conductor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high density semiconductor circuit, and more particularly to a method for forming an interconnection and a conductor in a high density integrated circuit.

[0002]

2. Description of the Related Art In semiconductor technology, the circuit density on a chip has dramatically increased, and the fine elements inside and on the surface of a semiconductor substrate have become very close to each other.
The degree of integration has also increased significantly. Recent developments in lithography technology, such as phase shift masks and self-alignment processes, have a significant effect on device scale-down and increased circuit density, and are very large with over one million sub-micron transistors. The advent of integrated circuits has caused some circuit elements to face the problem of limited electrical properties due to scale down.

One of such circuit elements is a storage cell on a dynamic random access memory chip, and the storage cell of each dynamic random access memory is usually a metal oxide field effect transistor and a capacitor. And is widely used in the electronics industry for storing data. A single dynamic random access memory stores 1 bit of data in the form of a charge in a capacitor. The metallization for contact with the semiconductor substrate is called contact metallization, and the polysilicon film of the MOS device is metallized to form the gate electrode and the interconnection inside the MOS device. If the metallization and the first layer interconnections (ie MOS on the substrate) cannot be scaled down, DRAM and other devices, eg M
It is a major obstacle in scaling down OS and bipolar devices. As the integration density of dynamic random access memory increases, the surface area of the memory decreases and the cell performance deteriorates, which is a serious obstacle. Therefore, in order to achieve high integration of a semiconductor memory, it is an object to solve a problem of forming a miniaturized first layer contact and a first layer interconnection and a problem of cell performance deteriorated thereby. Will be.

Manufacturing processes are described in relation to the following documents: (1) “CVD SiNx Anti-Reflective Coating for Sub-
0.5μm Lithography ”, TPOng et al., 1995 Symposiu
m on VLSI Technology Digest of Technical paper, (0-
7803-2602-4 / 95) p.73-74. (2) “Selective dry etching in a high density pl
asma for 0.5 complementary metal-oxide-semiconduc
tor thechnology ”, by Givens et al., Vac.Sci. Tech
nol. B12 (1), Jan / Feb 1994, p.427-432. (3) “High Selectivity Silicon Nitride Etch for
Sub-Half Micron Devices ”, by Karen Reinhard et a
l., Lam Reserch Corp., Taiwan Technical Symposium,
November 15, 1994.

[0005]

However, many prior art techniques require many manufacturing processes or planarization structures, which make the process complicated and costly. Other manufacturing methods also depended on the etching technique and the method of setting the etching depth in advance, but this type of control was quite difficult at the manufacturing site. For example, substantial or apparent gas leakage in the plasma etching process, residual vapor due to pump and load effects, etc. change the chemical etching atmosphere in the vacuum chamber, making it difficult to grasp the etching time. Was there. Therefore, it has been a problem to provide an etching technique that has a simple manufacturing process and does not require detection of the end point depth.

[0006] Therefore, there is a need to develop interconnections and conductors that reduce manufacturing costs and improve device yields, among other things, by reducing the photoresist process and maximizing yields and maximizing yields. Achieving marginal manufacturing process tolerances is required. In the process of forming the interconnection, which is a conductor, in the bit line and the contact hole by the conventional manufacturing process, two steps of photoresist and etching are required, and the conductor contact and the electrode contact are not self-aligned. and prevented miniaturization, and a thick insulating film through the co <br/> down high aspect ratio in contact holes (greater than 3)
Since it was difficult to etch the contacts due to the occurrence of defects, the yield was reduced due to poor etching. These are the problems to be solved by the present invention, and it is required to develop a manufacturing process of a scaled down interconnection capable of overcoming the lithography technology.

A main object of the present invention is to provide a method of forming interconnections and conductors of a high density integrated circuit which overcomes the limit scale of lithography technology and reduces the resist process.

Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit which forms high density contact holes and interconnections.

Another object of the present invention is to provide a method of manufacturing a dynamic random access memory device having a high density, low cost and a capacitor having a large manufacturing aperture which is easy to manufacture.

[0010]

In order to solve the above problems and achieve the above object, the present invention provides a conductor integrated circuit having high density first layer contacts and first layer interconnections. To provide a manufacturing method of
This is achieved by the following means. (1) An insulating cap film is formed on the uppermost surface to form a gate electrode having an antireflection function and an interconnection of the first layer. (2) Pattern the insulating cap film by highly selective silicon nitride etching. (3) Using the gate electrode and the insulating spacer on the first insulating film, the first and second layer substrate contacts are formed in self-alignment. Here, “on the gate electrode and the first insulating film
The structure of the “insulating spacer” will be described with reference to FIGS.
As is clear from FIG. 9, the upper insulating film is on the gate electrode side.
Second insulating wall spacer on the gate electrode through 20
34 is formed, and in the conductive structure on the insulating region side,
Is the second insulating film on the first insulating film (insulating cap film) 12.
Spacers 34 are formed.

To further explain these means, a method for forming an interconnection on a semiconductor substrate on which an active region and a wall spacer insulating region are formed is as follows.
It consists of the following steps. That is, a gate electrode having a wall spacer is provided in the active region and a conductive structure is provided on the insulating region. A first insulating cap film made of an antireflection type silicon nitride film is formed on the uppermost surface of the gate electrode and the conductive structure, and then a first insulating wall spacer made of silicon nitride is formed on the side wall of the gate electrode and the side wall of the conductive structure. To do. An upper insulating film is formed to cover the first insulating cap film on the gate electrode, and then the first polysilicon film 30, the dielectric film 26 (see FIG. 4) and the second insulating cap film are formed on the substrate. A first opening having a first sidewall is formed by patterning and etching the upper portion of the first polysilicon film, which is deposited on the entire surface and is between the second insulating film, the dielectric film, and the gate electrode, by using a resist. A second insulating wall spacer is formed on the first side wall of the first opening, the first opening is filled with the upper electrode plug to form the lower electrode plug, and the interconnection for electrically connecting to the source region is completed.

The manufacturing process of the present invention has many advantages over the prior art. First, the self-alignment process of the present invention utilizes two sets of sidewall wall spacers and is relatively wide. Since the contact opening is realized, it is advantageous for forming the contact hole. Secondly, since the insulating wall spacer has a small aspect ratio with respect to the contact hole,
Cell formation is less restricted by lithographic techniques. Furthermore, since the first and second insulating cap films improve the lithographic function by the antireflection coating, it is possible to form a contact hole having a smaller size by patterning. Thirdly, according to the method of the present invention, since the source region and the drain region can be simultaneously patterned by the same resist process, the resist process can be omitted. Fourthly, the dimensional accuracy of the contact hole and the storage cell can be improved by high selectivity and high density plasma etching.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. First, to give an overview of the present invention, the present invention provides a method for forming a reduced interconnection and a method for forming a capacitor memory cell which is small in size, high in performance, and easy to manufacture. It is provided. First, a field oxide film and a field effect transistor structure are formed, but only a brief description will be given within a range that helps understanding of the present invention. Next, as will be described later, an interconnection is patterned by using two sets of wall spacers and an antireflection type silicon nitride cap film.
The term "surface of the substrate" means the surface of each film body or the surface of a structure formed on a semiconductor substrate.

In FIG. 1, first, a transistor element (not shown) is provided in a semiconductor substrate 2, and a capacitor is formed in an active region surrounded by an insulating region 4. This insulating region 4 is a field oxide film. , Semiconductor substrate 2
It is formed above and separates the active region and the insulating region. A preferred substrate is P-type single crystal silicon having a crystal orientation of (100), and a sufficiently thick field oxide film is formed as an insulating region 4 around the active region for electrical isolation. The insulating region 4 is formed by depositing a thick silicon oxide film (oxidized pad) and a silicon nitride film as a barrier against thicker oxidation in the active region and then performing oxidation as a mask.
It is desirable to set it to 00Å.

Then, the silicon nitride film barrier and the oxide pad are removed by known wet etching, and then a semiconductor element is formed in the active region. MOSFET can be raised as an element of the dynamic type random access memory most frequently used.
First, a thin gate oxide film 3 is formed on the active region by thermal oxidation.
It is desirable that the thickness is 70 to 90Å.

Conductive film 6 which is a doped polysilicon film
The gate dielectric film 10 is deposited on the semiconductor substrate 2, and the conductive film 6 can be used as a gate electrode and polycide. The gate dielectric film 10 is formed of silicon oxide, and the thickness of the gate dielectric film 10 can be increased. 200 to 10
It can be in the range of 00Å.

Similarly, in FIG. 1, the first insulating cap film 12 is formed on the gate dielectric film 10. The first insulating cap film 12 has a junction structure as an upper layer of the gate electrode or an etching barrier. Yes, the first insulating cap film 1 formed of anti-reflection type silicon nitride
It is desirable to improve the lithographic resolution by means of an antireflection function that reduces the reflections caused by 2).
The first insulating cap film 12 made of silicon nitride is S
LPCVD by iH ₂ Cl ₂ and ammonia reaction
It is desirable to deposit it by (reduced pressure chemical vapor deposition method) and set its thickness in the range of 200 to 2000Å.
00Å is more desirable. The extinction coefficient (k) of the first insulating cap film 12 is in the range of 0.3 to 0.5, and the ratio of SiH ₂ Cl ₂ and ammonia by LPCVD is about 1: 2.
And the ratio is 1: 4, preferably 1: 3, the reaction pressure is about 100 to 500 × 10 ⁻³ Torr, 400 × 10 ⁻³ Torr is preferable, and the reaction temperature is 750 to 850 ° C. The range is set, and 780 ° C. is desirable.

The first insulating cap film 12 is also made of TEO.
The reaction temperature is adjusted to 750 to 850 with S, SiH ₄ , and NH _3.
The reaction pressure range is about 100 to 500 × 10.
^-3 Torr as SiOxNy using LPCVD
It is also possible to deposit H. First insulating cap film 1
2 is made of SiOxNyH, its thickness is about 20
The range is from 0 to 2000Å.

Next, the gate oxide film 3, the polysilicon film 6 and the gate dielectric film 1 are formed by lithography and etching.
0, the first insulating cap film 12 is formed as a gate electrode and a conductive structure. Insulating region 4 with two outer conductive structures
A word line is formed on the (field oxide film), and two inner gate electrodes are formed on the surface of the substrate to be a part of the transistor of the DRAM or other element.

A photoresist (not shown) is patterned and etched on the first insulating cap film 12 to form a gate electrode and a conductive structure. Also has a high selectivity, the first insulating cap film 12
Used for etching. This highly selective etching has two steps: main etching and over etching. The main etching pressure is set to about 280 to 320 × 10 ⁻³ Torr, the power is set to 250 to 300 W, and the electrode gap is set to 0.7.
To 0.9 μm and the flow rate of SF ₆ is 60 to 80 s
CHF ₃ flow rate is 9 to 11 sccm
And the flow rate of He is in the range of 240 to 260 sccm. In the over-etching step, the pressure is set to about 725 to 755 × 10 ⁻³ Torr and the power is set to 180.
The electrode gap is 0.9 to 1.1.
The flow rate of SF ₆ is 110 to 130 scc in the range of μm.
The flow rate of CHF ₃ is in the range of 9 to 11 sccm, and the flow rate of He is in the range of 18 to 22 sccm. By this highly selective and high density plasma etching process, it is possible to improve the accuracy of the contact hole and form a downsized interconnection. The gate dielectric film 10, the conductive film 6 and the gate oxide film 3 are
The same photomask can be used.

Next, a lightly doped source / drain (not shown) is formed in the N channel of the MOSFET, and N type ions are implanted. For example, arsenic or phosphorus is used as the gate electrode of the conductive film 6. Inject both sides,
Form lightly doped source / drain (not shown). Phosphorus P31 is used as a typical doping,
The dose amount can be set to 1E13 to 1E14 atoms / cm ² , and the energy amount can be set to 30 to 80 KeV.

In FIG. 2, the lightly doped source 1
After forming the 6, 16 / drain 14, the first insulating wall spacer 18 is formed on the side walls of the gate electrodes 3, 6, 10, 12.
Is formed by depositing silicon nitride by LPCVD, and its thickness is in the range of 200 to 1000Å.
00Å is desirable. In addition, the gate electrode 3,
The mutual distance between 6, 10, 12 is in the range of 0.25 to 0.4 μm, and the mutual distance between the first insulating wall spacers 18 is in the range of 0.2 to 0.35 μm.

The sources 16 and 16 / drain 14 of the MOSFET are formed by implanting N-type ions, for example, arsenic (As) 75, between the first insulating wall spacers 18 to make the heavily doped sources 16 and 16 (source 16 Contact electrode) / drain 14 is formed, but this doping step is usually performed through a silicon oxide film having a thickness of 200 to 300 Å to reduce the doping into the channel and to prevent metal and other impurities. To prevent pollution. Typical dose is 2E15-1E16st
and oms / cm ^2, amount of energy to inject 20-7
It is set to 0 KeV.

As shown in FIG. 3C, the upper insulating film 20 is formed on the upper surfaces of the two gate electrodes 3, 6, 10 and 12 on the inner side. The upper insulating film 20 is formed on the inner two gate electrodes. The upper surface of the upper insulating film 2 is provided to make the heights of the upper surfaces of the 3, 6, 10, and 12 and the upper surfaces of the two outer conductive structures 3, 6, 10, 12 above the insulating region 4 (field oxide film) uniform.
The thickness of 0 is preferably in the range of 100 to 1000Å, and it is desirable to form it by silicon oxide.
Although it can be produced by G, PSG, it is preferably formed by borophosphosilicate glass (BPSG).

In FIG. 3, the upper insulating film 20 is formed by the following steps. As shown in Fig. 3 (a),
After the oxide film 20B is formed of TEOS, the flat film 2
The entire surface of the substrate is covered with 0A. This flat film 20
A is preferably formed of BPSG (borin silicate glass) and has a thickness of 1000 to 5500.
The range is Å. Horin silicate glass is TEO
It is formed by low pressure chemical vapor deposition (LPCVD) using S (tetraethylorhosilicate) as a reactant, and heat treatment is performed at a temperature of 850 ° C. for 30 minutes after adding boron and phosphorus in the process of forming borophosphosilicate glass. And reflow to flatten.

In FIGS. 3B and 3C, the flat film 20A made of BPSG is etched back to a thickness of 3
It is desirable to set it in the range of 500 to 4500Å. Then, a photoresist 21 is patterned on the two gate electrodes on the inner side and the two conductive structures on the outer side to form a flat film 20A.
Then, the oxide film 20B is etched to form the upper insulating film 20. The upper insulating film 20 may remain on the two outer conductive structures.
0 plays an important role, which is advantageous for realizing the planarization and the subsequent etching of the polysilicon.

In FIG. 4, other film bodies such as the second polysilicon film 22, the tungsten silicide film 24, the dielectric film 26 and the second insulating cap are formed on the surface of the semiconductor substrate 2 formed as described above. The film 28 is formed. The second polysilicon film 22 has a thickness of 1000 to 60 after etching.
It is preferably 00Å, more preferably 1500Å. The tungsten silicide film 24 is formed on the second polysilicon film 22 and increases the conductivity of the second polysilicon film 22, and is made of SiH ₄ / WF ₆ or SiC.
It is formed by depositing with l ₂ H ₂ / WF ₆ by CVD. The dielectric film 26 preferably has a thickness in the range of 500 to 2000Å, more preferably 1000Å. Then, an oxide process of TEOS, for example, TEOS (tetra
ethylorhosilicate) in a reduced pressure atmosphere at 650-7
It is preferably formed by depositing silicon oxide by chemical vapor deposition at a temperature of 50 ° C. The second insulating cap film 28 is preferably formed of silicon nitride or silicon dioxide, and an antireflection type film is deposited and formed by a low pressure chemical vapor deposition method using SiH ₂ Cl ₂ and an ammonia reaction. Cap film 2
The thickness of No. 8 is in the range of 600 to 1800Å, and the extinction coefficient (k) is in the range of 0.3 to 0.5.

Similarly, in FIG. 4, the second insulating cap film 28 and the dielectric film 26 are selectively etched to cover the source 16 with at least the remaining portion of the second polysilicon film 22. By etching the upper portion of the second polysilicon film 22, the lower electrode plug 30A and the drain contact 30B for the drain 14 are formed. In addition, the first opening 3 is simultaneously formed by this etching.
2 and the first side wall 32A are formed (this first opening 3
2 is the interconnection opening). Then, the polysilicon region 30C is formed on the insulating region 4. The second insulating cap film 28 is formed similarly to the first insulating cap film 12 by highly selective etching in the same manner as described above. By this selective etching, interconnections can be formed that are smaller than the conventional silicon nitride manufacturing process. The dielectric film 26 etches away the upper portion of the second polysilicon film 22 covering the source 16 by a well-known etching having a high selectivity with respect to polysilicon. As a result, the lower electrode plug 30 is formed on the source 16.
A is formed, and its thickness is set in the range of 0 to 7,000Å. 3
It is more desirable to set it to 000Å.

In FIG. 5, a second insulating wall spacer 34 is formed on the first side wall 32A of the first opening 32, but a second insulating film (not shown) is deposited on the surface of the semiconductor substrate 2 of FIG. Is formed by anisotropic etching. This second
The insulating wall spacer 34 is formed of silicon oxide by the TEOS process and has a thickness of 200 to 1500Å.
The range of 1000 Å is desirable.

In FIG. 6, the upper electrode plug 36 is first
The storage electrodes 30A and 36 are formed by filling the openings 32 and connecting to the lower electrode plugs 30A. The thickness of the upper electrode plug 36 is set in the range of 2000 to 10000Å,
It is desirable to set it to 7,000Å. Upper electrode plug 36
Is formed of doped polysilicon or polycide, eg, tungsten silicide, and the upper electrode plug 36
The impurity concentration of 1E19 to 1E22 atoms / cm ²
And

In FIG. 7, the capacitor dielectric film 38 is formed so as to cover the upper electrode plug 36. The capacitor dielectric film 38 is formed of a substance having a high dielectric constant and excellent continuity and no pinhole. Is possible.
The capacitor dielectric film 38 may be formed of silicon nitride, oxide / nitride / oxide (ONO) thin film, silicon oxide or silicon oxide, but is an oxide / nitride / oxide (ONO) thin film. It is preferable that the thickness is in the range of 30 to 100Å, and 55Å is preferable.
Upper electrode plug 3 by carpet type etch back
The capacitor dielectric film 38 between 6 and 36 is removed.

In FIG. 8, the upper electrode film 40 is formed on the capacitor dielectric film 38, and a doped conductive film is deposited and formed on the surface of the semiconductor substrate 2. The doped polysilicon film or the ion-implanted polysilicon film provides an appropriately doped polysilicon film.
A suitable thickness of 500-2000, 1000
Desirably Å. The upper electrode film 40 is preferably polysilicon doped with impurities, and the impurity concentration of the upper electrode film 40 / conductive film is 1E19 to 1E22a.
a toms / cm ^2, it is desirable to 1E21 atoms / cm ^2.

In FIG. 9, the DRAM cell is completed by forming the upper insulating film 50 and the metal film 52 on the upper electrode film 40.

Although the present invention has been disclosed as above with reference to the preferred embodiments, it is not intended to limit the present invention, but the idea and scope of the present invention will be understood by those skilled in the art. Since there are many formal and minor changes that can be made in
The scope of protection of the present invention is based on the claims and their equivalent descriptions.

[0035]

With the structure described above, the interconnection and miniaturized memory cell forming method according to the present invention has many advantages as compared with the prior art. In each case, as shown in FIG.
In addition, since a wide process opening can be provided by utilizing the two sets of wall spacers 18 and 34 by the self-alignment process, and the insulating wall spacer 34 of the first opening (contact hole) 32 can be formed by etching. The aspect ratio of holes can be reduced. Second, the first opening (contact hole)
Since it is not necessary to use a photoresist and a flat film for forming 32 and the film is formed by self-alignment, a smaller spectrum ratio can be obtained in removing the flattened oxide film. Thirdly, since the antireflection material is deposited by the special first and second insulating cap films 12 and 28, the lithography performance can be improved and the miniaturized contact hole can be formed. Fourth
In addition, it is possible to reduce the photoresist process,
The lower electrode plug 30 which is the source 16 and the drain 14 and three contacts by the same three photoresist process
A, upper electrode plug 36, drain contact 30B
Can be formed. Fifthly, the first opening (contact hole) 32 and the storage electrode 36,
The dimensional accuracy of 30A can be improved. Sixth, first
Since the insulating cap film 20 can provide a flat lower surface, it is advantageous for subsequent film formation and
It also contributes to the improvement of yield. Therefore, the present invention can improve the integration density and performance of an integrated circuit, reduce the number of steps, simplify the manufacturing process, reduce the cost, and improve the yield. Is of high utility value.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing formation of a gate electrode according to the present invention.

FIG. 2 is a process sectional view showing formation of a first insulating wall spacer 18 of the present invention.

FIG. 3 is a process sectional view showing formation of a first insulating cap film 20 according to the present invention.

FIG. 4 is a process sectional view showing formation of a first opening 32 according to the present invention.

FIG. 5 is a process sectional view showing formation of a second insulating wall spacer 34 of the present invention.

FIG. 6 is a process cross-sectional view showing formation of a lower electrode plug 36 according to the present invention.

FIG. 7 is a process cross-sectional view showing the formation of a capacitor dielectric film 38 according to the present invention.

FIG. 8 is a process sectional view showing the formation of an upper electrode film 40 according to the present invention.

FIG. 9 is a process sectional view showing the completion of a DRAM memory cell according to the present invention.

[Explanation of symbols]

2 Semiconductor substrate 3 Gate oxide film 4 Insulation area (field oxide film) 6 Conductive film (first polysilicon film) 10 Gate dielectric film 12 First insulating cap film 14 drain 16 sources 18 First insulating wall spacer 20 Upper insulating film 20A flat film 20B oxide film 22 Second polysilicon film 24 Tungsten silicide film 26 Dielectric film 28 Second insulating cap film 30A lower electrode plug 30B drain contact 30C Polysilicon area 32 First opening 32A First side wall 34 Second insulating wall spacer 36 Upper electrode plug 38 Capacitor dielectric film 40 Upper electrode film 50 Upper insulating film 52 metal film

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References JP-A-3-64964 (JP, A)                 JP-A-5-218332 (JP, A)                 JP-A-3-174766 (JP, A)

Claims (14)

(57) [Claims] 1. A method of forming an interconnection on a semiconductor substrate having an active region and an insulating region, comprising: a) providing a gate electrode in the active region, providing a conductive structure in the insulating region, and forming the gate. Forming a first insulating cap film made of an antireflection type silicon nitride thin film on the electrodes and the conductive structure to form an upper surface, and providing sidewalls on the gate electrode and the conductive structure; and b) forming a silicon nitride film. 1) providing an insulating wall spacer on the gate electrode as well as on the sidewalls of the conductive structure; c) the first electrode on the gate electrode such that the height of the upper surface of the gate electrode is substantially equal to the height of the upper surface of the conductive structure. 1) a step of forming an upper insulating film on the insulating cap film, and d) a second polysilicon film, tan silicide. Stacking a second insulating cap film made of a stainless film, a dielectric film, and an antireflection type silicon nitride thin film to cover the surface of the semiconductor substrate; and e) selectively etching the gate electrode and the conductive structure. The second insulating cap film, the dielectric film, the tungsten silicide film, and a part of the second polysilicon film, which are between the two, are removed to form a first opening having a first sidewall and remain. Forming a lower electrode plug from the second polysilicon film, and f) a second insulating wall spacer on the first sidewall of the first opening, and on the gate electrode and the first insulating cap film. Forming a top electrode plug to fill the first opening;
Forming the interconnection of the semiconductor substrate by connecting to the lower electrode plug, and a method of forming an interconnection and a conductor in a high density integrated circuit. 2. The gate electrode and the conductive structure are:
(1) a gate oxide film, (2) a conductive film, (3) a gate dielectric film, and (4) a first insulating cap film, and the first insulating cap film is formed by depositing antireflective silicon nitride. The ratio of SiH ₂ Cl ₂ which is a reactant by the low pressure chemical vapor deposition method to ammonia is between 2 and 4, the pressure is in the range of 100 to 500 × 10 ⁻³ Torr, and the temperature is 750 to 850. And the thickness of the first insulating cap film is in the range of 200 to 2000Å,
The method of forming interconnections and conductors of a high-density integrated circuit according to claim 1, wherein the extinction coefficient is 0.3 to 0.5 (k). 3. The first insulating cap film is silicon nitride
The upper part made of a film and covering the silicon nitride film
Insulating film is made of silicon dioxide film, the thickness of the silicon nitride film in the range of about 400～2000A, and the thickness range of 200~1000Å of the silicon dioxide film, it claim 1, wherein High density integrated circuit interconnection and method of forming a conductor. 4. The second insulating cap film is made of a silicon nitride thin film having an antireflection coating, and is made of SiH.
Together they are formed by a ₂ Cl ₂ and ammonia pressure chemical vapor deposition method as a reactant, the thickness of the second insulating cap layer in the range of 600～1800A, the extinction coefficient from 0.3 to 0.5 The method for forming an interconnection and a conductor of a high-density integrated circuit according to claim 1, wherein: 5. A method of forming a capacitor on a semiconductor substrate having an active region and an insulating region, comprising the steps of: a) forming a gate oxide film on the active region and
Covering the insulating region ; b) forming a first conductive film to cover the gate oxide film; c) forming a gate dielectric film to cover the first conductive film; d. ) Forming a first insulating cap film to cover the gate dielectric film, the step of forming the first insulating cap film with antireflective silicon nitride, and e) the gate oxide film and the first oxide film. Patterning a first conductive film, the gate dielectric film, and the first insulating cap film to form a gate electrode disposed on the active region and a conductive structure disposed on the insulating region; f) A first insulating wall spacer is formed on a side wall of the gate electrode and the conductive structure;
Forming an insulating wall spacer of silicon nitride; g) implanting impurity ions into the semiconductor substrate using the gate electrode and the first insulating wall spacer as a mask to form a heavily doped source and drain, h ) An upper insulating film is formed on the first insulating cap film on the gate electrode such that the height of the upper surface of the gate electrode is substantially equal to the height of the upper surface of the conductive structure. A step of forming a film of silicon dioxide, and i) laminating a second polysilicon film, a tungsten silicide film, a dielectric film, and a second insulating cap film to form a layer on the surface of the semiconductor substrate formed up to the previous step. Forming a second insulating cap film of anti-reflection type silicon nitride , J) the said second insulating cap layer on the source dielectric layer and the subjected to selective etching, first with a first side wall
Forming the opening and forming the second portion on the source;
Forming a lower electrode plug with the remaining second polysilicon film by etching the upper portion of the polysilicon film and forming a drain contact connecting to the heavily doped drain; and k) a second insulating wall spacer. Is formed on the first side wall of the first opening, and on the gate electrode and the first insulating cap film, and the second insulating wall spacer is formed of silicon dioxide, and l). Forming an upper electrode plug to fill the first opening,
Forming an electrical connection to the lower electrode plug to form an interconnection to the source; and m) forming a capacitor dielectric film and an upper electrode film to cover the interconnection to form a capacitor and a memory cell A step of completing the fabrication, and a method of forming an interconnection and a conductor of a high-density integrated circuit. 6. The selective etching for the second insulating cap film is high selective etching for silicon nitride, and the high selective etching includes a main etching step and an overetching step, Pressure 280-320
Power is 250 to 300 with a range of × 10 ^-3 Torr
W range, electrode gap 0.7-0.9 μm, SF ₆ flow rate 60-80 sccm, CHF ₃ flow rate 9-11 sccm, H
The flow rate of e is in the range of 240 to 260 sccm, and the pressure in the overetching step is 725 to 7
The range is 55 × 10 ^-3 Torr and the power is 180-2.
In the range of 00 W, the electrode gap is 0.9 to 1.1 μm
_6. The flow rate of SF ₆ is in the range of 110 to 130 sccm, the flow rate of CHF ₃ is in the range of 9 to 11 sccm, and the flow rate of He is in the range of 18 to 22 sccm. High density integrated circuit interconnection and method of forming a conductor. 7. A method of forming an interconnection on a semiconductor substrate having an active region and an insulating region, comprising the steps of: a) forming a gate oxide film on the active region and
Covering the insulating region ; b) forming a first conductive film to cover the gate oxide film; and c) forming a gate dielectric film to cover the first conductive film. Forming the gate dielectric film of silicon dioxide; and d) forming a first insulating cap film to cover the gate dielectric film, the first insulating cap film being formed of anti-reflection silicon nitride. And e) patterning the gate oxide film, the first conductive film, the gate dielectric film, and the first insulating cap film to form a gate electrode on the active region and on the insulating region. forming a arranged conductive structure, f) the first insulating wall spacers are formed on sidewalls of the gate electrode and the conductive structure, the first insulating War Spacers and forming a silicon nitride, a first insulation
An edge cap film is formed to cover the surface of the semiconductor substrate,
One, there is anisotropically etching the first insulating cap film <br/> by highly selective etching, the high selectivity etch provided with a main etch process and the over-etch process, the pressure of the main etch process In the range of 280 to 320 × 10 ⁻³ Torr, the power in the range of 250 to 300 W, and the electrode gap of 0.
The flow rate of SF ₆ is 60 to 80 with the range of 7 to 0.9 μm.
The flow rate of CHF ₃ is 9 to 11 sccc in the sccm range.
m, the flow rate of He is in the range of 240 to 260 sccm, the pressure of the over-etching process is in the range of 725 to 755 × 10 ⁻³ Torr, the power is in the range of 180 to 200 W, and the electrode gap is 0.9
To 1.1 μm, and the flow rate of SF ₆ is 110 to 13
The flow rate of CHF ₃ is 9 to 11 sc
cm and He flow rate in the range of 18 to 22 sccm, and g) heavily doped source and drain by implanting impurity ions into the semiconductor substrate using the gate electrode and the first insulating wall spacer as a mask. And h) forming an upper insulating film on the first insulating cap film on the gate electrode so that the height of the upper surface of the gate electrode is substantially equal to the height of the upper surface of the conductive structure. a is, the steps of the upper insulating film is formed from silicon dioxide, i) a second polysilicon film, tungsten silicide film, by laminating forming a dielectric film and a second insulating cap layer, formed before step The second insulating cap film is formed of anti-reflection type silicon nitride. And step, j) subjected to selective etching to said second insulating cap film and the dielectric film on the source, the first having a first side wall
Forming the opening and forming the second portion on the source;
Forming a lower electrode plug from the remaining second polysilicon film by etching the upper portion of the polysilicon film and forming a drain contact to connect to the heavily doped drain; k) second insulating wall Forming a spacer on the first sidewall of the first opening and on the gate electrode and on the first insulating cap film, the step of forming the second insulating wall spacer from borophosphosilicate glass; L) forming an upper electrode plug to fill the first opening,
Forming an electrical connection to the lower electrode plug and forming an interconnection to the source. A method for forming an interconnection and a conductor in a high density integrated circuit, comprising: 8. The method according to claim 1, further comprising forming a capacitor dielectric film and an upper electrode film to cover the interconnection, thereby completing formation of a capacitor and fabrication of a memory cell. 4, 6, 7
A method for forming a high-density integrated circuit interconnection and a conductor according to claim 1. 9. The high density integrated circuit according to claim 1, wherein the second polysilicon film has a thickness in the range of about 1000 to 6000Å. Interconnection and conductor formation method. 10. The first insulating wall spacer is made of silicon nitride and has a thickness of about 200 to 2000Å.
The method for forming an interconnection and a conductor of a high-density integrated circuit according to any one of claims 1, 5 and 7, wherein: 11. The dielectric film has a thickness of 500 to 2
TEOS (tetra ethylorhosilica)
8. A high-density integrated circuit interface according to claim 1, characterized in that it comprises silicon nitride formed by a low pressure chemical vapor deposition (LPCVD) process using Methods of forming connections and conductors. 12. The first insulating cap film and the second insulating cap film are formed of anti-reflection type silicon nitride, and have a ratio using a reaction between SiH ₂ Cl ₂ and ammonia. Is deposited by low pressure chemical vapor deposition (LPCVD) in the range of 2 to 4,
The reaction pressure is in the range of 100 to 500 × 10 ⁻³ Torr, the reaction temperature is in the range of 750 to 850 ° C., the thickness thereof is in the range of 200 to 2000 Å, and the extinction coefficient (k) is 0.3 to 0.5. 5. The method according to claim 5, wherein
A method for forming a high-density integrated circuit interconnection and a conductor according to the description. 13. The distance between the gate electrodes is 0.25.
To 0.4 μm, and the distance between the first insulating wall spacers is in the range of 0.2 to 0.35 μm. 8. High density integrated circuit interconnection and method of forming a conductor. 14. The upper insulating film is made of borophosphosilicate glass and has a thickness of about 1000.
It is set to a range of up to 5500Å.
8. A method for forming a high-density integrated circuit interconnection and a conductor according to any one of 5 and 7.