JP2822795B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a self-aligned contact in which a contact hole for electrically connecting a wiring and a diffusion layer is formed in self-alignment with an intermediate wiring layer. .

[0002]

2. Description of the Related Art A self-aligned contact technique for forming a contact hole for electrical connection between wirings of different layers in a self-aligned manner with an intermediate wiring layer will be indispensable for reducing the size of a semiconductor integrated circuit in the future. Conceivable.

A conventional method of forming a typical self-aligned contact will be described with reference to the drawings.

As shown in FIG. 3A, after a field oxide film 2 is formed in a separation region on a P-type silicon substrate 1 by using a known selective oxidation (LOCOS) technique, a gate oxide film 3 is formed on the entire surface. A polycrystalline silicon film and a silicon oxide film serving as a gate electrode are sequentially formed, and the silicon oxide film 15 and the polycrystalline silicon film are patterned into a pattern of the gate electrode 4 by using a photolithography technique.

After that, as shown in FIG. 3B, a silicon oxide film 6 serving as an interlayer insulating film is formed on the entire surface by using a low pressure CVD method having good step coverage, and a photoresist film is formed by using photolithography. After patterning the silicon oxide film 8, the silicon oxide film 6 is patterned using anisotropic etching as shown in FIG. 3 (c), and then as shown in FIG. 3 (c) using anisotropic etching. Then, the silicon oxide film 6 is patterned to form a contact hole.

Since the wiring layer to be formed thereafter and the gate electrode are insulated by the silicon oxide film 2 previously formed on the gate electrode and the sidewall oxide film 6a formed by etching the contact hole. In the process described with reference to FIG. 3B, the margin between the mask contact and the gate electrode can be reduced to the limit of the alignment accuracy.

Another example of a conventional method for forming a self-aligned contact will be described with reference to FIG.

As shown in FIG. 4A, after a field oxide film 2 is formed in an isolation region on a P-type silicon substrate 1, a gate oxide film 3 and a polycrystalline silicon film serving as a gate electrode are formed on the entire surface. The gate electrode is patterned using a photolithography technique.

Subsequently, a silicon oxide film 6 as an interlayer insulating film, a BPSG film 7 doped with an impurity having reflow properties 7
After a silicon oxide insulating film such as a silicon oxide film is formed and heat treatment is performed, the contact hole is patterned in the photoresist film 8 using photolithography.
The first contact holes 11 are formed by etching the interlayer insulating films (7, 6) by anisotropic etching.

After removing the photoresist film 8, FIG.
As shown in FIG. 4B, a silicon oxide film 12 having good step coverage is formed on the entire surface and etched back using anisotropic etching to form a first contact as shown in FIG. An insulating spacer 13 made of a silicon oxide film is formed on the side wall of the hole 11 to obtain a second contact hole 14.

Since the insulating layer 13 insulates between the wiring layer and the gate electrode which are formed thereafter, FIG.
Masks, contacts, and contacts used in the process described with reference to
The gate margin can be reduced to the limit of the alignment accuracy as in the above-described example.

[0012]

In the first example of the above-described conventional method of forming a self-aligned contact, the silicon oxide film 15 is required on the gate electrode, so that the step due to the presence or absence of the gate electrode pattern is large. Therefore, there is a problem in that patterning of the upper wiring becomes difficult.

In the second example, since the lower layer of the wiring layer is flattened, the patterning of the wiring in the upper layer is easy. However, the depth of the contact hole is large in both the first example and the second example. As a result, when the upper layer wiring is formed by sputtering or the like, sufficient step coverage cannot be obtained when the upper layer wiring is formed using a sputtering method or the like.Therefore, the structure of the upper layer wiring and a process using such a self-aligned contact are required. There was a problem of being restricted.

[0014]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a MOS transistor on a semiconductor substrate of one conductivity type; and forming a first insulating film on the transistor. Forming a second insulating film having a film quality different from that of the first insulating film on the first insulating film and performing planarization; and opening the opening surface over the gate electrode of the transistor using a photoresist film as a mask. Forming a groove of a predetermined depth by isotropic etching so as to extend to the first contact hole by etching the bottom of the groove by performing anisotropic etching using the photoresist film as a mask. Forming a hole, removing the photoresist film, depositing a third insulating film having good step coverage, and etching back using anisotropic etching. Ko Forming a second contact hole provided with an insulating spacer on a side surface of the first contact hole by exposing a surface of the semiconductor substrate in the tact hole portion; Forming a contacting wiring layer.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1C are sectional views in the order of steps for explaining a method of forming a self-aligned contact according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a field oxide film 2 having a thickness of about 400 nm is grown on an isolation region on a P-type silicon substrate 1 by using a well-known LOCOS technique to partition an element formation region. I do. Next, ion implantation for adjusting the threshold voltage of the transistor is performed, and a thickness of about 1
A 5 nm gate oxide film 3 and a polycrystalline silicon film having a thickness of about 250 nm are formed, and the gate electrode 4 is patterned using photolithography.

Next, source / drain regions composed of N ⁻ and N ⁺ type diffusion layers are formed by using a known LDD forming technique. However, in FIG. 1A, the source / drain regions are simply shown as N-type diffusion layers 5 for convenience. Then decompression C
A silicon oxide film 6 having a thickness of about 100 nm
A BPSG film 7 having a thickness of about 250 nm is sequentially formed and is heat-treated in a nitrogen atmosphere to reflow the BPSG film and to planarize the surface. After patterning a contact on the photoresist film 8 by using a photolithography technique, a BPSG film of about 150 nm is isotropically etched using a hydrofluoric acid-based solution to form a groove 9a. BP at the bottom of groove 9a by dry etching
The first contact hole 11 is formed in the SG film 7 and the silicon oxide film 6.
Open a.

The photoresist film 8 is removed, and a silicon oxide film 9 having a thickness of about 100 nm is formed as shown in FIG. By etching back the entire surface using reactive etching, the first contact hole 1 is formed as shown in FIG.
The silicon oxide film is left as the insulating spacer 13a on the side wall 1a.

Under normal conditions for dry etching of a silicon oxide film, the etch rate of the BPSG film is about 1.5 times higher than the etch rate of the silicon oxide film, and the silicon oxide film 12 is removed at the groove 9a to remove the BPSG film 7. Since the end point can be detected at the time of exposure, the depth of the wide portion above the second contact hole 14a can be adjusted to a desired value.

In the method of forming a self-aligned contact according to the present embodiment, since the upper portion of the second contact hole can be formed in a tapered shape extending upward, it is sufficient to form the wiring layer 15 by sputtering. Step coverage can be obtained, and good contact can be realized.

FIGS. 2A to 2C are sectional views in the order of steps for explaining a method of forming a self-aligned contact according to a second embodiment of the present invention.

As shown in FIG.
As shown in FIG. 1, after a field oxide film 2, a gate oxide film 3, a gate electrode 4, and an N-type diffusion layer 5 are formed on a P-type silicon substrate 1, a silicon oxide film having a thickness of about 200 nm is formed using a low pressure CVD method. 6, a material for forming a silica film is applied so as to have a thickness of about 100 nm in a flat portion, and heat treatment is performed to flatten the surface to form a silica film 16.
The entire surface is etched back until the silica film 16 above the gate electrode is completely removed. The contact patterning is performed on the photoresist film 8 using a photolithography technique, and etching is performed using a hydrofluoric acid-based solution to completely remove a portion of the silica film where a contact is to be formed on the diffusion layer, thereby forming a groove. 9b is formed. Since the etching rate of the silica film is much higher than the etching rate of the silicon oxide film, the silicon oxide film 6 is hardly etched by this etching.

After that, dry etching is performed to obtain FIG.
As shown in (b), after opening the first contact hole 11b, an insulating spacer 13b of a silicon oxide film is formed on the side wall of the first contact hole in the same manner as in the above-described embodiment.

In the method of forming a self-aligned contact according to this embodiment, it is not necessary to perform a high-temperature heat treatment required for reflowing the BPSG film, so that diffusion of impurities in the source and drain regions of the transistor can be suppressed and the channel of the transistor can be shortened. Has the advantage of being advantageous to

[0026]

As described above, according to the method of forming a self-aligned contact according to the present invention, a first insulating film and a second insulating film are formed on a MOS transistor formed on a semiconductor substrate and planarized. After that, using a photoresist film as a mask, isotropic etching is performed so that the opening surface extends over the gate electrode where the margin between the contact and the gate is minimized, a groove is formed, and then dry etching is performed. After the first contact hole is opened by using this method, an insulating film having good step coverage is formed on the entire surface, and the first insulating film is formed on the opening surface (groove) of the first contact hole by anisotropic etching. The second contact hole having an insulating spacer on the side wall is formed by etching back until the hole is exposed, so that the depth of the steep portion of the hole becomes shallow. Then, the wiring layer is formed by sputtering. Also it is possible to secure a sufficient step coverage when deposited, there is an effect that can realize a good contact without trouble such as disconnection.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating a method of forming a self-aligned contact according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating a method of forming a self-aligned contact according to a second embodiment of the present invention.

3 (a) to 3 (c) are cross-sectional views in the order of steps, illustrating an example of a conventional method for forming a self-aligned contact.

4A to 4C are cross-sectional views in the order of steps for explaining another example of the conventional method of forming a self-alignment.

[Explanation of symbols]

 Reference Signs List 1 P silicon substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode 5 N-type diffusion layer 6 First insulating film 7 Second insulating film 8 Photoresist film 9a, 9b Groove 10a, 10b Bottom of groove 11, 11a, 11b first contact hole 12 silicon oxide film 13, 13a, 13b insulating spacer 14, 14a, 14b second contact hole

Claims (1)

(57) [Claims] A step of forming a MOS transistor on a semiconductor substrate of one conductivity type; a step of forming a first insulating film on the transistor; and a step of forming the first insulating film on the first insulating film. A step of forming a second insulating film having a different film quality from that of the film and performing planarization, and a predetermined depth by isotropic etching using a photoresist film as a mask so that an opening surface extends over the gate electrode of the transistor. Forming a groove, etching the bottom of the groove by performing anisotropic etching using the photoresist film as a mask to form a first contact hole, and removing the photoresist film. A step of depositing a third insulating film having good step coverage, and a step of exposing the surface of the semiconductor substrate at the first contact hole by etching back using anisotropic etching. Forming a second contact hole provided with an insulating spacer on a side surface of the first contact hole; and forming a wiring layer in contact with the semiconductor substrate at the second contact hole. A method for manufacturing a semiconductor device, comprising: