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TW449796B - Manufacturing method for integrated circuit module - Google Patents

Manufacturing method for integrated circuit module Download PDF

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Publication number
TW449796B
TW449796B TW089115476A TW89115476A TW449796B TW 449796 B TW449796 B TW 449796B TW 089115476 A TW089115476 A TW 089115476A TW 89115476 A TW89115476 A TW 89115476A TW 449796 B TW449796 B TW 449796B
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TW
Taiwan
Prior art keywords
circuit
integrated circuit
chip
manufacturing
module
Prior art date
Application number
TW089115476A
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English (en)
Inventor
Wen-Wen Chiou
Original Assignee
Chiou Wen Wen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Chiou Wen Wen filed Critical Chiou Wen Wen
Priority to TW089115476A priority Critical patent/TW449796B/zh
Application granted granted Critical
Publication of TW449796B publication Critical patent/TW449796B/zh
Priority to US10/046,208 priority patent/US6782612B2/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

五 6 發明説明（ Α7 Β7 經濟部中央梯準局員工消費合作¾%¾ 本發明係與積體電路模組之製造方法有關，特別是指 —種可有效降低制t路模組之製造成本，JL讀昇該積 體電路模組更換晶片時之修復速度之製造方法。 按’習用積體電路模組之製造流程’大體上係將已封 5裝測試完成之積體電路晶片分別組裝至一印刷電路板上， 再‘過模組測試而芫成該積體電路模組；其次，國内公告 第344853號「積體電路模组的製造方法」發明專利，其主 要係將積體電路晶片直接置於電路板上進行打線作業並封 裝該發明專利從電路板到模組成品可採一次加工流程， 相較前述之習用技術，從電路板、積體電路封裝、積體電 路測試到模組組裝及模组整體測試，必需採用多段分工製 ，而5，該發明專利之製程實較為簡單省時。然而，該發 月專利之製程，在晶片固定於電路板、打線及封裝之後才 進行電子元件之絲作業，*但料產生晶片㈣、銲線 斯裂或封裝體變形等問題，使得整個模组之不良率大增， 且該等問題產生後，因該積體電路晶片已先行封裝，故欲 修復取代不良之晶片較為不易。 、有鑑於此，中請人遂提出第87121036號「積體電路模 泊組疋版造方法」發明專利申請案，以解決前述之問題，然 -而’不論是中請人切提出之第S7121G36號_請案，或是 前逑之公告第3娜3號發明專利皆是將積體電路晶片直 電路板上進行打線作業’因此，整塊電路板必須作 f別處理，使電路板场植之模组線路可穩固地與銲線連 接，例如，若以金質銲線作為電性連接橋樣時電路板與 ：^丨·:---Γ 製--- (請先閲讀背面之注意事項再填寫本頁) I m 11T. η -Μ.· 本紙張 規格( 經濟部中央樣準局員工消費合作社印製 44s^6 A7 ----------- B7 ______ 五、發明説明（) 鲜線連接處必須作特殊之鍍金處理，使得該電路板之製作 成本相對升高；其次，該二發明案若進行修復動作需更換 晶片時’必須將連接電路板與晶片之銲線—移除，而後 取離舊有晶片、重新安裝新的晶片，再進行打線作業，因 5此’更換晶片之效率往往不高；此外，在移除銲線之過程 中’有相當的可能性會發生電路板之鍍金處理被剝除破壞 之情形’使得該電路板無法重覆使用，因此，更換晶片之 動作需相當小心，更加影響更換晶片之速度；再者，該二 發明案或可採用覆片（flip chip)技術使晶片與電路板電性 10 連接’以排除前述打線方式之缺點，然而不論採用打線技 街或覆片技術來連接電路板與晶片，一但晶片受絕緣樹脂 封裝包覆之後’更換修復即相當不易，嚴重影響晶片更換 之速度。 緣此，本發明之主要目的在於提供一種積體電路模組 15 之製造方法’其電路板不需作特殊處理，以降低該電路板 之製造成本者。 本發明之又一目的在於提供一種積體電路模組之製造 方法’可有效提昇更換晶片時之速度者。 本發明之又一目的在於提供一種積體電路模組之製造 20 方法，進行修復動作需更換晶片時，可確保該電路板不致 破壞，以供重覆使用者。 本發明之再一目的在於提供一種積體電路模組之製造 方法，縱使晶片受樹脂保護封裝，仍可有效提昇更換晶片 時之速度者。 -4- $蘇尺^適用中國囷家標準(CNS)A^?i& (2〗OX29h>t) (請先閲讀背面之注意事項再填寫本頁) 装. 本 經濟部中央橾準局®：工消費合作社印黎 44^796 Λ7 ___B7__________ 五、發明説明（ ) — '—~ ^ 為達成上述之目的，本發明所提供之一種積體電路模 組之製造方法，包含有下列步驟：（A)取用一電路板，其具 有至少一模組電路，且該模組電路具有至少一晶片裝配區 及一電子元件裝配區；（B)取用至少一承載板，其具有一連 5接電路’將該承載板組裝至該晶片裝配區，使該連接電路 與該模组電路電性連接；（C)取用至少一積體電路晶片，將 該晶片組裝至該承載板上’使該晶片與該連接電路電性連 接。 為使審查委員能詳細暸解本發明之實際製造步驟及 1〇特點，茲列舉以下實施例並配合圖示說明如后，其中： &第一圖係本發明一較佳實施例之流程圖； ^弟二圖至第八圖係本發明一較佳實施例各個製造流程 之結構示意圖。 請先參間各圖式’本發明積體電路模組之製造方法之 15 一較佳實施例包含有以下之步驟： (A)首先取用一電路板（10)，該電路板（1〇)係可為塑 勝、破璃纖維、強化塑膠、陶瓷·.等材質所製成之單層或 多廣電路板，其頂面佈設有預定數目之模組電路（12)，各 該模組電路（12)具有若干積體電路晶片裝配區（14)及一電 20子元件裝配區（16)，用以供預定數量及型態之電子元件（2〇) 組裝，使各該電子元件（20)與該模組電路（12)可電性連接； 其〜’可將該電路板（10)進行切割作業，用以將該電路板（1〇) 切割成多數個具有單一模組電路（12)之電路板(22)，如第二 圖所示。 -5- 適用中國财CNS) A4規格（2丨-- (請先閱讀背面之注意事項再填寫本頁) -裝. 訂 線 449796 A7 B7 ~ ~ " - " ~~~ 1 1 *' """"" 五、發明説明（） (B)其次，取用預定數量之承載板（23) ’該承載板(23) 係可由任何型態之單層或多層電路板所製成，該承載板(23) 之頂面佈設有一經特殊鍍金處理之連接電路（23a)，且該承 載板(23)之周緣設有多數連通該承載板(23)頂、底面之半圓 5 柱形貫孔(23c)，各個貫孔(23c)係分別對應該連接電路(23a) 之各個接線端，該承載板(23)係固置於該電路板（10)之晶片 裝配區（14)，且裝配時係利用銲錫（23d)或導電膠等具有導 電性之物皙，埴設於各該.貫孔（23c)中，俾以電性連接該模 組電路（12)及該承載板(23)之連接電路(23a)，如第三及第四 10 圖所示。 (請先聞讀背面之注意事項再填寫本頁) .裝· 15 經濟部中央標隼局貝工消費合作社印製 20 (c)取用預定數量之積體電路晶片（24)，各該晶片（24) 之頂面具有預定數目之銲墊(26)’作為該晶片（24)與外界電 性連通之輸出/輸入介面，各該晶片（24)係可藉由環氧樹 脂、梦樹脂、雙面膠帶…等黏性材料，而黏著固定於各該 承載板(23)之頂面’如第五圖所示；而後，進行打線作業 (WireBounding) ’藉由金質銲線(30)將各該銲墊(26)與該連 接電路（23a)連接起來’使各該晶片（24)與該模組電路（12) 及各該電予元件(20)可電性連通’而初步完成整個積體電 路模組之組裝，如第六及第七圖所示。 (D)待上述之步驟完成之後，即可針對該模組電路單元 (22)作組裝後之實際功能測試’測試時可直接針對整個$ 组之實際功能是否優良先行測試’若整個模組之功能運作 正常，即可進行下一個製程，若整個模組之功能運作不正 常’可再針對各該電子元件（20)本身、各該電子元件^ -6-
*1T 〇 本紙張尺度適用中國國家標準（CMS ) A4规格（210X297公釐> ~ '·~~· --- 449790 A7 B7 五、發明説明（） 與該模組電路（12)之連接、各該晶片（24>本身以及各該晶片 (24)與該連接電路(23a)之連接等項目作進一步之測試，速 進行修復更換之動作，以確保整個模組之功能運作正常。 其次，待上述之步驟完成後，可利用一蓋體遮蓋罩覆於該 5 承載板周緣’以保護該晶片’如第八圖所示’本實施例係 直接利用内部組裝有光學鏡片（31)之鏡頭座（32)，直接罩覆 於該承載板(23)之周緣，而達成保護該晶片之目的，或者， 可利用環氧樹脂、矽樹脂、丙稀酸樹脂…等絕綠材料將各 該晶片（24)本身及各該晶片（24)與該連接電路(23a)之連接 10處包覆起來’即可得到完整之積體電路模組成品。 由以上之陳述可知，本發明積體電路模組之製造方法 除了可解決前揭習用技術之缺點外，本案與及國内公告第 -3 344853號發明專利及第87121036號申請案相較，更具有 以下之優點： 15 h本案係藉由一承載板(23)供晶片（24)裝配打線，作為 經濟部中央標率局員工消費合作社印掣 晶片（24)與該電路板（1〇)之間之連接橋樑，因此該電路板 (1〇)不需作鍍金或其他特殊材質處理，而該承載板(23)需作 特殊鍍金（或其他特殊材質）處理之連接電路（23a)部分，可 控制在相當小面積之下，且製作時，可積集於一面積較大 20 之電路板上完成後再切割，以節省工時及成本》 2.本案進行功能測試若發現各該晶片（24)損壞，或者銲 線(30)斷裂時’可於該承載板(23)頂面進行修復之動作；其 次’在移除舊有銲線之過程中，若不慎發生該承載板(23) 連接電路(23a)之錄金處理被剝除、破壞之情形，致使該承 -7- 本纸張尺度適用中國國家裙準（CNS ) 規格（2〗0X297公釐} 6五、發明説明（） 10 15 A7 B7 鯉濟部中央標準局員工消費合作社印製 載板(23)典法供新的晶片打線安裝時，因第承載板(23)係利 用靜羞(总4)表.兔氣著教蘊電路板上乂柳，利用現行之除 今、…回焊·技術’可在不破壞該電路板之情形之下，輕易地 將該承載板(23)自該電路板（10)上取離，以便更換一新的承 載板於該電路板之原有位置上，供新的晶片打線安裝，換 吞之’本案可直接進行更換承載板之修復動作，以解決習 用技術，必須將銲線及晶片--移除，致修復動作效率不 问之缺點，更且，進行更換晶片之修復動作時，可確保該 電路板不致破壞，以供重覆使用者。 3.本案進行功能測試若發現各該晶片（2 4)損壞時，縱使 晶片已先行樹脂保護封裝，如前所述，可直接更換一新的 承載板與一新的晶片，以解決習用技術晶片樹脂封裝後更 換不易、影響修復速度之缺點。 此外事請人在此必須特別說明的是’前述之電路板 切割作業，亦可待整個晶片裝配、測試完成後再進行，以 便業者可於一較大面積之電路板上同時進行數個模組之組 裝，其次，於電路板上组裝電子元件之步驟，亦可待整個 卵片裝配芫成後再進行，此等電路板切割或裝配電子元件 步驟上之前後調整，並不影響本發明所能達成之功效；再 者，本實施例中係採用貫孔技術電性連接該承載板(23)與 電路板（10)，惟，此僅為本發明明之一較佳實施態樣，並 非用以限制該電路板（1〇)與該承載板（23)之電性連接方 式，此外，本實施例中係利用打線技術電性連接該晶片（24) 與該承載板(23)，然而，實際製作時，亦可採用覆片技術 -8- 卜紙張尺度適用中國國家榡準（CNS ) A4規格（210Χ29·7公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 、?τ 449796 A7 B7 五、發明説明（） 來電性連接該晶片與該電路板，並不會影響本發明所能達 成之功效。 综上所陳，本發明積體電路模組之製造方法確實具有 上述之優點，足以解決習用技術之缺點，故本追加發明之 5 實用性與進步性當毋庸置疑，今為保障申請人之權益，遂 依法提出追加發明專利申請，祈請審查委員詳加審查， 並早曰賜准本案專利，則為申請人是幸。 (請先閱讀背面之注意事項再填寫本頁) -55 ‘9- 經濟部中央標準局員工消費合作社印掣 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部中央標準局員工消費合作社印製 449796 A7 B7五、發明説明（） 圖式之簡單說明： 第一圖係本發明一較佳實施例之流程圖； 第二圖至第八圖係本發明一較佳實施例各個製造流程 之結構示意圖。 5 元件圖號說明 (10)電路板 (12)模組電路 _(14)積體電路晶片裝配區 (16)電子元件裝配區 10 (20)電子元件 (22)模组電路單元 (23)承載板 (23a)連接電路 (23c)貫孔 (23d)銲錫 (24)晶片 (26)銲墊 (30)銲線 (31)鏡片 15 (32)鏡頭座 附件一：國内公告第344853號「積體電路模組的製造方 法」發明專利公告影本。 附件二：國内申請第87121036號「積體電路模組之製造方 20 法」發明專利公告影本。 本紙張尺度適用中國國家標準（CNS ) Α4規掊（210X 297公釐） ί請先鬩讀背面之注意事項再填寫本頁) .装. 訂 '線'

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  1. ABCD 449 79 6 六、申請專利範圍 1. 一種積體電路模組之製造方法，包含有下列步驟： {請先閲讀背面之注意事項再填寫本頁) (A) 取用一電路板，其具有革少一模組電路，且該模组 電路具有至少一晶片裝配區及一電予元件裝配區； (B) 取用至少一承載板，其具有一連接電路，將該承載 5 板組裝至該晶片裝配區*使該連接電路與該模組電路電性 連接； (C) 取用至少一積體電路晶片，將該晶片組裝至該承載 板上，使該晶片與該連接電路電性連接。 2. 依據申請專利範圍第1項所述之積體電路模組之製 10 造方法，其中該步驟（C)之後，更包含有一遮蓋保護該晶片 之步驟者。 '-3.依據申請專利範圍第2項所述之積體電路模组之製 造方法，其中該遮蓋保護該晶片之步驟，係利用一蓋體罩 設於該承載板周緣，以保護該晶片者。 15 4.依據申請專利範圍第3項所述之積體電路模組之製 造方法，其中該蓋體中更固設有一光學鏡片者。 5.依據申請專利範圍第2項所述之積體電路模組之製 造方法，其中該遮蓋保護該晶片之步驟，係利用絕緣樹脂 封裝包覆該晶片者。 經濟部智慧財產局員工消費合作社印製 20 6.依據申請專利範圍第1項所述之積體電路模組之製 造方法，其中該步驟（C)之前，更包含有一取用至少一電子 元件，並將其組裝至該電子元件裝配區，使該電子元件得 與該模组電路電性連接之步驟者。 7.依據申請專利範圍第1項所述之積體電路模組之製 -11- 本紙張尺度適用令國國家標準（CNS ) A4規格（2丨0乂297公釐） ^ ^9,79 6 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8六、申請專利範圍 造方法，其中該步驟（c)之後，更包含有一取用至少一電子 元件，並將其组裝至該電子元件裝配區，使該電子元件得 與該模組電路電性達接之步驟者。 8. 依據申請專利範圍第1項所述之積體電路模組之製 5 造方法，其中該步驟（C)之前更包含有一切割步驟，用以將 該電路板切割成具有早一模組電路之電路抵者。 9. 依據申請專利範圍第1項所述之積體電路模組之製 造方法，其中該步驟（C)之後更包含有一切割步驟，用以將 該電路板切割成具有單一模組電路之電路板者。 10 10.依據申請專利範圍第1項所述之積體電路模组之製 造方法，其中該承載板，具有一頂面及一底面，該頂高佈 設有該連接電路，且該承載板具有至少一連通該頂面連接 電路與該承载板外界之貫孔，當該承載板組裝至該晶片裝 配區時，該貫孔係可連通該模組電路及該連接電路，並可 15 供導電物質填設，俾以電性連接該連接電路與該模組電路 者。 '11.依據申請專利範圍第10項所述之積體電路模組之 製造方法，其中該導電物質係為銲錫者 12.依據申請專利範圍第10項所述之積體電路模組之 20 製造方法，其中該導電物質係為導電膠者。 13·依據申請專利範圍第10項所述之積體電路模組之 製造方法，其中該貫孔係貫穿該承载板之頂、底面，且位 於該承載板之周緣者。 '14.依據申請專利範園第1項所述之積體電路模組之製 -12- (請先閱讀背面之注意事項再填寫本頁) ¥ 訂 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 2?7公釐） 449796 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 申請專利乾圍 造方法，其中該步驟（c)係利用打線技術，藉由金屬銲線而 電性連接該晶片與該承載板之連接電路者。 ‘15.依據申請專利範圍第1項所述之積體電路模組之製 造方法，其中該步驟（C)係利用覆片技術而電性連接該晶片 5 與該承載板之連接電路者。 -13- 矣紙張尺度適用中國國家標準（CNS )八4^格（210X297公釐） (請先間讀背面之注意事項再填寫本頁)
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