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KR100220154B1 - 반도체 패키지의 제조방법 - Google Patents

반도체 패키지의 제조방법 Download PDF

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Publication number
KR100220154B1
KR100220154B1 KR1019960009774A KR19960009774A KR100220154B1 KR 100220154 B1 KR100220154 B1 KR 100220154B1 KR 1019960009774 A KR1019960009774 A KR 1019960009774A KR 19960009774 A KR19960009774 A KR 19960009774A KR 100220154 B1 KR100220154 B1 KR 100220154B1
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lead
semiconductor chip
package
molding
semiconductor
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KR1019960009774A
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KR970072358A (ko
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허영욱
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김규현
아남반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명은 반도체패키지의 제조방법 및 구조에 관한 것으로, 반도체칩의 저면을 외부로 노출시켜 회로동작시 발생되는 열방출의 효과를 극대화하여 패키지의 수명을 연장시키고, 신뢰성을 향상 시킴은 물론, 패키지의 몰딩부 외측에 위치한 리드는 절단하고, 몰딩부 내측에 위치한 리드는 그 저면을 외부로 노출시켜 마더보드에 실장시 리드의 저면에서 신호전달을 하도록 함으로서 실장면적을 최소화 할 수 있는 반도체패키지이다.

Description

반도체패키지의 제조방법
제 1 도는 일반적인 반도체패키지의 구조를 보인 단면도
제 2 도는 본 발명에 적용되는 리드프레임을 도시한 평면도
제 3a 도 내지 제 3e 도는 본 발명의 제조 공정도
제 4a 도 내지 제 4d 도는 본 발명의 실시예에 의한 제조 공정도
제 5 도는 본 발명에 의한 반도체패키지의 저면도
제 6 도는 본 발명의 리드를 도시한 확대도
* 도면의 주요부분에 대한 부호의 설명
10 : 반도체칩 20 : 리드프레임
21 : 리드 30 : 와이어
41 : 액상봉지재 42 : 컴파운드
본 발명은 반도체패키지의 제조방법에 관한 것으로, 더욱 상세하게는 반도체칩의 저면을 외부로 노출시켜 회로동작시 발생되는 열방출의 효과를 극대화하여 패키지의 수명을 연장시키고, 신뢰성을 향상시킴은 물론, 패키지의 몰딩부 외측에 위치한 리드는 절단하고, 몰딩부 내측에 위치한 리드는 그 저면을 외부로 노출시켜 마더보드에 실장시 리드의 저면에서 신호전달을 하도록 함으로서 실장면적을 최소화 할 수 있는 반도체패키지의 제조방법에 관한것이다. 일반적으로 반도체패키지는 제 1 도에 도시된 바와 같이, 리드프레임의 칩탑재판(2a)상에 에폭시 어드히시브(Epoxy Adhesive)를 도포하여 반도체칩(1)올 접착시키고, 반도체칩(1)상의 칩패드와 리드프레임의 리드(2)를 와이어(3)로 본딩한 후, 컴파운드(4)로 몰딩하여 반도체패키지를 제조하였다. 그러나, 이러한 구조는 컴파운드(4) 외부로 리드(2)를 노출시켜 소정의 형태로 리드(2)를 절곡하여 입출력 단자로 사용하있으므로, 외부로 노출된 리드(2)에 충격이 가해져 쉽게 변형되는 이유로 유지 관리가 어려우며 패키지의 크기를 크게 만드는 요인이 되었다. 또한, 반도체칩(1)을 리드프레임의 칩탑재판(2a)에 접착시킬때 에폭시 어드히시브를 사용하기 때문에 에폭시와 반도체칩(1)의 인터페이스(Interface)부분에서 계면박리 및 크랙(Crack)을 발생시키는 요인이 되었던 것이다. 뿐만 아니라, 반도체칩(1)이 컴파운드(4)의 내부에 위치하기 때문에 열방출이 되지 않아 패키지의 수명을 단축시키는 등의 문제점이 있었던 것이다. 따라서, 본 발명은 이러한 문제점을 해소하기 위하여 발명된 것으로, 칩탑재판이 구비되지 않은 리드프레임으로 패키지를 제조함으로서 반도체칩과 칩탑체판과의 계면박리 및 불량을 방지하고, 패키지의 신뢰성을 향상 시킬수 있도록 된 반도체패키지 제조방법을 제공함에 그 목적이 있다. 이러한 본 발명의 목적을 달성하기 위해서는 다수의 리드가 형성되고, 상기 다수의 리드 중앙부에는 칩탑재판이 없는 리드프레임을 형성하는 단계와; 상기 리드프레임의 다수의 리드 중앙부에 반도체칩을 위치시켜 와이어본딩을 실시하는 단계와; 상기 와이어본딩된 리드, 반도체칩 및 와이어를 외부의 산화 및 부식으로 부터 보호하기 위하여 몰딩하는 단계와; 상기 단계후에 몰딩영역 외각에 위치한 리드를 절단하는 단계로 이루어 진 것을 특징으로하는 반도체패키지의 제조방법에 의해 가능하다. 이하, 본 발명을 첨부도면을 참조하여 상세히 설명하면 다음과 같다. 제 2 도는 본 발명에 사용되는 리드프레임을 도시한 평면도로서, 본 발명의 리드프레임(20)에는 반도체칩(10)이 부착되는 칩탑재판이 형성되어 있지 않은 것을 알 수 있다. 제 3a 도 내지 제 3e 도는 본 발명의 제조 공정을 나타낸 도면으로서, 제 3a 도는 칩탑재판이 없는 리드프레임(20)에 기존의 다이본딩시 반도체칩(10)이 위치되는 부분, 즉 다수의 리드(21) 중앙부에 반도체칩(10)을 위치시킨 상태를 도시한 것이고, 제 3b 도는 이와같이 반도체칩(10)이 다수의 리드(21)의 중앙부에 위치된 상태에서 와이어(30) 본딩을 실시한 상태를 도시한 것이다. 이때, 상기 반도체칩(10)은 제 7 도에 도시된 바와 같이 히터블럭(H)의 상부에 안착되는데, 이 히터블럭(H)에는 배큠 홀(V : Vacuum Hole)이 형성되고, 상기 배큠 홀(V)로 공기를 빨아들여 반도체칩(10)을 고정 지지함으로서 와이어 본딩 중에 반도체칩(10)이 혼들림을 방지하는 것이다.
이와 같이 리드프레임과 반도체칩이 와이어 본딩되면, 상기 리드프레임(20)을 운반 및 취급시에는 상기 반도체칩과 리드프레임이 와이어 본딩에 의해 서로 연결되어 있으므로 반도체칩(10)이 분리되지 않는 것이다. 제 3c 도와 제 3d 도는 와이어 본딩된 리드프레임(20)에 몰딩을 실시하여 반도체칩(10)을 외부의 산화 및 부석으로 부터 보호하는 것으로, 여기서는 액상 봉지재(41)를 사용하여 본딩한 상태를 도시한 것이다. 이때, 상기 액상 봉지재(41)가 흘러 넘치는 것을 방지하기 위하여 몰딩영역에 미리 댐(411)을 형성한 후, 액상 봉지재(41)로 몰딩을 실시하면 액상 봉지재(41)가 흘러 넘치는 것을 방지할 수 있다. 이와 같이 몰딩을 실시한 다음에는 150℃ 이상의 고온에서 수시간 노출시켜 액상 봉지재(41)를 경화시키고, 제 3e 도와 같이 몰딩영역의 외부에 위치된 리드(21)를 절단하여 반도체패키지를 완성하는 것이다. 상기 제조 공정중 몰딩을 실시할때 액상 봉지재(41)를 사용하지 않고, 액폭시 몰드 컴파운드(42)를 사용하여 제 4a 도 내지 제 4d 도에 도시된 바와같이 몰딩을 실시할 수 있는 바, 컴파운드(42)를 사용하여 몰딩을 실시할 겅우에는 몰드금형이 필요하게 되고, 몰딩잉역의 외곽으로 댐(411)을 형성할 필요는 없다. 이때에도 몰드 컴파운드(42)로 몰딩공정과 경화공정을 거친 후, 몰딩영역의 외각으로 돌출된 리드(21)를 절단하는 것이다. 이와 같은 제조공정을 거쳐 완성된 반도체패키지는 제 5 도에 도시된 바와 같이 저면에 반도체칩(10)과 다수의 리드(21)가 노출된 상태로 형성되는 것이로, 반도체칩(10)의 저면이 외부로 직접 노출되기 때문에 열방출이 우수하며, 다이본딩 공정을 거치지 않음으로서 계면박리가 발생되지 않는 것이다. 또한, 이와 같은 반도체패키지는 몰딩영역의 외각으로 위치되는 리드(21)가 없어 취급시 리드(21)가 휘거나, 손상되는 것을 방지할수 있으며, 패키지의 터미널(입출력단자) 부분이 패키지의 밑면에서 이루어짐으로 마더보드에 실장시 그 크기를 최소화 할 수 있는 것이다. 또한, 상기 반도체패키지의 저변에는 그라인드(Grind)을 실시하여 패키지의 저면에서 발생할 수 있는 플래쉬(Flash)를 제거할 수 있다. 즉, 몰딩 후에 플래쉬(몰드 찌거기)를 제거하는 플래쉬 제거단계를 추가할 수 있다. 또한, 제 6 도와 같이 본발명의 반도체패키지는 몰딩영역 외각에 위치한 리드(21)를 절단시 리드(21)의 절단을 용이하게 하기 위하여 절단되는 부위의 리드(21)에 노치(211 : Notch)를 형성할 수 있다. 이와 같은 제조방법에 의해 형성된 반도체패키지의 구조는, 저면이 외부로 직접 노출되는 반도체칩(10)과, 상기 반도체칩(10)의 외측에 위치되고 몰딩영역을 벗어나지 않으며 저변이 외부로 노출되어 저면에서 신호의 입출력이 이루어지는 다수의 리드(21)와, 상기 반도체칩(10)과 리드(21)를 연결시켜주는 와이어와, 상기 반도체칩(10), 리드(21) 및 와이어(30)를 외부 환경으로부터 보호하기 위하여 몰딩된 액상 봉지재(41) 또는 컴파운드(42)로 구성된 것이다.
여시서, 상기 액상 봉지재(41)로 몰딩할 경우에는 액상 봉지재(41)가 흘러 넘치는 것을 방지하기 위하여 몰딩영역의 외각으로 댐(411)을 형성한다. 또한, 상기 몰딩된 액상 봉지재(41) 및 컴파운드(42)는 리드(21) 및 반도체칩(10)의 상부로만 몰딩되는 것이며, 상기 반도체패키지의 저면에는 플래쉬(Flash)의 제거를 위해 그라인드(Grind)를 실시할 수 있다. 이와 같은 구성의 반도체패키지는 저면으로 반도체칩과 다수의 리드가 직접 노출되므로 열방출이 우수하며 계면박리가 발생되지 않고, 몰딩영역의 외각으로 위치되는 리드가 없어 취급시 리드가 휘거나, 손상되는 것을 방지할수 있으며, 패키지의 터미널(입출력단자) 부분이 패키지의 밑면에서 이루어짐으로 마더보드에 실장시 그 크기를 최소화 할 수 있는 잇점이 있다.

Claims (3)

  1. (정정) 다수의 리드가 형성되고, 이 다수의 리드 중앙부에는 칩탑재판이 없는 리드프레임을 제공하는 단계와; 상기 리드프레임의 다수의 리드중앙부에 반도체칩을 위치시키되, 상기 반도체칩은 배큠 홀(VacuumHole)이 형성된 히터블럭에 안착시킨 후, 상기 배큠 홀로 공기를 빨아들여서 반도체칩을 지지 고정한 상태에서 와이어본딩을 실시하는 단계와; 상기 와이어본딩된 리드, 반도체칩 및 와이어를 외부의 산화 및 부식으로 부터 보호하기 위하여 몰딩하는 단계와; 상기 단계후에 몰딩영역 외각에 위치한 리드를 절단하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체패키지의 제조방법.
  2. 제 1 항에 있어서, 상기 몰딩하는 단계 후에는 반도체 패키지의 저면에 그라인드(Grind)를 설치하여 플래쉬(Flash)를 제거하는 플레쉬 제거 단계를 더 포함하여서 이루어진 것을 특징으로 하는 반도체패키지의 제조방법.
  3. 제 1 항에 있어서, 상기 몰딩영역의 외각에 위치한 리드를 절단하는 단계는, 상기 리드의 절단되는 부위에 노치(Notch)를 형성하여 상기리드가 용이하게 절단되도록 한 것을 특징으로 하는 반도체패키지의 제조방법.
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