KR100233860B1 - 반도체 패키지 및 그 제조방법 - Google Patents
반도체 패키지 및 그 제조방법 Download PDFInfo
- Publication number
- KR100233860B1 KR100233860B1 KR1019960009775A KR19960009775A KR100233860B1 KR 100233860 B1 KR100233860 B1 KR 100233860B1 KR 1019960009775 A KR1019960009775 A KR 1019960009775A KR 19960009775 A KR19960009775 A KR 19960009775A KR 100233860 B1 KR100233860 B1 KR 100233860B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- package
- lead
- heat sink
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 14
- 238000000465 moulding Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 9
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 239000002390 adhesive tape Substances 0.000 abstract 1
- 239000004593 Epoxy Substances 0.000 description 7
- 238000005452 bending Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000032798 delamination Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (4)
- 반도체 칩이 안착될 위치를 중심으로 외측에 위치되며 내측이 하부로 절곡되고, 다시 반도체 칩이 안착될 방향으로 수평 절곡된 다수의 리드 저면에 일체의 자외선 테이프를 접착하는 단계와, 상기 다수의 리드 내측 중심인 자외선 테이프의 상면에 상기 리드와 일정 거리 이격된 채 반도체 칩을 접착하는 단계와, 상기 반도체 칩 상부에 구비된 반도체 칩 패드와 상기 리드를 와이어 본딩하는 단계와, 상기 반도체 칩 등을 외부 환경으로부터 보호하기 위해 봉지재로 몰딩 하여 패키지를 성형하는 단계와, 상기 패키지 저면에서 자외선 테이프를 제거하는 단계로 이루어진 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제1항에 있어, 상기 단계를 거쳐 완성된 패키지의 양단 외부로 돌출된 리드를 절단하는 단계와, 상기 패키지의 저면으로 노출된 리드의 저면에 솔더볼을 부착하는 단계를 더 포함하여 이루어진 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 개방형 관통구가 형성된 히트 싱크와, 상기 히트 싱크의 개방형 관통구 내부의 저면에 안착된 반도체 칩과, 상기 히트 싱크 상면 외측에 접착제로서 접착되어진 리드와, 상기 반도체 칩 상에 구비된 반도체 칩 패드와 리드를 연결하는 와이어와, 상기 반도체 칩, 와이어, 리드 및 히트싱크를 외부 환경으로부터 보호하기 위해 감싸되, 상기 반도체 칩 및 히트싱크의 저면은 외부로 노출되도록 한 봉지재를 포함하여 이루어진 반도체 패키지.
- 개방형 관통구가 형성되고 상면 외측에 접착제로 리드가 접착된 히트 싱크 저면에 자외선 테이프를 접착시키는 단계와, 상기 히트 싱크의 개방형 관통구 저면의 자외선 테이프에 반도체 칩을 안착시키는 단계와, 상기 반도체 칩 상에 구비된 반도체 칩 패드와 리드를 와이어 본딩하는 단계와, 상기 반도체 칩 등을 봉지재로서 몰딩 하여 패키지를 성형하는 단계와, 상기 패키지 저면에서 자외선 테이프를 제거하는 단계로 이루어진 것을 특징으로 하는 반도체 패키지의 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960009775A KR100233860B1 (ko) | 1996-04-01 | 1996-04-01 | 반도체 패키지 및 그 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960009775A KR100233860B1 (ko) | 1996-04-01 | 1996-04-01 | 반도체 패키지 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970072359A KR970072359A (ko) | 1997-11-07 |
KR100233860B1 true KR100233860B1 (ko) | 1999-12-01 |
Family
ID=19454814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960009775A Expired - Lifetime KR100233860B1 (ko) | 1996-04-01 | 1996-04-01 | 반도체 패키지 및 그 제조방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100233860B1 (ko) |
-
1996
- 1996-04-01 KR KR1019960009775A patent/KR100233860B1/ko not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR970072359A (ko) | 1997-11-07 |
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