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TW202504102A - 具有含超晶格之偏置源極/汲極摻雜物阻擋結構之奈米結構電晶體及相關方法 - Google Patents

具有含超晶格之偏置源極/汲極摻雜物阻擋結構之奈米結構電晶體及相關方法 Download PDF

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TW202504102A
TW202504102A TW113110756A TW113110756A TW202504102A TW 202504102 A TW202504102 A TW 202504102A TW 113110756 A TW113110756 A TW 113110756A TW 113110756 A TW113110756 A TW 113110756A TW 202504102 A TW202504102 A TW 202504102A
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semiconductor
superlattice
adjacent
layer
silicon
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東琿 康
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美商安托梅拉公司
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Abstract

一種半導體元件可包括一底材及該底材上隔開的閘極堆疊，該些閘極堆疊間界定出相應的溝槽。每個閘極堆疊可包括交替的第一半導體材料層及第二半導體材料層，其中該些第二半導體材料層界定出多個奈米結構。該半導體元件可進一步包括該些溝槽內部相應的源極/汲極區、與該些第一半導體材料層橫向末端相鄰的相應絕緣區，以及與該些奈米結構橫向末端相鄰並從相鄰的該些絕緣區之表面向外偏置之相應摻雜物阻擋超晶格。每個摻雜物阻擋超晶格可包括複數個堆疊之層群組，其中各層群組包括界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。

Description

具有含超晶格之偏置源極/汲極摻雜物阻擋結構之奈米結構電晶體及相關方法
本發明一般而言涉及半導體元件，更具體而言，涉及包含奈米結構之金氧半導體(MOS)元件及其相關方法。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件效能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致效能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與／或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘極上的電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其N型通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部份(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,934號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個阻障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一阻障區各係由厚度範圍大致在二至六個交替之SiO2／Si單層所構成。阻障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上出版的應用物理及材料科學及製程(Applied Physics and Materials Science & Processing) pp. 391 – 402中，Tsu於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice, SAS)。此矽／氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電致發光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種(adsorbed species) 及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1 nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol. 89, No. 7 (2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
授予Wang等人之美國專利第7,105,895號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一阻障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層／阻障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公開之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙 (aperiodic photonic band-gap, APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
除此之外，授予Wang等人的美國專利第6,376,337號揭示一種用於製作半導體元件絕緣或阻障層之方法，其包括在矽底材上沉積一層矽及至少一另外元素，使該沉積層實質上沒有缺陷，如此實質上無缺陷的磊晶矽便能沉積於該沉積層上。做爲替代方案，一或多個元素構成之一單層，較佳者為包括氧元素，在矽底材上被吸收。夾在磊晶矽之間的複數絕緣層，形成阻障複合體。
儘管已有上述方法存在，但為了實現半導體元件效能的改進，進一步強化先進半導體材料及處理技術的使用，是吾人所期望的。
一種半導體元件可包括一底材及該底材上複數個隔開的閘極堆疊，該些閘極堆疊間界定出相應的溝槽。每個閘極堆疊可包括交替的第一半導體材料層及第二半導體材料層，其中該些第二半導體材料層界定出多個奈米結構。該半導體元件可進一步包括該些溝槽內部相應的源極/汲極區、與該些第一半導體材料層橫向末端相鄰的相應絕緣區，以及與該些奈米結構橫向末端相鄰並從相鄰的該些絕緣區之表面向外偏置(offset outwardly)之相應摻雜物阻擋超晶格。每個摻雜物阻擋超晶格可包括複數個堆疊之層群組，其中各層群組包括界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。
在一示例實施方式中，該半導體元件可在每個奈米結構與相鄰的摻雜物阻擋超晶格之間進一步包括相應之一半導體緩衝層。在某些實施方式中，該半導體元件可在該底材與該些源極/汲極區之間亦包括相應之一橫向底部摻雜物阻擋超晶格，每個橫向底部摻雜物阻擋超晶格包括複數個堆疊之層群組，其中各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。
做爲示例，該第一半導體材料可包括矽鍺，且該第二半導體材料可包括矽。亦做爲示例，該些源極/汲極區可包括摻磷矽(Si:P)，該些基底半導體單層可包括矽，且該些非半導體單層可包括氧。
一種用於製造一半導體元件之方法可包括，在一底材上形成複數個隔開的閘極堆疊，該些閘極堆疊間界定出相應的溝槽。每個閘極堆疊可包括交替的第一半導體材料層及第二半導體材料層，其中該些第二半導體材料層界定出多個奈米結構。該方法可進一步包括在該些溝槽內部形成相應的源極/汲極區、形成與該些第一半導體材料層橫向末端相鄰的相應絕緣區，以及形成與該些奈米結構橫向末端相鄰並從相鄰的該些絕緣區之表面向外偏置之相應摻雜物阻擋超晶格。每個摻雜物阻擋超晶格包括複數個堆疊之層群組，其中各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。
在一示例實施方式中，該方法可進一步包括在每個奈米結構與相鄰的摻雜物阻擋超晶格之間形成相應之一半導體緩衝層。在某些實施方式中，該方法可亦包括在該底材與該些源極/汲極區之間形成相應之一橫向底部摻雜物阻擋超晶格，其中每個橫向底部摻雜物阻擋超晶格包括複數個堆疊之層群組，各層群組包括界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。
做爲示例，該第一半導體材料可包括矽鍺，且該第二半導體材料可包括矽。亦做爲示例，該些源極/汲極區可包括摻磷矽(Si:P)，該些基底半導體單層可包括矽，且該些非半導體單層可包括氧。
茲參考說明書所附圖式詳細說明示例性實施例，圖式中所示者為示例性實施例。不過，實施例可以許多不同形式實施，且不應解釋為僅限於本說明書所提供之特定示例。相反的，這些實施例之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡。在本說明書及圖式各處，相同圖式符號係指相同元件。
一般而言，本揭示內容係有關於內部有一增強型半導體超晶格(enhanced semiconductor superlattice)以提供更佳效能之半導體元件。在本揭示內容中，增強型半導體超晶格亦可稱為MST層，或「MST技術」。
詳言之，MST技術涉及進階的半導體材料，例如下文將進一步說明之超晶格25。在先前文獻中，申請人推論本說明書所述之超晶格結構可減少電荷載子之有效質量，從而提高電荷載子遷移率。舉例而言，請參閱美國專利第6,897,472號，其全部內容在此併入成為本說明書之一部。
申請人的進一步開發證實，MST層的存在可有利地改進半導體材料中自由載子之遷移率，例如在矽與絕緣體(如SiO 2或HfO 2)之間的交界面。申請人之理論認為(但申請人並不欲受此理論所束縛)，這可能因各種機制而發生。其中一種機制為降低界面附近帶電雜質的濃度，減少這些雜質的擴散及/或捕捉雜質使其無法到達界面附近。帶電雜質會導致庫侖散射(Coulomb scattering)，進而降低遷移率。另一機制為改進界面品質。例如，從MST薄膜釋放的氧可向Si-SiO 2界面提供氧，從而減少次化學計量(sub-stoichiometric)SiO x的存在。或者，MST層對間隙子(interstitials)的捕捉可降低Si-SiO 2界面附近的間隙矽濃度，從而降低形成次化學計量SiO x之趨勢。已知在Si-SiO 2界面處之次化學計量SiO x相對於化學計量SiO 2表現出較差之絕緣特性。減少界面處之次化學計量SiO x的量，可更有效侷限矽當中的自由載子(電子或電洞)，從而在平行於界面之電場作用下提高這些載子的遷移率，這是場效應電晶體(field-effect-transistor，「FET」)結構之標準作法。由於界面之直接影響而產生的散射稱為「表面粗糙度散射(surface-roughness scattering)」，其可經由在回火之後或在熱氧化期間因鄰近的MST層而有利地減少。
這些MST結構除了有較佳遷移率之特點外，其形成或使用之方式，亦使其得以提供有利於各種不同元件類型應用之壓電、焦電及／或鐵電特性，下文將進一步討論。
參考圖1及圖2，所述材料或結構是超晶格25的形式，其結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。超晶格25包含複數個堆疊排列之層群組45a-45n，如圖1之概要剖視圖所示。
如圖所示，超晶格25之每一層群組45a-45n包含複數個堆疊之基底半導體單層46(其界定出各別之基底半導體部份46a-46n)以及其上之非半導體單層50。為清楚呈現起見，非半導體單層50於圖1中以雜點表示。
如圖所示，非半導體單層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。「被拘束在相鄰之基底半導體部份之一晶格內」一詞，係指來自相對之基底半導體部份46a-46n之至少一些半導體原子，透過該些相對基底半導體部份間之非半導體單層50，以化學方式鍵結在一起，如圖2所示。一般而言，此一組構可經由控制以原子層沉積技術沉積在半導體部份46a-46n上面之非半導體材料之量而成為可能，這樣一來，可用之半導體鍵結位點(bonding sites)便不會全部(亦即非完全或低於100%之涵蓋範圍)被連結至非半導體原子之鍵結佔滿，下文將進一步討論。因此，當更多半導體材料單層46被沉積在一非半導體單層50上面或上方時，新沉積之半導體原子便可填入該非半導體單層下方其餘未被佔用之半導體原子鍵結位點。
在其他實施方式中，使用超過一個此種非半導體單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成爲塊狀，會是非半導體或半導體。亦即，一種材料(例如矽)之單一單層所顯現之特性，並不必然與形成爲塊狀或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，非半導體單層50與相鄰之基底半導體部份46a-46n，可使超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向即正交於堆疊方向。非半導體單層50亦可使超晶格25具有一般之能帶結構，同時有利地發揮做爲該超晶格垂直上下方之多個層或區域間之絕緣體之作用。
再者，此超晶格結構亦可有利地做爲超晶格25垂直上下方多個層之間之摻雜物及／或材料擴散之阻擋。因此，這些特性可有利地允許超晶格25為高K值介電質提供一界面，其不僅可減少高K值材料擴散進入通道區，還可有利地減少不需要之散射效應，並改進元件遷移率(device mobility)，熟習本發明所屬技術領域者當可理解。
本發明之理論亦認為，包含超晶格25之半導體元件可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為這些實施方式而實現之能帶工程，超晶格25可進一步具有實質上直接的能帶間隙，此對諸如光電元件等尤其有利。
如圖所示，超晶格25亦可在一上部層群組45n上方包含一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。頂蓋層52可包含基底半導體的2至100個之間的單層，較佳者為10至50個之間的單層。
每一基底半導體部份46a-46n可包含由 IV 族半導體、 III-V 族半導體及 II-VI 族半導體所組成之群組中選定之一基底半導體。當然， IV 族半導體亦包含 IV-IV 族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一非半導體單層50可包含由，舉例而言，氧、氮、氟、碳及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層(monolayer)」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之非半導體單層50，亦應包含層中所有可能位置未完全被佔據之單層(亦即非完全或低於100%之涵蓋範圍)。舉例來說，參照圖2之原子圖，其呈現以矽做爲基底半導體材料並以氧做爲能帶修改材料之一4／1重複結構。氧原子之可能位置僅有一半被佔據。
在其他實施方式及／或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有此處實施方式之超晶格25之半導體元件，可很容易地加以採用並實施，熟習本發明所屬技術領域者當能理解。
茲另參考圖3說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3／1／5／1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一非半導體單層50’可包含一單一單層。就包含矽／氧之此種超晶格25’ 而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖3中其他元件在此未提及者，係與前文參考圖1所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目單層之厚度。
參考圖4A-4E，現在描述用於製造結合上述超晶格結構之奈米片電晶體元件的方法，以便有利地在源極/汲極與奈米片通道層(nanosheet channel layers)之間提供摻雜物阻擋。在矽底材101上形成複數個閘極堆疊102，接着是形成源極/汲極凹槽103 (圖4A)。在圖示示例中，每個閘極堆疊102包含交替的矽(Si)奈米片104及矽鍺(SiGe)(例如，硼摻雜SiGe)層105，且矽鍺層的末端設有內間隔件(inner spacers)109 (例如，SiO 2)，但在不同實施方式中可使用不同材料。
在某些實施方式中，矽緩衝件(buffers)106a、106b可視需要分別磊晶生長在凹槽103內之奈米片104及底材101的面上(圖4B)。緩衝件106a、106b可協助在MST超晶格薄膜形成之前減輕任何表面粗糙度，從而有助於防止或減少其中的缺陷。在一示例實施方式中，緩衝件106a、106b可包含2nm或更小厚度，但在不同實施方式中可使用其他厚度。
隨後，可進行MST薄膜及頂蓋的形成(圖4C)，以在緩衝件106a上界定出超晶格125a及頂蓋層152a，並在緩衝件106b上界定出超晶格125b及頂蓋層152b (圖4D)，如上所述。 舉例而言，超晶格125a、125b可包含二或三個非半導體單層50 (例如，二或三個注氧單層(oxygen-inserted monolayers))，但在不同實施方式中可使用其他數目。
隨後，可使用硬光罩108在凹槽103內形成源極/汲極區107 (圖4D)。在圖示示例中，此係以Si:P生長來完成，但在不同實施方式中可使用其他源極/汲極材料。應注意，在圖示示例中，Si:P生長發生在頂蓋層152a、152b之上，但在某些實施方式中可省略此等頂蓋層。在去除硬光罩108 (圖4E)之後可進行額外處理步驟以完成奈米片電晶體，諸如去除矽鍺層105以形成環繞式閘極(gate-all-around，GAA)結構，其中奈米片104在源極/汲極區107之間提供複數個堆疊的通道，熟習本發明所屬技術領域者當可理解。關於GAA元件形成的更多細節提供於美國專利公開號US2022/0005926、US2022/0005927、US2022/0384600、US2022/0376047及US2023/0121774，其全部內容已讓與給本案申請人並以引用方式整體併入本說明書。應注意，在某些組構中除了奈米片104之外還可使用其他奈米結構(例如，奈米管(nanotubes))。
另外參考圖5A-5F，現在描述用於製造奈米片電晶體元件之另一示例方法。此方法始於與上述方法類似之方式，但在蝕刻溝槽103’之後，在矽奈米片104’及底材101’上進行進一步的凹槽蝕刻(圖5B)。因此，緩衝件106a’及部分緩衝件106b’在形成時，橫向地凹進內間隔件109’內部(圖5C)，同樣情況亦發生在後續MST超晶格薄膜 125a’及頂蓋層152a’，以及部分的超晶格125b’及頂蓋層152b’，如圖5D所示。源極/汲極區107’的形成(圖5E-5F)及後續處理步驟可與上文所述者類似。
應注意，在某些實施例中，可省略緩衝件106a’及/或106b’，因為額外的矽凹槽蝕刻可在不使用緩衝件的情況下提供足夠的表面平滑。此外，頂蓋層152b'的形成可做爲源極/汲極區107'形成(Si:P製程)的一部分而發生，這不會減少源極/汲極區的可用總面積。在此製程中，頂蓋層152’最終摻雜了磷(P)。此外，在某些實施例中，可視需要省略頂蓋層152a’及/或152b'。更詳細而言，在一示例實施方式中，MST及Si:P的形成可有利地在同一腔室內原位發生，此時，沒有頂蓋層的MST層仍可提供所需的阻擋能力。隨後，Si:P 107’通過硬光罩108’被暴露的部分可被蝕刻，並在其上沉積一金屬120’ (圖5F)，接着形成矽化物，以界定出接點。
雖然超晶格125a’提供與上述超晶格125a類似的摻雜物阻擋能力(亦即阻擋源極/汲極區107’中的磷與奈米片104通道層的接觸)，但本方法可提供一額外優勢，即緩衝件106a’、超晶格125a’及頂蓋層152a’不會突出至源極/汲極區107’中。做爲示例，此組構佔用的源極/汲極面積可顯著減少，在某些實施方式中約爲11-25%，但上述方法可能因損失可用的源極/汲極表面積而產生額外電阻，這在某些實施方式中可能並非所樂見的。
參考圖6A-6D，現在描述用於製造奈米片電晶體元件的習知方法。此方法始於在矽底材 61上形成複數個閘極堆疊62，隨後經由硬光罩68形成源極/汲極凹槽63 (圖6A)，如上文所述。在圖示示例中，每個閘極堆疊 62包含交替的矽奈米片64及矽鍺層65。隨後，可使用硬光罩68在凹槽63內形成源極/汲極區67及內間隔件69 (圖6B)。在圖示示例中，此係以Si:P生長來完成，但在不同實施方式中可使用其他源極/汲極材料。一金屬層70在硬光罩68及源極/汲極區 67上形成(圖6C)，接着進行矽化(silicidation)/金屬去除(圖6D)以界定出源極/汲極接點71。隨後可去除硬光罩68。
此習知方法的潛在缺點為接點70與源極/汲極區67之間存在相對小的接觸面積(亦即僅在源極/汲極區頂部)，這可能導致相對高的接觸電阻。以下描述提供增大接觸面積從而有較低接觸電阻的不同示例實施方式。圖7A-7H描述了一個此類示例實施方式。在矽底材 201上形成複數個閘極堆疊 202，隨後形成源極/汲極凹槽203 (圖7A)。在圖示示例中，每個閘極堆疊202包含交替的矽奈米片204及矽鍺層205，且矽鍺層的末端設有內間隔件209 (例如SiO 2)，如上文類似的討論。
在某些實施方式中，矽緩衝件206a、206b可視需要分別磊晶生長在凹槽203內之奈米片204及底材201的面上(圖7B)。如前所述，緩衝件206a、206b可協助在MST超晶格薄膜形成之前減輕任何表面粗糙度，從而有助於防止或減少其中的缺陷。然後，可進行MST薄膜及頂蓋的形成(圖7C)，以分別在緩衝件206a、206b上界定出超晶格225a、225b及頂蓋層252a、252b (圖7D)，如上文所述。隨後，可使用硬光罩208在凹槽203內形成源極/汲極區207 (例如，Si:P)(圖7D)。同樣地，在圖示示例中，Si:P生長發生在頂蓋層252之上，但在某些實施方式中可省略此等頂蓋層。
接著，在硬光罩208內緣形成間隔件212，從而允許Si:P可被蝕刻，使得Si:P襯墊保留在溝槽203內部(圖7E)。之後，可在硬光罩208上進行金屬層210沉積並使其填滿溝槽203 (圖7F)，然後進行矽化及金屬去除(圖7G)，以沿著溝槽203的底部及側壁界定出一接觸襯墊211，隨後溝槽203可以金屬插塞(metal plug)213填充而完成接觸結構(圖7H)。如上文進一步討論，隨後可去除硬光罩208並進行額外處理步驟，以完成奈米片電晶體。
現在參考圖8A-8C，描述提供較低接觸電阻的另一示例實施方式。從圖6B所示結構開始，在硬光罩208’內緣接著形成間隔件212’，從而允許Si:P可被蝕刻，使得Si:P襯墊保留在溝槽203’內部(圖8A)。接着可在硬光罩208’上進行金屬層210’沉積並使其填充溝槽203’ (圖8B)，隨後進行矽化/金屬去除並形成金屬插塞213’ (圖8C)，如上所述。所得的結構類似於圖7H的結構，但本實施方式中省略了MST薄膜225及頂蓋層252。同樣地，隨後可去除硬光罩208’並進行額外處理步驟，以完成奈米片電晶體。
現在參考圖9A-9D描述提供較低接觸電阻的又另一示例實施方式。此方法始於類似圖7B的結構，但隨後以Si:P源極/汲極材料207’’填滿溝槽203’’ (圖9A)。接著，在硬光罩208”內緣形成間隔件212”，從而允許Si:P可被蝕刻，使得Si:P襯墊保留在溝槽203’內部(圖9B)。之後，可進行金屬沉積，接著進行矽化/金屬去除(圖9C)及形成金屬插塞 213’’ (圖9D)，如上所述。同樣地，隨後可去除硬光罩208’’並進行額外處理步驟，以完成奈米片電晶體。
現在參考圖10A-10D描述提供較低接觸電阻的又另一示例實施方式。此方法亦始於類似圖7B的結構，但進行Si:P源極/汲極材料207’’’的部分沉積以鋪襯(但不完全填滿)溝槽203’’’ (圖10A)。之後，可進行金屬210’’’沉積，接著進行矽化/金屬去除(圖10C)及形成金屬插塞 213’’’ (圖10D)，如上所述。同樣地，隨後可去除硬光罩208’’’並進行額外處理步驟，以完成奈米片電晶體。關於Si:P的部分沉積，應注意，此亦可用於上述實施方式(不論是否使用MST層)，而非以Si:P完全填滿溝槽。此外，在與圖10A-10D所示方法類似的另一方法中，除了該製程將始於類似圖6A的結構(亦即在Si:P部分沉積之前，不對奈米片203’’’進行矽凹槽處理)之外，所有繪示步驟皆相同。
可用於以下實施方式當中一或多者的示例尺寸包括：閘極高度= ~63nm； 閘極長度(Lg) = ~12nm；矽鍺層厚度= ~12.8nm；以及矽奈米片厚度= ~5nm。但應理解的是，在不同組構中可能有其他尺寸，熟習本發明所屬技術領域者當可理解。
熟習本發明所屬技術領域者將受益於本說明書揭示之內容及所附圖式，從而構思出各種修改例及其他實施方式。因此，應了解的是，本發明不限於本說明書所述特定實施方式，相關修改例及實施方式亦落入本案申請專利範圍所界定之範疇。
21, 21’:底材 25, 25’, 125a, 125a’, 125b, 125b’, 225a, 225b:超晶格 45a~45n, 45a’~45n-1’, 45n’:層群組 46, 46’:基底半導體單層 46a~46n, 46a’~46n-1’, 46n’:基底半導體部份 50, 50’:能帶修改層/ 非半導體單層 52, 52’, 152a, 152a’, 152b, 152b’, 252a, 252b:頂蓋層 61, 101, 101’, 201:矽底材 62, 102, 202:閘極堆疊 63, 103, 103’, 203, 203’, 203’’, 203’’’:凹槽/ 溝槽 64, 104, 104’, 204:矽奈米片 65, 105, 205:矽鍺層 67, 107, 107’, 207, 207’’, 207’’’:源極/汲極區 68, 108, 208, 208’, 208”, 208’’’:硬光罩 69, 109, 109’, 209:內間隔件 70, 210, 210’, 210’’’:金屬層 71:源極/汲極接點 106a, 106b, 206a, 206b:緩衝件 211:接觸襯墊 212, 212’, 212”:間隔件 213, 213’, 213’’, 213’’’:金屬插塞
圖1為依照一示例實施例之半導體元件用超晶格之放大概要剖視圖。
圖2為圖1所示超晶格之一部份之透視示意原子圖。
圖3為依照另一示例實施例之超晶格放大概要剖視圖。
圖4A-4E為一系列剖視圖，其概要繪示依照一示例實施例製造具有超晶格摻雜物阻擋層(superlattice dopant blocking layers)之奈米片電晶體(nanosheet transistor)的方法。
圖5A-5F為一系列剖視圖，其概要繪示依照一示例實施例製造具有超晶格摻雜物阻擋層之奈米片電晶體的另一方法。
圖6A-6D為一系列剖視圖，其概要繪示依照習知技術製造奈米片電晶體的常規方法。
圖7A-7H為一系列剖視圖，其概要繪示依照一示例實施例製造具有超晶格摻雜物阻擋層之奈米片電晶體並提供增大接觸面積(enhanced contact area)的另一方法。
圖8A-8C為一系列剖視圖，其概要繪示依照一示例實施例製造奈米片電晶體並提供增大接觸面積的又一方法。
圖9A-9D為一系列剖視圖，其概要繪示依照一示例實施例製造奈米片電晶體並提供增大接觸面積的又另一方法。
圖10A-10D為一系列剖視圖，其概要繪示依照一示例實施例製造奈米片電晶體並提供增大接觸面積的另一方法。
101’:矽底材
102’:閘極堆疊
104’:矽奈米片
105’:矽鍺層
107’:源極/汲極區
108’:硬光罩

Claims (16)

  1. 一種半導體元件，其包括： 一底材； 該底材上複數個隔開的閘極堆疊，該些閘極堆疊間界定出相應的溝槽，每個閘極堆疊包括交替的第一半導體材料層及第二半導體材料層，該些第二半導體材料層界定出多個奈米結構； 該些溝槽內部相應的源極/汲極區； 與該些第一半導體材料層橫向末端相鄰的相應絕緣區；以及 與該些奈米結構橫向末端相鄰並從相鄰的該些絕緣區之表面向外偏置之相應摻雜物阻擋超晶格，每個摻雜物阻擋超晶格包括複數個堆疊之層群組，各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。
  2. 如請求項1之半導體元件，其在每個奈米結構與相鄰的摻雜物阻擋超晶格之間更包括相應之一半導體緩衝層。
  3. 如請求項1之半導體元件，其在該底材與該些源極/汲極區之間包括相應之一橫向底部摻雜物阻擋超晶格，每個橫向底部摻雜物阻擋超晶格包括複數個堆疊之層群組，各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。
  4. 如請求項1之半導體元件，其中該第一半導體材料包括矽鍺。
  5. 如請求項1之半導體元件，其中該第二半導體材料包括矽。
  6. 如請求項1之半導體元件，其中該些源極/汲極區包括摻磷矽(Si:P)。
  7. 如請求項1之半導體元件，其中該些基底半導體單層包括矽。
  8. 如請求項1之半導體元件，其中該些非半導體單層包括氧。
  9. 一種用於製造一半導體元件之方法，包括： 在一底材上形成複數個隔開的閘極堆疊，該些閘極堆疊間界定出相應的溝槽，每個閘極堆疊包括交替的第一半導體材料層及第二半導體材料層，該些第二半導體材料層界定出多個奈米結構； 在該些溝槽內部形成相應的源極/汲極區； 形成與該些第一半導體材料層橫向末端相鄰的相應絕緣區；以及 形成與該些奈米結構橫向末端相鄰並從相鄰的該些絕緣區之表面向外偏置之相應摻雜物阻擋超晶格，每個摻雜物阻擋超晶格包括複數個堆疊之層群組，各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。
  10. 如請求項9之方法，其更包括在每個奈米結構與相鄰的摻雜物阻擋超晶格之間形成相應之一半導體緩衝層。
  11. 如請求項9之方法，其包括在該底材與該些源極/汲極區之間形成相應之一橫向底部摻雜物阻擋超晶格，每個橫向底部摻雜物阻擋超晶格包括複數個堆疊之層群組，各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。
  12. 如請求項9之方法，其中該第一半導體材料包括矽鍺。
  13. 如請求項9之方法，其中該第二半導體材料包括矽。
  14. 如請求項9之方法，其中該些源極/汲極區包括摻磷矽(Si:P)。
  15. 如請求項9之方法，其中該些基底半導體單層包括矽。
  16. 如請求項9之方法，其中該些非半導體單層包括氧。
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