TW202321869A - Power supply device - Google Patents

Abstract

A power supply device includes a bridge rectifier, a first capacitor, a transformer, a power switch element, an output stage circuit, an MCU (Microcontroller Unit), and a switch circuit. The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The transformer includes a main coil and a secondary coil. The main coil receives the rectified voltage. The secondary coil generates an induced voltage. The power switch element selectively couples the main coil to a ground voltage according to a clock voltage. The output stage circuit generates an output voltage according to the induced voltage. The MCU generates the clock voltage. The MCU and the switch circuit are configured to switch between a latch-off mode and an auto-recovery mode according to a selection voltage.

Description

Power Supplier

The present invention relates to a power supply, in particular to a power supply with switchable modes.

Currently, there are two types of protection mechanisms for power supplies. One is the Latch-off design, and the other is the Auto-recovery design. There is a shortcoming in the latch-off protection mechanism. , that is, when a fault occurs, the AC power supply must be plugged and unplugged before the normal operation can be resumed, which reduces the overall operating efficiency. On the other hand, if a gaming computer requires a large output current, it is easy to induce malfunction of the protection mechanism, which will affect the overall user experience. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the previous technology.

In a preferred embodiment, the present invention provides a power supply, comprising: a bridge rectifier, which generates a rectified potential according to a first input potential and a second input potential; a first capacitor, which stores the rectified potential; A transformer includes a primary coil and a secondary coil, wherein the primary coil is used to receive the rectified potential, and the secondary coil is used to generate an induced potential; a power switch selectively converts the The main coil is coupled to a ground potential; an output stage circuit generates an output potential according to the induced potential; a microcontroller generates the clock potential; and a switching circuit is coupled to the bridge rectifier and the second A capacitor, wherein the microcontroller and the switching circuit are switched between a latch-off mode and an auto-recovery mode according to a selection voltage.

In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node for receiving the first Input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode, with an anode and a cathode, wherein the second diode of the the anode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode , wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; wherein the first capacitor has a first One terminal and a second terminal, the first terminal of the first capacitor is coupled to the first node, and the second terminal of the first capacitor is coupled to the ground potential.

In some embodiments, the transformer further has a built-in magnetizing inductor, the main winding has a first end and a second end, the first end of the main winding is coupled to the first node to receive the rectified potential, the second end of the main coil is coupled to a second node, the magnetizing inductor has a first end and a second end, the first end of the magnetizing inductor is coupled to the first node , and the second end of the magnetizing inductor is coupled to the second node, the secondary coil has a first end and a second end, the first end of the secondary coil is coupled to a third node to output the induced potential, and the second end of the secondary coil is coupled to a common node.

In some embodiments, the power switch includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the time pulse potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the second node.

In some embodiments, the output stage circuit includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the third node to receive the induced potential, The cathode of the fifth diode is coupled to an output node to output the output potential; and a second capacitor has a first end and a second end, wherein the first end of the second capacitor is coupled to the output node, and the second end of the second capacitor is coupled to the common node.

In some embodiments, the microcontroller further generates a control potential to control the switching circuit according to the selection potential, and there is a delay time between the control potential and the selection potential.

In some embodiments, the switching circuit includes: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to a first control node, the first terminal of the second transistor is coupled to a fourth node, and the second terminal of the second transistor is coupled to the first node; a first resistor has a a first end and a second end, wherein the first end of the first resistor is coupled to the fourth node, and the second end of the first resistor is coupled to a first switching node for outputting a first switching potential to the microcontroller; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the first switching node, and the second end of the second resistor is coupled to the ground potential; and a blocking resistor has a first end and a second end, wherein the first end of the blocking resistor is coupled to The first node receives the rectified potential, and the second end of the blocking resistor is coupled to the first control node.

In some embodiments, the switching circuit further includes: a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to a first terminal two control nodes to receive the control potential, the first terminal of the third transistor is coupled to a fifth node, and the second terminal of the third transistor is coupled to the first node; a first terminal of the third transistor is coupled to the first node; Three resistors having a first end and a second end, wherein the first end of the third resistor is coupled to the fifth node, and the second end of the third resistor is coupled to a second switching node to output a second switching potential to the microcontroller; and a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to to the second switching node, and the second end of the fourth resistor is coupled to the ground potential.

In some embodiments, the switching circuit further includes: a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is coupled to the first terminal two control nodes to receive the control potential, the first end of the fourth transistor is coupled to the ground potential, and the second end of the fourth transistor is coupled to the first control node; and a A fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is coupled to the first control node, and the second end of the fifth resistor is coupled to connected to this ground potential.

In some embodiments, if the first switching potential is a high logic level and the second switching potential is a low logic level, the microcontroller and the switching circuit will switch to the latch off mode, and if the If the first switching potential is a low logic level and the second switching potential is a high logic level, then the microcontroller and the switching circuit will switch to the automatic recovery mode.

In order to make the purpose, features and advantages of the present invention more comprehensible, specific embodiments of the present invention are listed below, together with the accompanying drawings, for detailed description as follows.

Certain terms are used in the specification and claims to refer to particular elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This description and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The words "comprising" and "comprising" mentioned throughout the specification and scope of patent application are open-ended terms, so they should be interpreted as "including but not limited to". The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if it is described that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. Two devices.

FIG. 1 is a schematic diagram of a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in Figure 1, the power supply 100 includes: a bridge rectifier 110, a first capacitor C1, a transformer 120, a power switch 130, an output stage circuit 140, and a microcontroller (Microcontroller Unit, MCU) 150, and a switching circuit 160. It should be noted that although not shown in FIG. 1 , the power supply 100 may further include other components, such as a voltage regulator and/or a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2, wherein one of any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2 AC voltage. For example, the frequency of the AC voltage can be about 50Hz or 60Hz, and the root mean square value of the AC voltage can be about 90V to 264V, but it is not limited thereto. The first capacitor C1 can be used to store the rectified potential VR. The transformer 120 includes a primary coil 121 and a secondary coil 122 . The primary coil 121 can be located on one side of the transformer 120 , and the secondary coil 122 can be located on the opposite side of the transformer 120 . The primary coil 121 can receive the rectified potential VR, and in response to the rectified potential VR, the secondary coil 122 can generate an induced potential VS. The power switch 130 can selectively couple the main coil 121 to a ground potential VSS (eg, 0V) according to a clock potential VA. For example, if the clock potential VA is a high logic level (ie, logic “1”), the power switch 130 can couple the main coil 121 to the ground potential VSS (ie, the power switch 130 can be approximately a short circuit path); on the contrary, if the clock potential VA is a low logic level (that is, logic "0"), the power switch 130 will not couple the main coil 121 to the ground potential VSS (that is, the power switch 130 can be approximated as an open path). The output stage circuit 140 can generate an output potential VOUT according to the sensing potential VS. For example, the output potential VOUT can be a DC potential, and its potential level can be from 18V to 22V, but it is not limited thereto. The microcontroller 150 can generate the clock potential VA. The switching circuit 160 is coupled to the bridge rectifier 110 and the first capacitor C1. It should be noted that the microcontroller 150 and the switch circuit 160 can be switched between a latch-off mode (Latch-off Mode) PLM and an auto-recovery mode (Auto-recovery Mode) AUM according to a selection potential VE. For example, the selection potential VE can be generated according to a user input. Under this design, the user can choose between the latch closing mode PLM and the automatic recovery mode AUM according to different operating conditions. Therefore, even if the related mobile device has relatively large power consumption (for example: playing 3D games or overclocking operation), the power supply 100 of the present invention can prevent the over-current protection (Over Current Protection, OCP) mechanism from being falsely triggered , so that the operation fluency of the mobile device and the actual experience of the user can be greatly improved.

The following embodiments will introduce the detailed structure and operation of the power supply 100 . It must be understood that these drawings and descriptions are examples only and are not intended to limit the scope of the present invention.

FIG. 2 is a schematic diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first capacitor C1, and a transformer 220 , a power switcher 230 , an output stage circuit 240 , a microcontroller 250 , and a switching circuit 260 . The first input node NIN1 and the second input node NIN2 of the power supply 200 are respectively used to receive a first input potential VIN1 and a second input potential VIN2 . The output node NOUT of the power supply 200 can be used to output an output potential VOUT.

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 To output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2 , and the cathode of the second diode D2 is coupled to the first node N1 . The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1 . The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The first capacitor C1 has a first end and a second end, wherein the first end of the first capacitor C1 is coupled to the first node N1 to receive and store the rectified potential VR, and the second end of the first capacitor C1 is Coupled to ground potential VSS.

The transformer 220 includes a primary coil 221 and a secondary coil 222, wherein the transformer 220 can further have a built-in magnetizing inductor LM. The magnetizing inductor LM can be an inherent component produced by the manufacture of the transformer 220 , and it is not an external independent component. Both the primary coil 221 and the magnetizing inductor LM can be located on the same side of the transformer 220 (for example: the primary side), and the secondary coil 222 can be located on the opposite side of the transformer 220 (for example: the secondary side, which can be connected to the primary side). isolated). The main coil 221 has a first end and a second end, wherein the first end of the main coil 221 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the main coil 221 is coupled to a first node N1. Two nodes N2. The magnetizing inductor LM has a first terminal and a second terminal, wherein the first terminal of the magnetizing inductor LM is coupled to the first node N1, and the second terminal of the magnetizing inductor LM is coupled to the second node N2 . The secondary coil 222 has a first end and a second end, wherein the first end of the secondary coil 222 is coupled to a third node N3 to output an induced potential VS, and the second end of the secondary coil 222 is coupled to A common node NCM. For example, the common node NCM can be regarded as another ground potential, which can be the same as or different from the aforementioned ground potential VSS.

The power switch 230 includes a first transistor M1. For example, the first transistor M1 may be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The first transistor M1 has a control end (for example: a gate), a first end (for example: a source), and a second end (for example: a drain), wherein the control of the first transistor M1 The terminal is used to receive a clock potential VA, the first terminal of the first transistor M1 is coupled to the ground potential VSS, and the second terminal of the first transistor M1 is coupled to the second node N2. For example, if the clock potential VA is at a high logic level, the first transistor M1 will be enabled; otherwise, if the clock potential VA is at a low logic level, the first transistor M1 will be disabled.

The output stage circuit 240 includes a fifth diode D5 and a second capacitor C2. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the third node N3 to receive the induced potential VS, and the cathode of the fifth diode D5 is coupled to the output Node NOUT. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the common node NCM.

The microcontroller 250 can generate the aforementioned clock potential VA. For example, the microcontroller 250 may be implemented by a Pulse Width Modulation Integrated Circuit (PWM IC), but it is not limited thereto. The microcontroller 250 can further generate a control potential VC according to a selection potential VE to control the switching circuit 260 so that the power supply 200 can switch between a latch-off mode PLM and an automatic recovery mode AUM. In some embodiments, the selection potential VE comes from a mobile device 290 such as a notebook computer. The power supply 200 can supply power to the mobile device 290 by outputting the potential VOUT. Specifically, the mobile device 290 may include a main circuit board 292, and the main circuit board 292 may include an embedded controller (Embedded Controller, EC) 294, wherein the embedded controller 294 may generate the aforementioned The selection potential VE. It must be understood that the mobile device 290 does not belong to any part of the power supply 200 .

The switching circuit 260 includes a second transistor M2, a third transistor M3, a fourth transistor M4, a blocking resistor RG, a first resistor R1, a second resistor R2, and a third resistor R3, a fourth resistor R4, and a fifth resistor R5. For example, each of the second transistor M2 , the third transistor M3 , and the fourth transistor M4 can be an N-type metal oxide semiconductor field effect transistor.

The second transistor M2 has a control end (for example: a gate), a first end (for example: a source), and a second end (for example: a drain), wherein the control of the second transistor M2 The terminal is coupled to a first control node NC1, the first terminal of the second transistor M2 is coupled to a fourth node N4, and the second terminal of the second transistor M2 is coupled to the first node N1 . The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is coupled to the fourth node N4, and the second end of the first resistor R1 is coupled to a The first switch node NW1 outputs a first switch potential VW1 to the microcontroller 250 . The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the first switching node NW1, and the second end of the second resistor R2 is coupled to Ground potential VSS. The blocking resistor RG has a first end and a second end, wherein the first end of the blocking resistor RG is coupled to the first node N1 to receive the rectified potential VR, and the second end of the blocking resistor RG is coupled to to the first control node NC1.

The third transistor M3 has a control end (for example: a gate), a first end (for example: a source), and a second end (for example: a drain), wherein the control of the third transistor M3 The terminal is coupled to a second control node NC2 to receive the control potential VC, the first terminal of the third transistor M3 is coupled to a fifth node N5, and the second terminal of the third transistor M3 is coupled to The first node N1. The third resistor R3 has a first end and a second end, wherein the first end of the third resistor R3 is coupled to the fifth node N5, and the second end of the third resistor R3 is coupled to a The second switch node NW2 outputs a second switch potential VW2 to the microcontroller 250 . The fourth resistor R4 has a first end and a second end, wherein the first end of the fourth resistor R4 is coupled to the second switching node NW2, and the second end of the fourth resistor R4 is coupled to Ground potential VSS.

The fourth transistor M4 has a control end (for example: a gate), a first end (for example: a source), and a second end (for example: a drain), wherein the control of the fourth transistor M4 The terminal is coupled to the second control node NC2 to receive the control potential VC, the first terminal of the fourth transistor M4 is coupled to the ground potential VSS, and the second terminal of the fourth transistor M4 is coupled to the first control node. Node NC1. The fifth resistor R5 has a first end and a second end, wherein the first end of the fifth resistor R5 is coupled to the first control node NC1, and the second end of the fifth resistor R5 is coupled to Ground potential VSS.

In some embodiments, the operation principle of the power supply 200 can be as follows. Roughly speaking, if the first switching potential VW1 is at a high logic level and the second switching potential VW2 is at a low logic level, then the microcontroller 250 and the switching circuit 260 of the power supply 200 will switch to the latch-off mode PLM . Conversely, if the first switching potential VW1 is at a low logic level and the second switching potential VW2 is at a high logic level, the microcontroller 250 and the switching circuit 260 of the power supply 200 can switch to the automatic recovery mode AUM.

At the beginning, when the bridge rectifier 210 receives the first input potential VIN1 and the second input potential VIN2, the relatively high rectification potential VR can turn on the second transistor M2, and can pull the first switching potential VW1 to a high logic level allow. At this time, the relatively low control potential VC can simultaneously turn off the third transistor M3 and the fourth transistor M4, so that the second switching potential VW2 is maintained at a low logic level. In other words, the power supply 200 can initially operate in the latch-off mode PLM.

If the user wants to play 3D games (or perform overclocking operation) on the mobile device 290, he can use the embedded controller 294 to output the selection potential VE of a high logic level to the microcontroller 290 to pull up the control Potential VC. It should be noted that the control potential VC and the selection potential VE can have the same waveform, but the control potential VC can be regarded as the selection potential VE and then delayed by a delay time TD. Since the control potential VC is relatively high, the third transistor M3 and the fourth transistor M4 can be turned on at the same time, wherein a short circuit path formed by the fourth transistor M4 can close the second transistor M2, so that the first switching The potential VW1 can drop to a low logic level. In addition, the relatively high rectification potential VR can pull the second switching potential VW2 to a high logic level. In response to the selection potential VE of the high logic level, the power supply 200 can be switched from the latch-off mode PLM to the automatic recovery mode AUM. In short, the potential relationships of the power supply 200 can be shown in Table 1 below:

The first switching potential VW1 Second switching potential VW2 Select potential VE Control potential VC Latch Off Mode PLM high logic level low logic level low logic level Low logic level (with delay time TD) Auto Recovery Mode AUM low logic level high logic level high logic level High logic level (with delay time TD) Table 1: Potential Relationships of Power Supply 200

FIG. 3A is a potential waveform diagram of the power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 3A, if the power supply 200 receives the selection potential VE of a high logic level, it can switch from the latch-off mode PLM to the automatic recovery mode AUM. FIG. 3B is a potential waveform diagram of the power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 3B , if the power supply 200 receives the selection potential VE of a low logic level, it can switch from the automatic recovery mode AUM to the latch-off mode PLM. According to the measurement results in Figures 3A and 3B, the aforementioned delay time TD can be used as a buffer switching time between the first switching potential VW1 and the second switching potential VW2, which can prevent the power supply 200 from entering the latch-off mode at the same time PLM and automatic recovery mode AUM, which can reduce the overall probability of malfunction.

FIG. 4 shows a signal waveform diagram of the power supply 200 in the latch-off mode PLM according to an embodiment of the present invention. At a first time point T1, the output current IOUT of the power supply 200 exceeds a critical current ITH, thus triggering the overcurrent protection mechanism in the latch-off mode PLM. At this time, both the output potential VOUT and the output current IOUT rapidly drop to 0. Then, at a specific time point TC, the AC power coupled to the power supply 200 is removed. At a second time point T2, the aforementioned AC power is re-coupled back to the power supply 200 and the original over-current protection is removed, so the output potential VOUT and the output current IOUT can gradually return to normal levels. It must be understood that although the latch-off mode PLM can provide higher security, it is also easy to cause malfunction of the over-current protection mechanism.

FIG. 5 shows a signal waveform diagram of the power supply 200 in the automatic recovery mode AUM according to an embodiment of the present invention. At the first time point T1, the output current IOUT of the power supply 200 exceeds the critical current ITH, thus triggering the overcurrent protection mechanism in the automatic recovery mode AUM. At this time, both the output potential VOUT and the output current IOUT rapidly drop to 0, but the output current IOUT still has some test glitches during the overcurrent protection period. Then, at the second time point T2, the above-mentioned over-current protection has been eliminated (but the AC power supply does not need to be re-plugged), so the output potential VOUT and the output current IOUT can gradually return to normal levels. In some embodiments, the power supply 200 can switch to the automatic recovery mode AUM when the mobile device 290 has a large power consumption (for example: playing 3D games or overclocking operation), and can switch to the automatic recovery mode AUM when the mobile device 290 has a small power consumption. (Example: Word Processing) Switch to Latch Off Mode PLM.

FIG. 6 is a schematic diagram showing a mobile device 290 according to an embodiment of the present invention. In the embodiment of FIG. 6 , the mobile device 290 includes a display 296 that can display a text area 298 . The text field 298 can be used to describe the current state of the power supply 200 . For example, the text area 298 can describe the instantaneous state of the output current IOUT, whether the over-current protection mechanism is triggered, the current over-current protection mechanism is the latch-off mode PLM or the automatic recovery mode AUM, or (and) the current over-current The protection mechanism is still switching or has been switched, but it is not limited to this.

In some embodiments, the component parameters of the power supply 200 may be as follows. The inductance of the magnetizing inductor LM can be between 432 μH and 528 μH, preferably 480 μH. The capacitance of the first capacitor C1 can range from 96 μF to 144 μF, preferably 120 μF. The capacitance of the second capacitor C2 can range from 544 μF to 748 μF, preferably 680 μF. The resistance value of the first resistor R1 can be between 73.15KΩ and 80.85KΩ, preferably 77KΩ. The resistance value of the second resistor R2 can be between 2.85KΩ and 3.15KΩ, preferably 3KΩ. The resistance value of the third resistor R3 can be between 73.15KΩ and 80.85KΩ, preferably 77KΩ. The resistance value of the fourth resistor R4 can be between 2.85KΩ and 3.15KΩ, preferably 3KΩ. The resistance value of the fifth resistor R5 can be between 85KΩ and 115KΩ, preferably 100KΩ. The resistance value of the blocking resistor RG can be between 9.5KΩ and 10.5KΩ, preferably 10KΩ. The turn ratio of the primary coil 221 to the secondary coil 222 can be between 1 and 100, preferably 20. The delay time TD between the control potential VC and the selection potential VE can be greater than or equal to 1 ms. The above parameter ranges are obtained according to the results of multiple experiments, which help to optimize the smoothness of the operation of the power supply 200 .

The present invention proposes a novel power supply. According to actual measurement results, the power supply using the aforementioned design can be switched between the latch-off mode and the automatic recovery mode according to different requirements, so it is very suitable for use in various electronic devices.

It should be noted that the potential, current, resistance value, inductance value, capacitance value, and other component parameters mentioned above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the states shown in FIGS. 1-6. The present invention may only include any one or multiple features of any one or multiple embodiments of Figures 1-6. In other words, not all the illustrated features must be implemented in the power supply of the present invention at the same time. Although the embodiment of the present invention uses a metal oxide half field effect transistor as an example, the present invention is not limited thereto, and those skilled in the art can use other types of transistors, such as junction field effect transistors, or fin Type field effect transistors, etc., and will not affect the effect of the present invention.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to mark and distinguish between two The different elements of the name.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the scope of the appended patent application.

100,200: Power supply 110,210: bridge rectifier 120,220: transformer 121,221: main coil 122,222: secondary coil 130,230: Power Switcher 140,240: output stage circuit 150,250: microcontroller 160,260: switching circuit 290: Mobile Devices 292: Main circuit board 294: Embedded Controller 296:Display 298: Text area AUM: Auto Recovery Mode C1: first capacitor C2: second capacitor D1: the first diode D2: second diode D3: The third diode D4: The fourth diode D5: fifth diode IOUT: output current ITH: critical current LM: Exciting inductor M1: the first transistor M2: second transistor M3: The third transistor M4: The fourth transistor N1: the first node N2: second node N3: the third node N4: the fourth node N5: fifth node NC1: the first control node NC2: Second Control Node NCM: common node NIN1: the first input node NIN2: Second input node NOUT: output node NW1: the first switching node NW2: second switching node PLM: Latch Off Mode R1: first resistor R2: second resistor R3: Third resistor R4: Fourth resistor R5: fifth resistor RG: blocking resistor T1: the first time point T2: second time point TC: specific point in time TD: delay time VA: clock potential VC: control potential VE: selection potential VIN1: the first input potential VIN2: the second input potential VOUT: output potential VR: rectification potential VS: Induction potential VSS: ground potential VW1: the first switching potential VW2: the second switching potential

FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing a power supply according to an embodiment of the present invention. FIG. 3A is a potential waveform diagram of a power supply according to an embodiment of the present invention. FIG. 3B is a potential waveform diagram of the power supply according to an embodiment of the present invention. FIG. 4 shows a signal waveform diagram of the power supply in the latch-off mode according to an embodiment of the present invention. FIG. 5 shows a signal waveform diagram of the power supply in the automatic recovery mode according to an embodiment of the present invention. FIG. 6 is a schematic diagram showing a mobile device according to an embodiment of the present invention.

100: Power supply

110: Bridge rectifier

120: Transformer

121: Main coil

122: secondary coil

130: Power switcher

140: Output stage circuit

150: microcontroller

160: switching circuit

AUM: Auto Recovery Mode

C1: first capacitor

PLM: Latch Off Mode

VA: clock potential

VE: selection potential

VIN1: the first input potential

VIN2: the second input potential

VOUT: output potential

VR: rectification potential

VS: Induction potential

VSS: ground potential

Claims (10)

A power supply, comprising: a bridge rectifier for generating a rectified potential according to a first input potential and a second input potential; a first capacitor for storing the rectified potential; a transformer comprising a primary coil and a secondary coil, wherein the primary coil is used to receive the rectified potential and the secondary coil is used to generate an induced potential; a power switch selectively couples the main coil to a ground potential according to a clock potential; an output stage circuit, which generates an output potential according to the induced potential; a microcontroller, generating the clock potential; and A switching circuit coupled to the bridge rectifier and the first capacitor, wherein the microcontroller and the switching circuit are switched between a latch-off mode and an auto-recovery mode according to a selection voltage. The power supply as claimed in item 1, wherein the bridge rectifier comprises: A first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the first diode of the the cathode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the second diode of the a cathode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential and the cathode of the fourth diode is coupled to the second input node; wherein the first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the ground potential. The power supply as described in claim 2, wherein the transformer further has a built-in magnetizing inductor, the main coil has a first end and a second end, and the first end of the main coil is coupled to the second end a node to receive the rectified potential, the second end of the main coil is coupled to a second node, the exciting inductor has a first end and a second end, the first end of the exciting inductor is coupled connected to the first node, and the second end of the magnetizing inductor is coupled to the second node, the secondary coil has a first end and a second end, the first end of the secondary coil is coupled connected to a third node to output the induced potential, and the second end of the secondary coil is coupled to a common node. The power supply as described in claim 3, wherein the power switch includes: A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the clock potential, and the first transistor of the first transistor A terminal is coupled to the ground potential, and the second terminal of the first transistor is coupled to the second node. The power supply as claimed in item 3, wherein the output stage circuit includes: A fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the third node to receive the induced potential, and the cathode of the fifth diode is coupled to connected to an output node to output the output potential; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node. The power supply according to claim 2, wherein the microcontroller further generates a control potential according to the selection potential to control the switching circuit, and there is a delay time between the control potential and the selection potential. The power supply according to claim 6, wherein the switching circuit includes: A second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to a first control node, and the first terminal of the second transistor one end is coupled to a fourth node, and the second end of the second transistor is coupled to the first node; A first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the fourth node, and the second end of the first resistor is coupled to connected to a first switching node to output a first switching potential to the microcontroller; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the first switching node, and the second end of the second resistor is coupled to the ground potential; and A blocking resistor having a first end and a second end, wherein the first end of the blocking resistor is coupled to the first node to receive the rectified potential, and the second end of the blocking resistor is coupled to the first control node. The power supply as described in Claim 7, wherein the switching circuit further includes: A third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to a second control node to receive the control potential, the third the first terminal of the transistor is coupled to a fifth node, and the second terminal of the third transistor is coupled to the first node; A third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the fifth node, and the second end of the third resistor is coupled to connected to a second switching node to output a second switching potential to the microcontroller; and a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the second switching node, and the second end of the fourth resistor is coupled to this ground potential. The power supply as described in Claim 8, wherein the switching circuit further includes: A fourth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is coupled to the second control node to receive the control potential, the fourth the first terminal of the transistor is coupled to the ground potential, and the second terminal of the fourth transistor is coupled to the first control node; and a fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is coupled to the first control node, and the second end of the fifth resistor is coupled to this ground potential. The power supply according to claim 8, wherein if the first switching potential is a high logic level and the second switching potential is a low logic level, the microcontroller and the switching circuit will switch to the latch shutdown mode, and if the first switching potential is a low logic level and the second switching potential is a high logic level, then the microcontroller and the switching circuit will switch to the automatic recovery mode.

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